JPH04299617A - A/d conversion system - Google Patents

Abstract

PURPOSE:To revise the sampling rate and to prevent production of drift in an offset as the result of conversion. CONSTITUTION:A latch circuit 4 is provided just after an A/D converter 3. A sampling clock C1 whose frequency is always the same is inputted to the A/D converter 3 and a clock C2 whose frequency is one over an optional integer of the frequency of the sampling clock C1 given to the A/D converter 3 is applied to the post stage latch circuit 4 so that the latch timing of the post-stage latch circuit 4 is varied while the sampling rate of the A/D converter 3 is made constant thereby varying the sampling rate equivalently.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A/D conversion system with a variable sampling rate.

0002

2. Description of the Related Art Conventionally, this type of A/D conversion system has been a system in which the frequency of a sampling clock input to an A/D converter is changed when changing the sampling rate.

0003

[Problem to be solved by the invention] The above-mentioned conventional A/D
The conversion method has the disadvantage that if the frequency of the sampling clock is changed when changing the sampling rate, an offset drift occurs in the A/D converter output data.

An object of the present invention is to provide an A/D conversion method that can prevent offset drift from occurring in output data when the sampling rate is changed.

[0005]

[Means for Solving the Problems] The A/D conversion method of the present invention samples an input analog signal at a fixed first sampling rate that is not lower than the highest sampling rate in a variable range of required sampling rates. It includes an A/D converter that digitizes, and a latch circuit that latches output data of the A/D converter at a second sampling rate that is the required sampling rate.

The A/D conversion system of the present invention also includes a source clock generation circuit that generates a first clock having the first sampling rate and supplies it to the A/D converter; a clock rate switching circuit that receives the first clock from a generation circuit, divides the frequency at a variable frequency division ratio, generates a second clock at the second sampling rate, and supplies the generated second clock to the latch circuit. may be configured.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In the embodiment shown in FIG. 1, an original clock generation circuit 1 generates a clock C1 of the highest frequency used in the device and supplies it to a clock rate switching circuit 2. The clock rate switching circuit 2 receives the input clock C1.
is supplied as is to the A/D converter 3, and the clock C1
is divided by a variable frequency division ratio to generate a clock C2 of a required sampling rate, and the clock C2 is supplied to the latch circuit 4. The A/D converter 3 converts the input analog signal into a digital signal using the input clock C1 as a sampling clock, and outputs the digital signal to the latch circuit 4. The latch circuit 4 latches the output data of the A/D converter 3 at the timing of the input clock C2, and outputs output data whose sampling rate is equivalently changed to a required sampling rate.

0010

[Effects of the Invention] As explained above, the present invention operates an A/D converter that converts an analog signal into a digital signal in a sampling operation using a fixed clock, and the digital signal output of this A/D converter is provided immediately after. By latching with a variable timing using a latch circuit, there is an effect that the sampling rate can be made variable equivalently while essentially eliminating offset drift of output data caused by switching the sampling rate.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

[Explanation of symbols]

1 Original clock generation circuit 2 Clock rate switching circuit 3 A/
D converter 4 latch circuit

Claims (2)

[Claims] Claim 1: A fixed first sampling rate not lower than the highest sampling rate in a variable range of required sampling rates.
an A/D converter that samples and digitizes an input analog signal at a sampling rate of An A/D conversion method characterized by: 2. A first sampling rate of the first sampling rate.
an original clock generating circuit that generates a clock and supplies it to the A/D converter; 2. The A/D conversion system according to claim 1, further comprising: a clock rate switching circuit that generates a second clock having a sampling rate of 1 and supplies the second clock to the latch circuit.