JPS61283231A - Loop control circuit - Google Patents

Abstract

PURPOSE:To attain stable operation to a controlled system where the sample period T changes over 10 times by integrating an error voltage synchronously with the sampling timing and obtained while being gated at a prescribed time below the sample period. CONSTITUTION:Even when the sample period T changers, an output gain of an integration device 6 is unchanged by allowing a monostable multivibrator circuit 11 to turn on a gate 12 synchronously with the sampling timing so as to obtain the stable control system. That is, the output of the integration device 6 is independently of the sample period T but depends on a prescribed time t(T>=t). Even when the sample period T is changed, the gain to the error voltage Er is kept constant so as to realize a stable loop control circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a sample value controlled loop control circuit having a variable repetition period. Then, the voltages from the sample 2-2 and the sample hold 3, which open and close at regular intervals, are used to obtain an error voltage, which is the difference from the reference voltage 5, using a subtracter 4, and the error voltage is input to an integrator 6. Many of them were getting output to A.

Problems to be Solved by the Invention However, in the conventional configuration, for purposes where the input frequency, that is, the sampling period T changes by a factor of two or more, the gain G to the controlled object changes, making stable control difficult. there were.

In other words, it is difficult for conventional circuits to be used for purposes in which the sampling period T changes.

The present invention has been made in view of the above, and an object of the present invention is to provide a loop control circuit that has a simple configuration and operates stably even for a controlled object in which the sampling period T changes by a factor of 10 or more. It is said that

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention integrates the voltage obtained by further gating the error output from the subtracter at a constant time equal to or less than the sampling period in synchronization with the sampling timing. It is equipped with a configuration to do this.

Effect of the Invention With the above-described configuration, the present invention can obtain a constant loop gain even if the sampling period T changes by gating the output from the subtracter by a time t that is less than or equal to the input sampling period T. It is possible to realize stable loop control operation.

Embodiment FIG. 1 shows an embodiment of the loop control circuit of the present invention, and is an example applied to a time code reader used in a commercial VTR.

The time code is a pie-phase signal as shown in Figure 2(b), and if there is a phase change between the clocks in Figure 2(f), it has a value of '1'', otherwise it has a value of 0'', It has a digital value as shown in the figure (-). 1 is the input signal source as shown in Figure 2(b)
A signal indicating K is output. Reference numeral 9 denotes a timing generation circuit which generates a pulse every time the phase of the input terminal 94 connected to the output of the signal source 1 changes to generate the pulse shown in FIG. 2(C). Furthermore, from the sawtooth wave input from the input terminal 96, a pulse as shown in FIG. 2(e), which is the 76th percentile pulse of the clock, is created. ), the clock shown in FIG. 2(f) is obtained. Based on the clock, timings for each part are created and output to output terminals 91, 92, and 93.

3 is the sample hold, 13 capacitors and 10
The maximum voltage of the sawtooth wave shown in FIG. 2(d) created by the discharger is output to the subtracter 4. The subtracter 4 outputs the difference between the maximum voltage of the sawtooth wave and the reference voltage 6 to an output terminal 43 as an error voltage Er. Reference numeral 12 denotes a gate, which sends the error voltage Er to the integrator only during the period when the output from the monostable circuit 11 is 1''. 1'' is sent to the gate 12 for a time t (T≧t). The integrator 6 inputs the error voltage Er to the gate 12.
Integrates only while is on. 8 is a voltage-current conversion circuit, which inputs the output voltage from the integrator 6 to a voltage input terminal 81 and outputs it to a current output terminal 82 as a constant current i. The capacitor 13 creates a sawtooth wave as shown in FIG. 2 (-) using this constant current i.

As described above, according to this embodiment, even if the sampling period T changes, the output gain of the integrator 6 does not change because the monostable circuit 11 turns on the gate 12 in synchronization with the tenbling timing. A stable control system can be obtained.

In other words, in the conventional configuration, the output of the integrator 6 becomes a large output even for the same error voltage Er, and conversely, if it becomes short,
This results in a small output. However, the sample period T
It is determined by a certain time t (T≧t) regardless of the time period. Even when the sampling period T changes by -br, the gain for the error voltage Er is kept constant, making it possible to realize a stable loop control circuit.

Effects of the Invention As described above, according to the present invention, it is possible to realize a loop control circuit that operates stably even when the sampling period changes by a factor of 10 or more with an extremely simple circuit configuration, and is extremely useful in practice. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a loop control circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram of essential parts of the present invention, and FIG. 3 is a block diagram of a conventional loop control circuit. 3...Sample hold, 4...Group/subtractor,
6...Reference voltage, 6...Integrator, 8...
... Voltage-current conversion circuit, 9... Timing creation circuit, 1o... Old... Discharger, 11... Monostable circuit, 12... Old... Gate, 13... ...Capacitor. Name of agent: Patent attorney Toshio Nakao and 1 other person 40
- Mosquito t, # (CL) 'O' ” ”o'
@f'→Intercostal Figure 3

Claims (1)

[Claims] An error voltage obtained from a difference between a reference voltage and a sample-and-hold voltage of an output voltage from a controlled object operated by a control voltage is integrated, and the integrated output is used as the control voltage, and the error voltage is used as a sampling timing. A loop control circuit that is synchronized and integrates the voltage obtained by gate at a constant time less than the sampling period.