JPH0472917A - Sampling phase locked loop circuit - Google Patents

Abstract

PURPOSE:To allow the pulse width to satisfy the phase locked range by converting the output signal of a voltage controlled oscillator into a digital signal at an A/D converter, inputting the signal to a latch circuit, and converting the output signal into a D/A converter to control the voltage controlled oscillator. CONSTITUTION:The output signal of a voltage controlled oscillator 5 is inputted to an A/D converter and the output signal of the voltage controlled oscillator 5 is converted into a digital signal at an A/D converter 2. Then the output signal of the A/D converter 2 and the output signal of a frequency divider circuit 1 are inputted to a latch circuit 3. The output digital signal from the latch circuit 3 is inputted to a D/A converter 4, in which the signal is converted into an analog signal, the output signal of the D/A converter 4 is inputted to the voltage controlled oscillator 5, which is controlled. Thus, the synchronization range is not susceptible to the effect of a pulse width of an output signal of a pulse wave generating circuit and stable phase locked range is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase-locked circuit, and particularly to a sampling phase-locked circuit.

[Conventional technology]

An example of a conventional sampling phase synchronization circuit is shown in FIG. 3 and will be described.

As shown in FIG. 3, the conventional sampling phase-locked circuit is composed of an analog circuit, and the output signal of the frequency dividing circuit 6 (see FIG. 4 (,)) is connected to a capacitor 8 and a resistor 9.
and is input to a pulse wave generation circuit 7 composed of a diode 10 and a transistor 11. The output signal of this pulse wave generation circuit 7 becomes as shown in FIG. The output signal is input to the gate of the field effect transistor (hereinafter referred to as FET) 13, and the change in the drain-source resistance value RD due to the gate voltage V of the FET 13, that is, the gate voltage Va of the FET By utilizing the change as shown in FIG. 5, which is an explanatory diagram showing an example of the drain-source resistance value aos(p) characteristic according to The output signal of the voltage controlled oscillator 19 (see Φ in FIG. 4) is sampled by the FET 13. The voltage sampled by this FET13 is transferred to capacitors 15 and 16 and resistor 1.
7, this holding circuit 1
4 (see Figure 4(d)), the resistor 18
The voltage controlled oscillator 19 was controlled via the voltage controlled oscillator 19.

[Problem to be solved by the invention]

This conventional sampling phase synchronization circuit has a problem in that the pulse width of the pulse signal, which is the output signal of the pulse wave generation circuit, affects the synchronization range, and if the pulse width is wide, the required synchronization range cannot be satisfied.

In addition, since the holding circuit is configured as shown in FIG.
During the next sampling, the output signal of the holding circuit is
There was a problem in that a voltage drop occurred as shown in Figure (d).

[Means to solve the problem]

The sampling phase synchronized circuit of the present invention includes a frequency dividing circuit that receives a reference signal as an input, an analog-to-digital converter that converts an output signal of a voltage-controlled oscillator into a digital signal, an output signal of this analog-to-digital converter, and the above-mentioned. A holding circuit that receives the output signal of the frequency divider circuit and outputs and holds the input digital signal when a clock signal is input, and a digital-to-analog converter that converts the output signal of this holding circuit into an analog signal. is provided, and the voltage controlled oscillator is controlled by the output signal of the digital-to-analog converter.

[Effect]

In the present invention, the output signal of the voltage controlled oscillator is converted into a digital signal by an analog-to-digital converter, this digital signal is inputted to the other input terminal of the holding circuit, and the output signal of this holding circuit is converted into a digital signal. This analog signal is used to control the voltage controlled oscillator.

〔Example〕

Embodiments of the present invention will be described in detail below based on the drawings.

FIG. 1 is a block diagram showing an embodiment of a sampling phase synchronization circuit according to the present invention.

In FIG. 1, 1 is a frequency dividing circuit that receives a reference signal as input, and 2 is an analog-to-digital converter (hereinafter referred to as an A/D converter) that converts the output signal of the voltage controlled oscillator 5 into a digital signal. , 3 is a holding circuit that receives the output signal of the A/D converter 2 and the output signal of the frequency dividing circuit 1, and outputs and holds the input digital signal when the clock signal is input. A digital-to-analog conversion circuit (hereinafter referred to as
(referred to as a D/A converter).

The voltage controlled oscillator 571il is controlled by the output signal of the D/A converter 4.

FIG. 2 is a waveform diagram showing an example of the signals of each part to explain the operation of FIG. 2, (C) shows the output signal of the frequency dividing circuit 1, (d) shows the output digital signal of the holding circuit 3, and (e) shows the output signal of the D/A converter 4.

In this FIG. 2, Do and Dl are A/D
represents the minimum and maximum values of the output digital signal of converter 2, D2. D3 represents the output signal of the A/D converter 2 during sampling. Also, vI.

V2 represents the potential of the DC voltage.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2.

First, the output signal of the voltage controlled oscillator 5 (see FIG. 2(a)) is input to the A/D converter 2, and the output signal of the voltage controlled oscillator 5 shown in FIG. 2(IL)K is input to the A/D converter 2. 2 to convert it into a digital signal. Then, the output signal of the A/D converter 2 (see FIG. 2(b)) and the output signal of the frequency dividing circuit 1 (the second
(See Figure (C)) is input to the holding circuit 3, and when the output No. 16 of the frequency divider circuit 1 is input to the holding circuit 3, the digital signal input from the A/D converter 2 to the holding circuit 3 is The number is output from the holding circuit 3 and held.

Next, the output digital signal of this holding circuit 3 (Fig. 2 (
d)) is input to the D/A converter 4 to convert it into an analog signal, and the output signal of the D/A converter 4 (see Fig. 2(e)) is input to the voltage controlled oscillator 5 to perform voltage control. Controls the oscillator 5.

〔Effect of the invention〕

As explained above, the present invention includes an analog-to-digital converter that converts the output signal of a voltage controlled oscillator into a digital signal, and a holding circuit that outputs and holds the input digital signal when a clock signal is input. By having a digital-to-analog converter that converts the output signal of this holding circuit into an analog signal, the synchronization range is not affected by the pulse width of the output signal of the pulse wave generation circuit, resulting in stable synchronization. This has the effect of providing a range.

Further, there is an effect that a flat control voltage can be obtained without causing a voltage drop in the control voltage of the voltage controlled oscillator within the sampling period.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the sampling phase synchronization circuit according to the present invention, Fig. 2 is a waveform diagram showing examples of signals of each part to explain the operation of Fig. 1, and Fig. 3 is a conventional sampling phase synchronization circuit. Circuit configuration diagram showing an example of a synchronous circuit, No. 4
The figure is a waveform diagram showing examples of signals of each part to explain the operation of FIG. 3, and FIG. 5 shows the gate voltage V of the field effect transistor. FIG. 2 is an explanatory diagram showing an example of drain-source resistance value RDs characteristics according to the present invention. 1...↑・Frequency dividing circuit, 2...A/D converter (analog/digital converter), 3...Holding circuit, 4...
・D/A converter (digital/analog converter), 5...
...Voltage controlled oscillator.

Claims (1)

[Claims] A frequency dividing circuit that receives a reference signal as an input, an analog-to-digital converter that converts an output signal of a voltage controlled oscillator into a digital signal, and an output signal of this analog-to-digital converter and an output signal of the frequency dividing circuit as inputs. A holding circuit that outputs and holds an input digital signal when a clock signal is input, and a digital-to-analog converter that converts the output signal of the holding circuit to an analog signal, the digital-to-analog converter 1. A sampling phase synchronization circuit, characterized in that said voltage controlled oscillator is controlled by an output signal of said voltage controlled oscillator.