KR890004158B1 - Tone singnal demodulator - Google Patents

Abstract

The circuit for demodulating tone signal of some input frequency using together with phase-synchronizing loop method and wave star method includes a first buffer (30) shock-absorbing with input of signal, a phase synchronizing loop circuit composed of voltage modulation oscillator (70) and the first phase detector (40), a 900phase-shiftor, a second phase detector (50) generating the greatest DC output when input frequency signal is phasesynchronized with the output of voltage regulation oscillator (70), a delay regulator (90) to delay output clock of voltage regulator when comparator (80) is on-condition, and a wave transducer (100) that make delayed clock pulse to sinusodial wave.

Description

Tone signal demodulator

1 is a block diagram of a conventional tone signal demodulator.

2 is a block diagram of a tone signal demodulator according to the present invention.

3 is a circuit diagram showing an embodiment of the delay controller of FIG.

4 (a) to 4 (c) are operation waveform diagrams of each point in FIG.

5 is a circuit diagram showing an embodiment of the waveform modifier of FIG.

6 (a) and 6 (b) are operational waveform diagrams of the respective points in FIG.

7 is a circuit diagram of another embodiment of the sinusoidal wave forming machine of FIG.

8 is an operational waveform diagram of FIG.

* Explanation of symbols for main parts of the drawings

1 band pass filter 2 full band filter

3: signal size comparator 4: switch

30: first shock absorber 40: first phase detector

50: second phase detector 60: 90 °

70: voltage controlled oscillator 80: comparator

90: delay adjuster 100: waveform transducer

The present invention relates to a circuit for demodulating a tone signal, and more particularly, to a tone signal demodulator capable of reproducing a tone signal of a specific frequency among input signals.

Among the signals handled by an electronic device, when a constant frequency (tone) and other signals are mixed, only a single frequency (called a tone signal) is often separated.

For example, if the digital signal must be modulated at a certain frequency to transmit and receive a long distance, the external noise of the communication line must be removed at a certain distance. In case of retransmission after demodulation, the phase of input / output signal should be corrected.

In another example, in the case of a wireless car phone, the vehicle detects the distance by measuring a phase difference between a signal re-sent from the vehicle and a signal sent by the vehicle using a signal of a special frequency to measure the distance from a cell site.

In this case, conventionally, as shown in FIG. 1, an input signal passes through a band pass filter 1, and then a signal size comparator (3) switch 3 is used to adjust the delay time according to the strength of the signal. ) To "on" the output of the full-band filter (2). In addition, the signal size comparator 3 has been commonly used in a phase locked loop method. However, this method requires a large number of individual elements in the filter configuration of each stage. Also, since the temperature characteristics of the individual elements are different, the characteristics of the entire system are greatly influenced by the variation of the value of the external elements with temperature, and the operating temperature range is not large. I can't. This is due to the variation of the oscillation frequency of the voltage-controlled oscillator in the phase-locked loop and the filter characteristics using the active element.

Accordingly, an object of the present invention is to provide a tone signal demodulator that reproduces an input signal using a phase locked loop method and a waveform shaping method together.

In order to achieve the object of the present invention as described above, the present invention buffers an input signal having a specific frequency with a circuit of a front end through a first buffer and inputs the signal to a first phase detector to oscillate in a voltage controlled oscillator. Compared to the oscillation frequency, the oscillation frequency of the same frequency as that of the input signal is output from the voltage controlled oscillator, and at the same time, the output of the voltage controlled oscillator is outputted from the first buffer and the second phase detector through 90 ° or more. When the frequency of the input signal and the phase of the oscillation frequency of the voltage regulating oscillator coincide with each other in phase comparison, output the maximum DC voltage and turn on the comparator at the maximum DC voltage to output the waveform of the voltage regulating oscillator in the delay controller. Phase adjusted waveform outputted from the delay controller after adjusting the phase of The waveform is characterized by transforming the waveform into a sine wave.

Hereinafter, the present invention will be described in detail with reference to the drawings.

2 is a block diagram of a tone signal demodulator according to the present invention, in which a two-dot inner line is implemented as an integrated circuit 200, and reference numerals 10 to 19 are external pins. A power supply voltage Vcc is supplied to the reference numeral 18 to supply power to each block.

Reference numeral 19 is a ground terminal, and capacitors C ₂ and C ₃ are connected to pins 11 and 15 to supply a power supply voltage Vcc. The first phase detector 40 is a known phase detector and generates an error signal corresponding to a frequency difference and a phase difference between two signals input to the detector and is connected to the phase detector 40 through a pin 15. The capacitor C ₂ constituting the low pass filter outputs a DC voltage corresponding to the error signal. In addition, the voltage regulating oscillator 70 is oscillated when there is no signal input to the input terminal 10 by the resistor R ₁ and the capacitor C ₁ connected to the pins 16 and 17 at the free frnning frequency. When a signal having a near frequency is input to the input terminal 10, a well-known circuit oscillating in a direction in which the phase of the input signal phase and the clock oscillated by the voltage adjusting oscillator become the same, and the voltage control with the first phase detector 40 is performed. The part composed of the oscillator 70 is a phase locked loop (PLL) circuit 150.

Therefore, the phase-locked loop circuit 150 outputs the signal output from the first shock absorber 30 and the signal output from the voltage regulating oscillator 70 and the two signals in the first phase detector 40 comparing the frequency and phase. A DC voltage corresponding to the error value of the output is output and the output of the voltage regulating oscillator 70 is adjusted by using the DC voltage as a control signal.

As a result, the two frequencies applied to the first phase detector 40 are the same, and the output of the voltage regulating oscillator 70 generates a phase locked clock on the output signal of the first buffer 30.

The 90 ° phase shifter 60 is a circuit for inputting the output of the voltage controlled oscillator 70 to change the output signal by 90 ° phase.

The second phase detector 50 inputs the above-described output signal of the first shock absorber 30 and the output signal of the 90 ° phase shifter 60 and compares the phase and the frequency of the capacitor C ₃ connected to the pin 11. DC voltage is output by the low pass filter. The second phase detector 50 outputs a maximum DC voltage when the two input signals have the same frequency and have a 90 ° phase difference.

The comparator 80 is a conventional comparator that operates " on " (high state) when the output of the second phase detector 50 is maximum.

The delay controller 90 inputs the output clock pulse of the voltage controlled oscillator 70 when the comparator 80 is on, and charges the variable resistor R _ex and the capacitor C ₄ connected to the pins 12 and 13. It is a circuit that adjusts the time delay using discharge as the user wants. Delay controller 90 may be delayed by using a microcomputer may be easy to adapt to any situation.

The waveform modifier 100 is a circuit for transforming the output clock (square wave) of the delay adjuster 90 into a sine wave.

Hereinafter, the operation relationship of FIG. 2 will be described.

A signal of a specific frequency (tone signal) is input to the input terminal 10 as a line noise and input to the first buffer 30 having a high input impedance, and the output signal is inputted to the first phase detector 40 and the second phase detector. Enter in (50).

Therefore, the voltage regulating oscillator 70 operates at a frequency equal to a specific frequency (tone signal) of the input signal and in a direction in which phases are synchronized.

As a result, when the output clock of the voltage controlled oscillator 70 is in phase with the above-described tone signal of a specific frequency, the output of the 90 ° phase 60 and the tone signal are compared in phase with the second phase detector 50 to maximize The DC voltage is output, and the comparator 80 operates on.

Therefore, when the phase having the same frequency and the same phase as the tone signal input to the input terminal 10, the output of the comparator 80 is in a "high" state and the delay controller 90 is applied to the logic output of the comparator 80. By inputting the output clock of the voltage control oscillator 70 by the switching action, the user wants a time delay to output a time delayed clock pulse. The waveform transformer 100 inputs the time-delayed clock pulse which is the output of the delay controller 90 to convert the waveform into a sine wave and output it to the output terminal 20.

Therefore, in the present invention, a signal having a specific frequency is input to the input terminal 10, and a sine wave having the same frequency as this frequency is delayed as necessary for output to the output terminal 20.

3 is a circuit diagram of one embodiment of the delay regulator 90 of FIG. 2 according to the present invention. The line 210 is a line connected to the output line 210 of the voltage controlled oscillator 70 of FIG. 220 is a line connected to the comparator 80 of FIG.

Reference numeral 110 denotes a buffer having a high input impedance such that the signal of the output terminal does not affect the input side as the second buffer. For example, it may be a ballage flowerer.

The switch SW operates to close the switch SW when the line 220, that is, the comparator 80 of FIG. It can be easily recognized by those skilled in the art that it can be a switch using a conventional transistor or a tristate switch.

The variable resistor R _ex and the capacitor C ₄ are the same as the resistors and capacitors connected to the pins 12 and 13 in FIG. 2 to form the charge / discharge circuit. Therefore, the capacitor C ₄ is adjusted by adjusting the variable resistor R _ex . The voltage to be charged can be adjusted.

Reference numeral 120 is an operational amplifier and a reference voltage V _refl is applied to the terminal 225, and is connected to the positive feedback of the non-inverting terminal (+) of the operational amplifier 120 through a resistor R ₂ and through a resistor R ₃ . It is connected to the output terminal 230 and the pin 13 is connected to the inverting terminal (-) of the operational amplifier 120.

The comparator composed of the resistors R ₂ and R ₃ and the operational amplifier 120 has a high threshold voltage V _TH and a low threshold voltage V _TL and is expressed as follows.

In Equations (1) and (2), V _OH is the maximum output of the comparator and V _OL is the minimum output of the comparator.

4 (a) to 4 (c) show the operation waveform diagram of the delay controller of FIG. 3, and FIG. 4 (a) shows the waveform diagram when the switch SW is on. FIG. 4 (b) shows the switch SW. 4C is a waveform diagram that appears at the terminal 230 when the switch is turned on.

As described above, when the frequency and phase of the tone signal and the voltage control oscillator 70 coincide with each other, the output line 220 of the comparator 80 becomes "high" and the line 210 has the same phase as the tone signal. The clock pulse which is the output of the regulating oscillator 70 appears and this clock pulse causes the clock of the square wave as shown in FIG. do. The waveform of FIG. 4 (a) is charged and discharged to the capacitor C ₄ through the resistor R _ex constituting the charge / discharge circuit so that the waveform 300 appears on the pin 13 as shown in FIG. 4 (b). . This waveform is applied to the output terminal 230 of the operational amplifier 120 by the high threshold voltage V _TH and the low threshold voltage V _TL of the comparator composed of the resistors R ₂ and R ₃ and the operational amplifier 120. As shown in FIG. 4 (c), the same waveform having a delayed time as shown in FIG. 4 (a) appears. Accordingly, by adjusting the variable resistor R _ex to adjust the charge / discharge time of the charge / discharge waveform 300 of FIG. 4 (b), a waveform having a desired time delay by the user can be obtained from the terminal 230.

FIG. 5 is an embodiment of the waveform transformer 100 of FIG. 2. The input terminal of the inverter 130 is connected to the operational amplifier output terminal 230 of FIG. ₃ while connected to the switch SW ₃ and the output terminal is connected to the switch SW ₂ . do. Pin 14 is grounded by the capacitor C ₅ as a second assist. Also, pin 14 is connected to a voltage follower acting as a buffer of operational amplifier 140, and the output terminal is connected in series with diodes D ₁ , D ₂ and resistor R ₅ through resistor R ₄ , and diode D _3. The series connection of the resistor R ₆ , the resistor R ₇ , the resistor R ₈ and the diode D ₄ in series, and the resistor R ₉ , the diode D ₅ , and the series ₇ in series are connected to the output terminal 20 and the reference voltage V _ref2. Is connected in parallel to the terminal 280 to which is supplied.

The operations of the switches SW ₂ and SW ₃ alternately turn on and off depending on the "high" or "low" state of the voltage output from the delay regulator output terminal 230 of FIG. That is, when the terminal 230 is "high", the output of the inverter 130 is "low" state, the switch SW ₂ is connected to the contact 250, the switch SW ₃ is connected to the contact 260, the constant current source ( When the capacitor C ₅ is charged with the constant current I ₁ of the capacitor 600 and the terminal 230 is “low”, the switches SW ₂ and SW ₃ operate in reverse, so that the charged voltage is supplied through the constant current source 700. Discharge.

The charging voltage V according to the time t of the capacitor C ₅ by the constant current I ₁ of the constant current source 600 can be written as follows.

Q = C ₅ V = I ₁ t

therefore

Where Q is the amount of charge charged in capacitor C _5. Therefore, as can be seen from equation (3), it can be seen that the voltage charged in capacitor C ₅ increases linearly with time t. (Linear decreases during discharge)

Therefore, the waveform of the pin 14 with respect to the waveform of the terminal 230 as shown in Figure 6 (a) can obtain a triangular wave as shown in the waveform (800) of Figure 6 (b).

The triangular waveform 800 of FIG. 6 (b) is inputted to the sine wave waveform shaper 950 composed of the resistors R ₄ -R ₉ and the diodes D ₁ -D ₆ through a buffer circuit composed of the operational amplifier 140. The sine wave is output to 20.

The operation of the sinusoidal waveform shaper 950 is as follows.

The voltage corresponding to the difference between the output voltage of the operational amplifier 140 and the reference voltage V _ref2 supplied to the terminal 280 does not conduct the diodes D ₁ -D ₆ between the times t ₀ and t _{1 in} FIG. 6 (b). If the voltage fails, current flows through resistors R ₄ and R ₇ , and if only diode D ₃ conducts between times t ₁ and t ₂ , the current draws resistor R ₄ , which corresponds to the parallel composite resistance of resistors R ₆ and R ₇ . If the diode D ₁ -D ₃ becomes conductive between the times t ₂ and t ₃ , the current flows through the parallel composite resistance of the resistors R ₅ , R ₆ and R ₇ and the resistor R ₄ , so that the output terminal 20 A waveform such as waveform 900 of FIG. 6 (b) is outputted to form a sine wave.

Continued parallel connection of more diodes and resistors in series allows us to subdivide the time segment of Figure 6 (b) and to form an accurate sine wave.

FIG. 7 illustrates another embodiment of the sinusoidal wave forming machine 950 of FIG. 5, in which an output terminal of the operational amplifier 140 of FIG. 5 is connected to the base of transistor Q ₁ , and terminal 280 of FIG. 5 is transistor Q _2. A nonlinear output curve of a differential amplifier, which is connected to the base of the transistor and composed of transistors Q ₁ and Q _2, and resistors R ₁₀ -R ₁₂ and a constant current source 850, is used to calculate the output voltage V of the sine wave of the transistors Q ₁ and Q ₂ . Output is available at the collector terminal.

It should be noted that the resistance values connected to the collectors and emitters of the transistors Q ₁ and Q ₂ are the same, so the same notation is used.

FIG. 8 is a diagram showing the operation waveforms of the sinusoidal wave forming machine of FIG. 7 and when the triangular wave Vin of FIG. 8 is input to the input terminals 290 and 280 of FIG. A sinusoidal wave like the eighth degree curve V _out appears between the terminals 293 and 294.

That is, since the voltage across the terminal 290 is greater than the voltage across the terminal 280 between t ₁ and t ₂ in FIG. ₈ , the current flowing through the transistor Q ₁ becomes larger than the current flowing through the transistor Q ₂ . Thus, the voltage between terminals 293 and 294 is curved, as between the times t ₁ and t _{2 of the} line V _ou in FIG. 8 (since curve C is nonlinear).

In addition, since the saturation point of the curve C is when the transistor Q ₂ is turned off and the entire current flows to the transistor Q ₁ , the voltage between the terminals 293 and 294 becomes I _s R _{12, which} is as shown in FIG. 8.

As described above, the tone signal demodulator of the present invention uses the PLL waveform shaping method together to reproduce the sinusoidal signal by outputting the signal of the sinusoidal wave as much as necessary by delaying the input tone signal. You have an advantage.

Claims (3)

In the circuit for detecting and demodulating a specific frequency, the predetermined frequency and phase are input by inputting a signal having the specific frequency and buffering the first buffer 30 and the output signal of the first buffer 30. A phase-locked loop circuit 150 comprising a first phase detector 40 and a voltage-regulated oscillator 70 to match with each other, and a 90 ° phase shifter 60 having a 90 ° phase shift by inputting an output of the voltage-regulated oscillator 70. And the output of the phase shifter 60 and the output of the buffer 30 to generate a maximum DC output when the signal of the input specific frequency is in phase synchronization with the output of the voltage regulating oscillator 70. A two-phase detector 50, a comparator which is turned on with respect to the maximum DC output, and a delay regulator 90 which delays the output clock of the voltage controlled oscillator 70 by a predetermined time when the comparator 80 is turned on. And sine wave the delayed clock pulse. Tone signal demodulator, characterized in that the transducer consists of waveforms 100 for a waveform shaping. The switch SW according to claim 1, wherein the delay controller 90 passes an output clock of the voltage regulating oscillator 70 during operation of the comparator 80, and a charge / discharge circuit R _ex charging and discharging the clock. , C ₄ ) and comparing means (R ₂ , R ₃ ) (120) for generating a clock waveform time-delayed by the charge and discharge waveform. The triangular wave of claim 1, wherein the waveform transformer 100 inputs a time-delayed clock pulse to switch alternately to switch a linear wave of a capacitor by the current sources 600 and 700 by a switch SW ₂ (SW ₃ ). Means for generating a (C ₅ ), the second shock absorber 140 for buffering by inputting the triangular wave, and the sinusoidal wave shaper 950 for generating a sine wave by inputting the output of the buffer 140 Circuit.

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