JP2001186017A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit that can more easily and more positively adjust the output phase difference of a phase comparator. SOLUTION: In the PLL circuit where the frequency of an oscillated output is controlled in response to the result of phase comparison between a fed-back oscillation output and an input signal, an LPF 3 integrates the oscillated output and an output in response to the result of comparison between the integrated output and two threshold values of a Schmitt trigger buffer 6 is applied to a phase comparator circuit 1. The phase comparator circuit 1 compares the phase of the output of the buffer 6 with a phase of the input signal and controls the oscillated frequency of a VCO 4 depending on the result of phase comparison. Controlling variably the voltage applied to a phase difference adjustment terminal, the phase of an output 60 of the buffer 6 can adjusted to control the result of phase comparison.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit,
In particular, a PLL (Ph
ase Locked Loop) circuit.

[0002]

2. Description of the Related Art Among digital data transfers, those using a synchronous method require a stable reference clock in order to perform stable data transfer at a high speed. In order to achieve more reliable synchronization, it is necessary to adjust the phase of each device receiving the reference clock. For example, FIG.
, The reference clock CLK is divided into N devices D1, D1, D2,... DN (N is an integer of 2 or more).
Consider the case of distribution to In this case, the reference clock CL
Clock skew occurs between a device (for example, device D1) that is physically close to the input unit of K and a device (for example, device DN) that is physically far from the input unit of K. Therefore, in order to adjust this, it is necessary to provide a PLL circuit for each device and perform phase adjustment. This conventional PLL circuit is disclosed in
No. 0046 discloses this. This publication describes the PLL circuit shown in FIG. This PLL
The circuit includes a phase comparator (Phase Comparator), a low-pass filter (LPF; Low Pass Filter), and a voltage controlled oscillator (VCO; Voltage Controlled Oscilator). In this PLL circuit, first, the output frequency and phase of the VCO are fed back and compared with the reference frequency and phase in the phase comparator. Then, the result of the phase comparison is integrated by the LPF, and the oscillation frequency of the VCO is controlled based on the result of the integration.

In addition, as shown in FIG. 8, a frequency divider (Divider) is added to the feedback loop from the VCO to the phase comparator, and the frequency divider outputs the frequency divided output from the frequency divider. The derived PLL circuit is also described. By adding this frequency divider, a desired oscillation frequency output can be derived.

[0004]

SUMMARY OF THE INVENTION The above-mentioned conventional PLL
The circuit performs the phase adjustment using a circuit driven by the output signal of the VCO. Therefore, unless the output frequency of the VCO is at least twice as high as the desired frequency and the required adjustment accuracy is higher, practical adjustment cannot be performed, and the upper limit of the output frequency of the PLL circuit is limited by the characteristics of the VCO. was there.

[0005] The present invention has been made to solve the above-mentioned disadvantages of the prior art, and the object thereof is to make it easier.
Another object of the present invention is to provide a PLL circuit capable of more positively adjusting the output phase difference.

[0006]

A PLL circuit according to the present invention comprises an oscillator having an oscillation output frequency controlled in accordance with a phase comparison result output of a phase comparator, and a first low-pass which receives the oscillation output as an input. A filter for transmitting an output corresponding to a result of comparison of the output of the filter with a predetermined threshold value, and control means for controlling the threshold value, wherein the phase comparator includes an output of the buffer and an input to its own circuit. A phase difference from a signal is output as the phase comparison result output, and an oscillation output of the oscillator is derived as its own circuit output. The buffer is a Schmitt trigger type buffer in which a threshold for changing the output from a low level to a high level and a threshold for changing the output from a high level to a low level are different. Then, the control means controls the increase or decrease of the threshold value according to an external command.

A second low-pass filter having a cut-off frequency lower than a cut-off frequency of the first low-pass filter, receiving the phase comparison result output as input, and controlling an oscillation frequency of the oscillator by a filtered output; It may further include a pass filter. Further, the phase comparator may further include an inverting means for inverting an output of the buffer to be input to the phase comparator.

Another PLL circuit according to the present invention is a PLL circuit for controlling the frequency of the oscillation output in accordance with the result of the phase comparison between the feedback oscillation output and the input signal, and integrating means for integrating the oscillation output. And a buffer for transmitting an output corresponding to a result of comparison of the integrated output with a predetermined threshold value is provided in a feedback loop, and the phase of the output of the buffer and the phase of the input signal are compared. The buffer is a Schmitt trigger type buffer in which a threshold for changing the output from a low level to a high level and a threshold for changing the output from a high level to a low level are different. Further, the apparatus may further include control means for increasing or decreasing the threshold value according to an external command. The image processing apparatus may further include an inverting unit that inverts the output of the buffer, which is used as a reference for phase comparison.

In a PLL circuit that forms a closed loop by connecting a phase comparator, an LPF, a VCO, and a frequency divider in series, a phase is adjusted using a circuit driven by an output signal of the VCO.
For this reason, the output frequency of the VCO is set at 2 times higher than the desired frequency.
Practical adjustment cannot be performed unless the required adjustment accuracy is higher than twice or more, and the upper limit of the output frequency of the PLL circuit is limited by the VCO. Therefore, the present invention provides a means for adjusting the output phase difference of the PLL circuit more easily and more positively.

[0010]

Next, an embodiment of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, the same parts as those in the other drawings are denoted by the same reference numerals.

FIG. 1 is a block diagram showing an embodiment of a PLL circuit according to the present invention. A general PLL circuit is
A closed loop is formed by connecting the phase comparator, LPF, VCO, and frequency divider in series. However, in a synchronous digital circuit, it is necessary to accurately adjust the phase of a reference clock. Therefore, the PLL circuit shown in FIG. 1 has a phase adjustment function.

That is, the present PLL circuit comprises a phase comparator 1
0, LPF2, VCO4, another L
PF3 is present. If the cutoff frequency of LPF3 is set sufficiently higher than the cutoff frequency of LPF2 (that is, the cutoff frequency of LPF2 is lower than the cutoff frequency of LPF3), buffer 6 is compared with the integrated waveform obtained from the output of LPF3. The desired input / output phase difference can be obtained by increasing / decreasing the threshold (threshold voltage). In other words, by allowing the threshold voltage at the input of the phase comparator to change arbitrarily,
The desired input / output phase difference can be obtained.

The operation of the PLL circuit will be described.
In FIG. 1, the circuit includes a phase comparator 10, an LPF2,
It is composed of VCO4 and LPF3. In such a configuration, a general PLL other than the phase comparator 10 and the LPF 3 is used.
Performs the same operation as the circuit.

The phase comparator 10 has a Schmitt trigger type input circuit (buffer) corresponding to two signals to be compared. That is, in the present PLL circuit, the buffer 5 is provided corresponding to the input signal, and the buffer 6 is provided corresponding to the output 30 of the LPF 3 which is a feedback loop signal. Then, the phase comparison circuit 1 compares the phases of the outputs of the two buffers 5 and 6.

The phase comparison result output of the phase comparison circuit 1 is integrated in the LPF 2 and converted into a voltage level. Then, the oscillation frequency of the VCO 4 is controlled by this voltage level. This oscillation output 40 is
It is derived as the output of the L circuit.

The oscillation output 40 of the VCO 4 is fed back to the phase comparator 10. An LPF 3 is provided in the feedback loop. Oscillation output 40
Is a square wave as shown in FIG.
The output 30 of 3 has an integral waveform as shown in FIG. That is, unlike the general PLL circuit, the LPF is inserted in the feedback loop, so that the slew rate of the feedback waveform becomes slow.

The output 30 of the LPF 3 is input to the buffer 6. The buffer 6 is a Schmitt trigger type buffer circuit, and has a different threshold for changing the output 60 from a low level to a high level and a threshold for changing the output 60 from a high level to a low level. In other words, when the level of the output 60 changes, “LOW” → “HIG”
The threshold of “H” is different from the threshold of “HIGH” → “LOW”. Further, a variable threshold voltage terminal for controlling the change of the threshold value is added to the buffer 6. This terminal functions as a phase difference adjustment terminal in the present PLL circuit.

Referring now to FIG. 3, the output 30 of the LPF 3
And the relationship between the threshold and the threshold of the buffer 6 will be described. In the figure, the output 40 of the VCO 4 is indicated by a dashed line,
The output 30 of the LPF 3 is shown by a solid line. Also, Th1a, Th1b, Th2a, Th2b, Th3 in FIG.
a and Th3b are threshold values of the buffer 6. Buffer outputs 60-1, 60-2 and 60-3 are shown corresponding to these thresholds.

As described above, the feedback waveform, which is the output 40 of the VCO 4, passes through the LPF 2, and the slew rate can be reduced so as to secure the desired phase difference adjustment accuracy and phase difference adjustment range. Then, the feedback waveform whose slew rate has been sufficiently reduced is input to the phase comparator 10 having the Schmitt trigger type buffer 6.

When the threshold voltage applied to the threshold voltage variable terminal added to the buffer 6 is changed, the threshold voltage of the Schmitt trigger from "LOW" to "HIGH" and the threshold voltage from "HIGH" to "LOW" are simultaneously increased. Shall change.

For example, when the voltage applied to the threshold voltage variable terminal is changed, the Schmitt trigger “LO
The threshold voltage from "W" to "HIGH" increases, and the threshold voltage from "HIGH" to "LOW" decreases. Specifically, when the voltage applied to the threshold voltage variable terminal is changed in a state where the threshold voltages Th1a and Th1b in FIG. 3 are set, the threshold voltages Th2a and Th2b, and the threshold voltages Th3a and Th3b
, The voltage value changes sequentially.

As described above, when the threshold voltage value is changed, the output of the buffer 6 becomes the output 60- in FIG.
1, the phase changes like the output 60-2 and the output 60-3. The waveform whose phase has been controlled in this manner is input to the phase comparator 10, and the phase of the waveform input to the present PLL circuit is compared. Then, the phase difference between these two waveforms is output as a phase comparison result.

As a result, a closed loop is formed, and the PLL
An output adjusted to a desired phase difference with the input waveform to the circuit can be obtained. That is, in this circuit, by controlling the change in the voltage to the phase difference adjustment terminal, the buffer 6
Is adjusted to control the result of the phase comparison. Since the LPF is provided in the feedback loop, the slew rate of the feedback waveform is slower than that of the conventional circuit, and the accuracy of the phase difference adjustment can be improved.

By the way, a predetermined voltage is applied to the phase difference adjusting terminal. Then, a desired phase difference is obtained by changing the applied voltage value. In order to change the voltage value, for example, as shown in FIG. 4, a variable voltage divider VR may be connected and the applied voltage value may be adjusted. If the threshold voltage at the input of the phase comparator is changed by this voltage adjustment, the phase difference can be easily adjusted. Thus, the input phase difference can be adjusted with a simple configuration. As the variable voltage divider VR, a trimmer resistor or the like may be used so that the voltage dividing resistance value can be manually changed.
Further, the resistance value may be changed and controlled by a command signal input from the outside.

In this embodiment, a Schmitt trigger type buffer is used in the input stage of the phase comparator. Thus, even if the phase difference is adjusted, the pulse duty of the output of the buffer is always 50%. A general buffer other than the Schmitt trigger type may be used, but the pulse duty may not be 50%, and an offset may occur to shift the frequency.

In order to ensure a sufficient phase difference, P
A phase inversion circuit or the like may be added in the feedback loop of the LL circuit. That is, as shown in FIG. 5, if the waveform is inverted by providing the inverting circuit 7 in the feedback loop from the VCO 4 to the phase comparing circuit 1, the phase of the signal to be given to the phase comparing circuit 1 is greatly shifted. Can be. Thereby, even when the clock skew value is large, it can be effectively adjusted.

As described above, the present circuit is a PLL circuit that controls the frequency of the oscillation output according to the phase comparison result between the oscillation output that is fed back and the input signal, and the LPF that integrates the oscillation output and the LPF that integrates the oscillation output. A buffer for sending an output according to the result of comparison of the integrated output with a predetermined threshold is provided in the feedback loop, and the phase of the output of the buffer is compared with the phase of the input signal. If the electronic apparatus is configured by using the PLL circuit configured as described above and each of the devices illustrated in FIG.
The clock phase can be adjusted for each device, and clock skew can be eliminated.

The present invention can take the following aspects in connection with the description of the claims.

(1) P according to any one of claims 1 to 9
A plurality of devices each provided with an LL circuit; and a unit for commonly supplying a clock to the PLL circuit provided in each of the devices, wherein the threshold value is set in each of the PLL circuits provided in each device. An electronic device characterized by being controlled.

(2) The electronic device according to (1), wherein the plurality of devices operate in synchronization with outputs of PLL circuits provided respectively.

[0031]

As described above, according to the present invention, the phase difference between the input and output signals of the PLL circuit is easily adjusted with a large change amount by changing the threshold voltage of the buffer at the input portion of the phase comparator. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a PLL circuit according to an embodiment of the present invention.

FIG. 2 is a waveform chart showing an operation of the PLL circuit of FIG. 1;

FIG. 3 is a waveform chart showing an operation of the PLL circuit when a threshold value is changed.

FIG. 4 is a diagram illustrating an example of a threshold adjustment circuit in FIG. 1;

FIG. 5 is a block diagram showing a configuration of a PLL circuit according to another embodiment of the present invention.

FIG. 6 is a diagram illustrating an example of clock skew adjustment using a PLL circuit.

FIG. 7 is a block diagram showing a configuration of a conventional PLL circuit.

FIG. 8 is a block diagram showing another configuration of a conventional PLL circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Phase comparison circuit 2, 3 LPF 4 VCO 5, 6 Buffer 7 Inversion circuit 10 Phase comparator

Claims (9)

[Claims] An oscillator whose oscillation output frequency is controlled in accordance with a phase comparison result output of a phase comparator, a first low-pass filter having the oscillation output as an input, and a predetermined threshold for an output of the filter. And a control unit for controlling the threshold value, wherein the phase comparator outputs a phase difference between an output of the buffer and an input signal to its own circuit. Wherein the oscillation output of the oscillator is derived as its own circuit output. 2. The buffer according to claim 1, wherein the buffer is a Schmitt trigger type buffer having a threshold value for changing an output from a low level to a high level and a threshold value for changing an output from a high level to a low level. Claim 1
The PLL circuit as described in the above. 3. The PLL circuit according to claim 1, wherein said control means controls to increase or decrease said threshold value according to an external command. 4. A second low-pass filter having a cut-off frequency lower than a cut-off frequency of the first low-pass filter, receiving the phase comparison result output as input, and controlling an oscillation frequency of the oscillator by a filtered output. The PLL circuit according to claim 1, further comprising a pass filter. 5. The PLL circuit according to claim 1, further comprising an inverting means for inverting an output of said buffer to be input to said phase comparator. 6. A PLL circuit for controlling a frequency of an oscillation output according to a phase comparison result between an oscillation output and an input signal fed back, wherein: an integrating means for integrating the oscillation output; A PLL circuit, wherein a buffer for outputting an output according to a comparison result with a threshold value is provided in a feedback loop, and a phase of an output of the buffer and a phase of the input signal are compared. 7. The buffer according to claim 1, wherein the buffer is a Schmitt trigger type buffer having a threshold value for changing an output from a low level to a high level and a threshold value for changing an output from a high level to a low level. Claim 6
The PLL circuit as described in the above. 8. The apparatus according to claim 6, further comprising control means for controlling to increase or decrease said threshold value according to an external command.
The PLL circuit as described in the above. 9. The PLL circuit according to claim 6, further comprising an inverting means for inverting an output of said buffer, which is used as a reference for phase comparison.