JP3602487B2 - Frequency shift keying demodulator - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a frequency shift keying type demodulator for modulating a digital signal by frequency shift.
[0002]
[Prior art]
Generally, a phase locked loop (hereinafter, referred to as "PLL" (Phase Locked Loop)) circuit is used for a demodulator using the frequency shift keying method.
Hereinafter, a frequency shift keying demodulator using a conventional PLL circuit will be described with reference to FIG.
FIG. 15 is a block diagram showing a configuration of a frequency shift keying demodulator using a conventional PLL circuit.
15, 1501 is an IF signal, 1502 is a phase comparator, 1503 is an LPF, 1504 is a demodulated baseband signal, 1505 is a VCO, 1506 is a VCO output signal, 1507 is a determiner, 1508 is a threshold voltage, and 1509 is a demodulated signal. It is.
[0003]
The IF signal 1501 is an intermediate frequency signal generated by converting a frequency shift keying modulation signal, which is a high frequency signal received by an antenna or the like, by a frequency conversion circuit (not shown).
The phase comparator 1502 compares the phases of the IF signal 1501 and the VCO output signal 1506, detects the phase difference between the two signals, and outputs a phase error signal.
The LPF 1503 is a low-pass filter that outputs a demodulated baseband signal 1504 by integrating the phase error signal from the phase comparator 1502 (removing high-frequency components and outputting low-frequency components).
The VCO 1505 is a voltage controlled oscillator (hereinafter, referred to as “VCO” (Voltage Controlled Oscillator)), and changes the VCO output signal 1506 so that the phase error signal approaches 0 according to the demodulated baseband signal 1504.
The determiner 1507 compares the demodulated baseband signal 1504 with a fixed threshold voltage 1508 to generate a demodulated signal 1509 which is a digital signal.
[0004]
[Problems to be solved by the invention]
As described above, the PLL circuit is a loop circuit including the phase comparator 1502, the LPF 1503, and the VCO 1505. In order to accurately demodulate the frequency shift keying modulation signal, it is important to improve the characteristics of the PLL circuit.
In particular, the cut-off frequency (cut-off frequency) of the PLL circuit needs to be increased in order to improve the response to the input modulation signal. However, if the response is improved, the signal-to-noise ratio becomes worse due to noise. In order to maintain the balance, an optimum circuit design has been required, and the circuit has been complicated by adding a compensation circuit and the like.
Further, since the cutoff frequency acts on the demodulated baseband signal 1504 as intersymbol interference, it has been a cause of erroneous determination when the determinator 1507 determines the demodulated signal 1509.
The conventional frequency shift keying demodulator has the above problem.
[0005]
An object of the present invention is to provide a frequency shift keying demodulator that accurately demodulates a frequency shift keying modulation signal input with a simple circuit configuration without using a high-precision PLL circuit.
[0006]
[Means for Solving the Problems]
In order to solve the above problems, a frequency shift keying demodulator according to the present invention has the following configuration.
According to the first aspect of the present invention, there is provided a fixed oscillation circuit for oscillating a reference signal of a fixed frequency, a phase difference between a frequency shift keying modulation signal obtained by performing modulation by frequency shift using a digital signal as a baseband signal, and a phase difference between the reference signal and the reference signal. A phase difference integrator for detecting the integral value of each of the symbol periods defining a section of 1-bit data, a symbol detector for detecting a symbol synchronization signal from the frequency shift keying modulation signal, and an output from the phase difference integrator. A signal, a sample and hold circuit that samples and holds a timing signal generated based on the symbol synchronization signal, a determiner that generates a demodulated signal by comparing an output signal from the sample and hold circuit with a threshold voltage, And a frequency shift keying demodulator.
[0007]
According to a second aspect of the present invention, the phase difference integrator detects a first zero-cross point of the frequency shift keying modulation signal and a second zero-cross detection of the reference signal. A circuit, a first zero-crossing detection counter that counts a detection signal of the first zero-crossing detection circuit for each symbol period, and a second that counts a detection signal of the second zero-crossing detection circuit for each symbol period. A zero-cross detection counter, a time difference detection circuit that measures a time until the first zero-cross detection counter and the second zero-cross detection counter reach a constant value, and obtains a time difference between the two; and a frequency shift keying modulation based on the time difference. A phase difference detection circuit for obtaining a phase difference per symbol period of the signal. A frequency shift keying demodulator according to claim 1.
[0008]
According to a third aspect of the present invention, there is provided a symbol detector for detecting a symbol synchronization signal from a frequency shift keying modulated signal obtained by performing modulation by frequency shift using a digital signal as a baseband signal, and a zero cross point of the frequency shift keying modulated signal. , A zero-cross detection counter that counts a detection signal of the zero-cross detection circuit for each symbol period that defines a section of 1-bit data, and a time until the zero-cross detection counter reaches a constant value. A phase difference integrator having a time difference detection circuit for obtaining a time difference between the measurement time and the fixed time; and a phase difference detection circuit for obtaining a phase difference per symbol period of the frequency shift keying modulation signal from the time difference. The output signal from the phase difference integrator is calculated based on the symbol synchronization signal. Frequency shift comprising: a sample and hold circuit for sampling and holding with the generated timing signal; and a determiner for generating a demodulated signal by comparing an output signal from the sample and hold circuit with a threshold voltage. It is a keying demodulator.
[0009]
According to a fourth aspect of the present invention, the fixed oscillation circuit generates two or more oscillation output signals having different phases, and selects the oscillation output signal having the smallest phase difference from the symbol synchronization signal as a reference signal. The frequency shift keying demodulator according to claim 1 or 3, wherein the frequency shift keying demodulator outputs the signal.
[0010]
The invention according to claim 5 has a PLL circuit in place of the fixed oscillation circuit, wherein the PLL circuit integrates a phase comparator for comparing a phase difference between two signals and an output signal of the phase comparator. A low-pass filter, a voltage-controlled oscillator whose oscillation frequency changes according to the output signal of the low-pass filter, and a frequency divider for dividing the output signal of the voltage-controlled oscillator. The voltage controlled oscillator is controlled so that the phase of the signal and the output signal of the frequency divider coincide, and the output signal of the voltage controlled oscillator is output as a reference signal. 3. The frequency shift keying demodulator according to item 3.
[0011]
The invention according to claim 6 is the frequency shift keying demodulator according to claim 1 or 3, wherein a voltage obtained by averaging an output signal of the phase difference integrator is used as the threshold voltage. .
[0012]
According to a seventh aspect of the present invention, as the averaging means, a voltage obtained by smoothing an output signal of the phase difference integrator by a low-pass filter is used as the threshold voltage. It is a frequency shift keying demodulator.
[0013]
The invention according to claim 8 is characterized in that, as the averaging means, a maximum value and a minimum value of the output signal from the sample hold circuit are detected, and a midpoint of each potential is set as the threshold voltage. A frequency shift keying demodulator according to claim 6.
[0016]
Claim 9 2. The invention according to claim 1, further comprising a low-pass filter circuit between the phase difference integrator and the sample-and-hold circuit, the low-pass filter circuit passing only a frequency lower than a predetermined frequency. Or Claim To 3 3 is a frequency shift keying demodulator as described.
[0017]
Claim 10 The invention according to claim 1, further comprising a band-pass filter circuit between the phase difference integrator and the sample-and-hold circuit, the band-pass filter passing only a frequency within a certain frequency range. Or Claim To 3 3 is a frequency shift keying demodulator as described.
[0018]
The present invention has an effect that a frequency shift keying demodulator having good reception characteristics can be realized with a simple circuit configuration not including a PLL circuit or a circuit configuration including a simple PLL circuit.
Further, since the present invention can automatically generate (adjust) the threshold voltage used in the decision unit, even if the input frequency shift keying modulation signal has a frequency offset, it can use a suitable threshold voltage to accurately digitize. This has the effect of realizing a frequency shift keying demodulator capable of obtaining a demodulated signal.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment that specifically shows a preferred embodiment for carrying out the present invention will be described with reference to the drawings.
[0020]
<< Example 1 >>
First Embodiment A frequency shift keying demodulator according to a first embodiment will be described with reference to FIGS.
FIG. 1 is a block diagram illustrating a configuration of the frequency shift keying demodulator according to the first embodiment of the present invention.
In FIG. 1, 101 is an IF signal, 102 is a symbol detector, 103 is a symbol synchronization signal, 104 is a fixed oscillation circuit, 105 is a phase difference integrator, 106 is a demodulation baseband signal, 107 is a sample and hold circuit, and 108 is a sample. A hold signal, 109 is a determiner, 110 is a threshold voltage, and 111 is a demodulated signal.
The IF signal 101 is an intermediate frequency signal generated by converting a frequency shift keying modulation signal, which is a high frequency signal received by an antenna or the like, by a frequency conversion circuit (not shown).
[0021]
The frequency shift keying modulation signal in the first embodiment increases the frequency by a fixed amount from the center frequency when the transmission baseband signal indicates “+1”, and decreases by the same frequency when the transmission baseband signal indicates “−1”. It is modulated according to the method of causing.
[0022]
The symbol detector 102 detects a symbol period from the preamble signal transmitted first of the IF signal 101, generates a symbol synchronization signal 103 that defines a symbol period boundary by a rising edge, and outputs the symbol synchronization signal 103 to the phase difference integrator 105 and Output to the sample and hold circuit 107. The preamble signal is a bit pattern sequence transmitted prior to a transmission frame (symbol) to establish clock synchronization. Also, one-bit data is transmitted in one symbol period.
The fixed oscillation circuit 104 outputs a signal of a fixed frequency (reference signal).
[0023]
The phase difference integrator 105 compares the phase of the IF signal 101 with the phase of the reference signal from the fixed oscillation circuit 104, and integrates the phase error (removing high-frequency components and outputting low-frequency components) to obtain a demodulation baseband. A signal 106 is generated and output.
FIG. 2 is a block diagram showing an internal configuration of the phase difference integrator 105.
2, reference numeral 201 denotes a first zero-crossing detection circuit, 202 denotes an IF signal zero-crossing detection signal, 203 denotes a first zero-crossing detection counter, 204 denotes an IF signal zero-crossing counter signal, 205 denotes a second zero-crossing detection circuit, and 206 denotes a fixed. Oscillation circuit zero-cross detection signal, 207 is a second zero-cross detection counter, 208 is a fixed oscillation circuit zero-cross counter signal, 209 is a clock signal generator, 210 is a time difference detection circuit, 211 is a leading time signal, 212 is a delay time signal, 213 Is a phase difference detection circuit.
[0024]
The first zero cross detection circuit 201 detects a zero cross point of the IF signal 101 and outputs an IF signal zero cross detection signal 202. The zero cross point is a point where the polarity of the IF signal 101 is inverted. Typically, the first zero-crossing detection circuit 201 amplifies the IF signal 101 with a high amplification factor, saturates it, binarizes it, and outputs it. The first zero-crossing detection counter 203 is a counter that increments each time a rising edge of the IF zero-crossing detection signal 202 from the first zero-crossing detector 201 is detected. Further, the first zero-crossing detection counter 203 outputs a HIGH-level signal until the counter value is incremented to a constant value (N), and outputs a LOW-level signal after reaching the N value. (IF signal zero cross counter signal 204)
[0025]
The second zero cross detection circuit 205 detects a zero cross point of the reference signal output from the fixed oscillation circuit 104, and outputs a fixed oscillation circuit zero cross detection signal 206. The second zero-cross detection counter 207 is a counter that increments each time a rising edge of the fixed oscillation circuit zero-cross detection signal 206 from the second zero-cross detection circuit 205 is detected. Further, the second zero-crossing detection counter 207 outputs a HIGH level signal until the counter value is incremented and reaches a constant value (N), and outputs a LOW level signal after reaching the N value. (Fixed oscillation circuit zero cross counter signal 208)
[0026]
The counter value of the first zero-crossing detection counter 203 and the counter value of the second zero-crossing detection counter 207 are reset (cleared to 0) at the rising edge 801 of the symbol synchronization signal 103 from the symbol detector 102.
[0027]
The time difference detection circuit 210 measures the time difference between the falling edge of the IF signal zero-cross counter signal 204 and the falling edge of the fixed oscillation circuit zero-cross counter signal 208 using the clock signal from the clock signal generator 209, and calculates the time difference signal. To the phase difference detection circuit 213. At this time, if the HIGH level time of the IF signal zero-cross counter signal 204 <the HIGH level time of the fixed oscillation circuit zero-cross counter signal 208, the advance time signal 211 is output, and the HIGH level time of the IF signal zero-cross counter signal 204> fixed oscillation In the case of the HIGH level time of the circuit zero-cross counter signal 208, a delay time signal 212 is output.
[0028]
The phase difference detection circuit 213 detects the time difference detection The time difference signal (lead time signal 211 or delay time signal 212) from the circuit 210 is measured using the reference clock signal from the clock signal generator 209. Then, the demodulation baseband signal 106 is generated and output by multiplying the time (the advance time or the delay time) by a proportional constant (K).
[0029]
FIG. 3 shows an operation waveform example of each component of the phase difference integrator 105.
In one symbol period 301 of the symbol synchronization signal 103, since the frequency of the IF signal 101> the frequency of the fixed oscillation circuit 104, the IF signal zero-cross detection signal 202 and the fixed oscillation circuit zero-cross detection signal 206 have waveforms as shown in the figure.
Then, the counter value of the first zero-crossing detection counter 203 reaches N earlier than the counter value of the second zero-crossing detection counter 207. The time difference detection circuit 210 outputs the difference signal to the phase difference detection circuit 213 as an advance time signal 211.
The phase difference detection circuit 213 measures the time width of the advance time signal 211 using the clock signal from the clock signal generator 209, and obtains the advance time difference 303. To convert the advance time difference 303 into a phase, the phase difference is multiplied by K to calculate a phase difference 305 (demodulated baseband signal 106) in one symbol period 301.
[0030]
In one symbol period 302, the frequency of the IF signal 101 <the frequency of the fixed oscillation circuit 104, and the IF signal zero-cross detection signal 202 and the fixed oscillation circuit zero-cross detection signal 206 have waveforms as shown in the figure.
Therefore, the counter value of the second zero-crossing detection counter 207 reaches N earlier than the counter value of the first zero-crossing detection counter 203. The time difference detection circuit 210 outputs the difference signal as a delay time signal 212 to the phase difference detection circuit 213.
The phase difference detection circuit 213 measures the time width of the delay time signal 212 using the clock signal from the clock signal generator 209, and obtains the delay time difference 304. The delay time difference 304 is multiplied by K in order to convert it into a phase, and a phase difference 306 (demodulated baseband signal 106) of one symbol period 302 is calculated.
[0031]
The sample and hold circuit 107 is a circuit that samples and holds the demodulated baseband signal 106 every symbol period.
The determiner 109 compares the sample and hold signal 108 from the sample and hold circuit 107 with the threshold voltage 110. At this time, if the sample and hold signal 108 is large, a high level signal is used, and if the sample and hold signal 108 is small, a low level signal is used. Output , And this becomes the demodulated signal 111.
[0032]
FIG. 4 shows an operation waveform example of a main signal in the frequency shift keying demodulator of the first embodiment.
When the transmission baseband signal 401 has a waveform as shown in the figure, the demodulated baseband signal 106 is converted into a sawtooth signal by the above-described phase difference integrator 105 as shown in the figure.
The sample and hold circuit 107 samples and holds the peak of the demodulated baseband signal 106 for each symbol period. Then, a sample hold signal 108 is output.
The determiner 109 compares the sample and hold signal 108 with the threshold voltage 110 to generate a demodulated signal 111 which is a digital signal.
[0033]
As described above, in the frequency shift keying demodulator of the first embodiment, the phase difference integrator 105 integrates the phase difference between the IF signal 101 and the reference signal from the fixed oscillation circuit 104 for each symbol period. A band signal 106 is generated. The sample hold circuit 107 detects a sample point of the demodulated baseband signal 106 for each symbol period. By comparing the potential at the sample point with the threshold voltage 110, a demodulated signal 111 is generated. Therefore, since a PLL circuit is not required to generate the demodulated baseband signal 106, the overall circuit configuration is simple, and accurate demodulation without the problem of intersymbol interference acting on the demodulated baseband signal 106 can be achieved. it can.
[0034]
<< Example 2 >>
Second Embodiment A frequency shift keying demodulator according to a second embodiment will be described with reference to FIG. FIG. 5 is a block diagram illustrating a configuration of a frequency shift keying demodulator according to a second embodiment to which a filter circuit is added. The configuration of the frequency shift keying demodulator of the second embodiment is different from that of the first embodiment (FIG. 1) in that a filter circuit 501 is added. Otherwise they are identical. The same components are denoted by the same reference numerals, and description thereof will be omitted.
The filter circuit 501 is located between the phase difference integrator 105 and the sample and hold circuit 107, and is a noise removing filter (for example, a low-pass filter) suitable for signal transmission.
In the frequency shift keying demodulator (FIG. 15) using the conventional PLL circuit, the demodulated baseband signal 1504 is fed back to the control voltage of the VCO 1505, and the noise component included in the IF signal 1501, especially phase noise, is also fed back as a signal. Is done. However, adding a filter circuit that separates the demodulated baseband signal 1504 from the noise changes the transfer characteristic of the PLL circuit, resulting in a change in the characteristic of the PLL circuit itself, making it impossible to obtain optimum reception characteristics.
[0035]
However, in the configuration of the frequency shift keying demodulator according to the second embodiment, since it is not necessary to feed back a signal, the signal and noise can be separated by a filter, which is difficult with a frequency shift keying demodulator using a conventional PLL circuit. By improving the signal-to-noise ratio, the reception characteristics can be improved.
[0036]
<< Example 3 >>
Third Embodiment A frequency shift keying demodulator according to a third embodiment will be described with reference to FIGS.
FIG. 6 is a block diagram illustrating a configuration of the frequency shift keying demodulator according to the third embodiment of the present invention. Note that the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.
The fixed oscillation circuit 601 outputs a signal of a fixed frequency (fixed oscillation circuit signal 602) as in the first embodiment, but outputs a signal in synchronization with the symbol synchronization signal 103 from the symbol detector 102. Are different.
FIG. 7 is a logic circuit diagram of the fixed oscillation circuit 601.
In FIG. 7, CLK_A 701, CLK_B 702, CLK_C 703, and CLK_D 704 are oscillation signals (clocks) of the same frequency which are frequency-divided and output at different phases from one fixed-frequency oscillator, respectively. , Have a constant phase difference (for example, π / 2 [rad]).
[0037]
The D latch 707 has a data input terminal 708, a clock input terminal 709, a reset input terminal 710, a Q output terminal 711, and a Q bar output terminal 712.
The ENB 705 resets the four D latches 707 immediately before the start of the wireless frame period 803, which is a group of wireless data strings. The reset period is short, and the ENB 705 does not reset the four D latches 707 (makes them operable) in the other periods. The Q-bar output terminals 712 of the four reset D-latches 707 become HIGH level, and the 4-input AND gate 717 which inputs these signals outputs HIGH level. Four two-input AND gates 716 receive and output CLK_A 701, CLK_B 702, CLK_C 703, and CLK_D 704, respectively.
[0038]
The four D latches 707 enter a state in which CLK_A 701 to CLK_D 704 can be input to the respective clock input terminals 709 (the radio frame period 803 starts).
After the four D-latches 707 are ready to input a clock and the symbol synchronization signal 103 is at the HIGH level (after the start of the symbol period), first, for example, CLK_A 701 changes from the LOW level to the HIGH level. I do. D latch 707 corresponding to CLK_A 701 latches symbol synchronization signal 103 (HIGH level), Q output terminal 711 outputs HIGH level, and Q bar output terminal 712 outputs LOW level. The 4-input AND gate 717 outputs a LOW level because a signal including the LOW level is input. Four two-input AND gates 716 cut off CLK_A 701 to CLK_D 704 and output a LOW level.
[0039]
The selector 715 selects a signal (CLK_A 701) corresponding to the D latch 707 in which the Q output terminal 711 has become HIGH level, and outputs the signal as a fixed oscillation circuit signal 602 (reference signal).
The states of the four D latches 707 do not change over the radio frame period 803.
The above operation is repeated every time a radio frame is input.
Therefore, a signal (one of CLK_A701 to CLK_D704) having a rising timing closest to the rising timing of the symbol synchronization signal 103 is selected for each radio frame period 803, and the selected signal is the fixed oscillation circuit signal 602 (reference signal). Is output as
[0040]
This operation will be described with reference to FIG.
FIG. 8 shows an example of operation waveforms in the fixed oscillation circuit 601.
CLK_A 701, CLK_B 702, CLK_C 703, and CLK_D 704 oscillate from the power-on of the receiving-side system regardless of the symbol synchronization signal 103. Now, it is assumed that ENB 705 is a HIGH level signal, Q output signal 713 from all D latches 707 is a LOW level signal, and Q bar output signal 714 is a HIGH level signal.
Here, after the rising edge 801 of the symbol synchronization signal 103, the CLK_A 701 rises earliest (the rising edge 802 of the CLK_A 701). Therefore, when the clock selection signal 706 of the CLK_A 701 is input to the corresponding latch D707, the latch D707 corresponding to the CLK_A 701 is generated. Changes to a HIGH level (outputs the symbol synchronization signal 103), and the Q bar output signal 714 changes to a LOW level signal.
[0041]
The selector 715 determines the clock (CLK_A 701) in which the Q output signal 713 has changed to the HIGH level, and outputs CLK_A 701 as the fixed oscillation circuit signal 602.
In addition, if the Q-bar output signal 714 goes low at any one of the four D-latches 707, all the clock selection signals 706 go low, so that no change occurs in all the D-latches 707.
This is the same signal during the wireless frame period 803, which is a group of wireless communication data strings.
This state is reset when ENB 705 goes low. When the input of the next radio frame starts, ENB 705 changes to the HIGH level again, and operates so as to select the optimum clock for fixed oscillation circuit signal 602.
[0042]
In the frequency shift keying demodulator of the present invention, the reference signal of the fixed oscillation circuit 601 is preferably synchronized with the symbol synchronization signal 103. As described above, the fixed oscillation circuit 601 of the third embodiment has a plurality of phase shifters. Has a different clock and employs a clock having a phase closer to that of the symbol synchronization signal 103 as the fixed oscillation circuit signal 602, so that this can be realized.
[0043]
<< Example 4 >>
Fourth Embodiment A frequency shift keying demodulator according to a fourth embodiment will be described with reference to FIG. The frequency shift keying demodulator of the fourth embodiment has a configuration in which the fixed oscillation circuit 601 of the second embodiment (FIG. 6) is replaced with a PLL circuit 901. Otherwise they are identical.
The PLL circuit 901 in FIG. 9 includes a phase comparator 902, an LPF 903, a VCO 904, and a frequency divider 905.
Phase comparator 902 compares the phase difference between symbol synchronization signal 103 and the output signal from frequency divider 905, and outputs a phase error signal to LPF 903.
The LPF 903 is a low-pass filter that integrates the phase error signal and outputs a voltage for controlling the VCO 904 (VCO control voltage).
The VCO 904 changes the oscillation frequency by changing the VCO control voltage.
The frequency divider 905 divides the oscillation frequency of the VCO 904.
The PLL circuit 901 controls the oscillation frequency of the VCO 904 so that the phases of the symbol synchronization signal 103 and the output signal of the frequency divider 905 match each other, and can generate a fixed oscillation circuit signal 602 that is phase-synchronized with the symbol synchronization signal 103. .
[0044]
The frequency shift keying demodulator of the fourth embodiment has the same effect as the frequency shift keying demodulator of the third embodiment.
[0045]
<< Example 5 >>
Fifth Embodiment A frequency shift keying demodulator according to a fifth embodiment will be described with reference to FIGS.
FIG. 10 is a block diagram illustrating a configuration of a frequency shift keying demodulator according to a fifth embodiment of the present invention.
The frequency shift keying demodulator according to the fifth embodiment is different from the first embodiment in that a threshold voltage 1004 is generated using a threshold voltage generation circuit 1001. Otherwise they are identical. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. As shown in FIG. 10, the threshold voltage generation circuit 1001 has a maximum hold circuit 1002 and a minimum hold circuit 1003, and the maximum potential of the sample hold signal 108 is set by the maximum hold circuit 1002, and the minimum potential is set by the minimum hold circuit 1003. Detected, and the midpoint between these two potentials is set as a threshold voltage 1004.
[0046]
An operation in the case where there is a difference (frequency offset) between the center frequencies of the fixed oscillation circuit signal 602 from the fixed oscillation circuit 104 and the IF signal 101 will be described.
FIG. 11 shows an embodiment. 5 5 is an example of operation waveforms of each component of the frequency shift keying demodulator in FIG.
Now, in the modulation method of the received frequency shift keying modulation signal, when the transmission baseband signal indicates “+1” and “−1”, the width for increasing or decreasing the frequency from the center frequency is different, and when “+1”. >"-1".
Therefore, when the transmission baseband signal 401 is "+1", the phase shift becomes large, and the plus side amplitude of the demodulated baseband signal 106 becomes large. On the other hand, when the transmission baseband signal 401 is “−1”, the phase shift is small, and thus the amplitude of the demodulated baseband signal 106 on the minus side is small. That is, maximum phase shift> minimum phase shift.
When this signal is sampled and held to generate the sample and hold signal 108, the waveform is shifted in the plus direction as shown in the figure.
[0047]
The threshold voltage generation circuit 1001 detects the maximum potential of the sample and hold signal 108 by using the max hold circuit 1002. Further, the minimum potential of the sample hold signal 108 is detected by using the minimum hold circuit 1003. The threshold voltage generation circuit 1001 generates a threshold voltage 1004 by finding an intermediate potential between the detected maximum potential and minimum potential.
[0048]
As described above, in the frequency shift keying demodulator of the fifth embodiment, the maximum value of the sample hold signal 108 is detected by the maximum hold circuit 1002, and the minimum value of the sample hold signal 108 is detected by the minimum hold circuit 1003. Is set as the threshold voltage 1004 to be compared with the sample-and-hold signal 108. Therefore, even if the IF signal 101 has a frequency offset, for example, the threshold voltage 1004 is automatically adjusted. The baseband signal 106 is determined, and a demodulated signal 111 is output.
[0049]
Further, similarly to the frequency shift keying demodulator of the second embodiment, a filter circuit 501 may be provided between the phase difference integrator 105 and the sample hold circuit 107. In that case, the same effect as that of the frequency shift keying demodulator of the second embodiment is obtained.
[0050]
<< Example 6 >>
Sixth Embodiment A frequency shift keying demodulator according to a sixth embodiment will be described with reference to FIG.
FIG. 12 is a block diagram illustrating a configuration of the frequency shift keying demodulator according to the sixth embodiment of the present invention.
The frequency shift keying demodulator of the sixth embodiment has a low-pass filter 1201 instead of the threshold voltage generation circuit 1001 of the frequency shift keying demodulator of the fifth embodiment. Otherwise they are identical. The same components as those in the fifth embodiment are denoted by the same reference numerals, and description thereof is omitted.
[0051]
The low-pass filter 1201 averages the demodulated baseband signal 106 using a low-pass filter to generate a threshold voltage 1202.
The low-pass filter used here may be a passive filter (a lag filter, a lag-lead filter) formed only of a resistor and a capacitor, or an active filter using an active element such as a transistor.
[0052]
In the frequency shift keying demodulator of the sixth embodiment, even when the IF signal 101 has a frequency offset, the threshold voltage 1202 is automatically adjusted, the demodulated baseband signal 106 is determined with the optimal threshold voltage, and the demodulated signal 111 Can be output.
[0053]
Further, similarly to the frequency shift keying demodulator of the second embodiment, a filter circuit 501 may be provided between the phase difference integrator 105 and the sample hold circuit 107. In that case, the same effect as that of the frequency shift keying demodulator of the second embodiment is obtained.
[0054]
<< Example 7 >>
Seventh Embodiment A frequency shift keying demodulator according to a seventh embodiment will be described with reference to FIGS.
FIG. 13 is a block diagram illustrating a configuration of a frequency shift keying demodulator according to the seventh embodiment of the present invention. The frequency shift keying demodulator of the seventh embodiment has a phase difference integrator 1301 instead of the phase difference integrator 105 of the frequency shift keying demodulator of the first embodiment, and further includes a delay unit 1313. Different from frequency shift keying demodulator. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
In FIG. 13, the phase difference integrator 1301 includes a first zero cross detection circuit 201, a second zero cross detection circuit 205, an initial value voltage generation circuit 1302, a gate circuit 1303, a constant current charger 1305, a constant current discharger 1306, A shift amount detection circuit 1307 and a capacitor 1310 are provided.
[0055]
The initial value voltage generation circuit 1302 supplies a DC voltage of E / 2 (V) (the power supply voltage is E (V)). E / 2 (V) is an intermediate potential in a potential variable range (dynamic range) of the capacitor 1310.
The gate circuit 1303 outputs the DC voltage supplied by the initial value voltage generation circuit 1302 for a certain pulse period, triggered by the signal detection start command 1304 (for example, the rising edge of the wireless frame).
[0056]
The constant current charger 1305 raises the potential of the capacitor 1310 for a certain pulse period every time the rising edge of the IF signal zero cross detection signal 202 is detected.
Each time the constant current discharger 1306 detects the rising edge of the fixed oscillation circuit zero cross detection signal 206, it lowers the potential of the capacitor 1310 for a certain pulse period.
The charge and the discharge at the time of detecting the rising edge are set to be equal.
[0057]
The shift amount detection circuit 1307 includes a low-pass filter 1308 and an operational amplifier 1309. The low-pass filter 1308 outputs an average potential of the capacitor 1310. If the charge per pulse of the constant current charger 1305 is equal to the discharge charge per pulse of the constant current discharger 1306 (if there is no offset), the average potential of the capacitor 1310 is maintained at E / 2 (V). Dripping.
The operational amplifier 1309 amplifies the difference between the output voltage (E / 2 (V)) from the initial value voltage generation circuit 1302 and the input signal (the output voltage from the low-pass filter 1308, that is, the average potential of the capacitor 1310), Output the difference signal.
[0058]
The output voltage of the operational amplifier 1309 is fed back to the constant current charger 1305 and the constant current discharger 1306, so that the average charge of the constant current charger 1305 and the average discharge charge of the constant current discharger 1306 become equal, and the average potential of the capacitor 1310 becomes equal. Is maintained at E / 2 (V), the charge of the constant current charger 1305 and the discharge of the constant current discharger 1306 are controlled.
[0059]
Demodulated baseband signal 1311 output from phase difference integrator 1301 configured as described above has a continuous phase change. (FIG. 14)
The sample and hold circuit 107 samples the demodulated baseband signal 1311 for each symbol synchronization and outputs a sample and hold signal 1312.
The delay unit 1313 outputs a delayed signal 1314 obtained by delaying the sample-and-hold signal 1312 from the sample-and-hold circuit 107 for one symbol period to the decision unit 1315.
The determiner 1315 subtracts the delay signal 1314 from the sample hold signal 1312, and outputs a HIGH level signal when the result is “+” and a LOW level signal otherwise. This becomes the demodulated signal 111. (FIG. 14)
[0060]
As described above, in the frequency shift keying demodulator of the seventh embodiment, the phase difference integrator 1301 does not need a circuit configuration for synchronizing with the symbol synchronization signal 103, and the delay signal 1314 delayed by one symbol period by the delay unit 1313 And a sample hold signal 1312 to generate a demodulated signal 111. This is because a reception characteristic equivalent to that of the frequency shift keying demodulator of the first embodiment can be obtained with a simple circuit configuration, and the frequency offset key problem can be solved similarly to the frequency shift keying demodulator of the fifth or sixth embodiment. Response is possible.
[0061]
Further, similarly to the frequency shift keying demodulator of the second embodiment, a filter circuit 501 may be provided between the phase difference integrator 1301 and the sample hold circuit 107. In that case, the same effect as that of the frequency shift keying demodulator of the second embodiment is obtained.
[0062]
【The invention's effect】
As described above, according to the frequency shift keying demodulator of the present invention, in the process of generating the demodulated baseband signal from the IF signal, the PLL circuit is not directly used, so that the circuit has a simple circuit configuration. Since a signal and noise can be separated by a filter, which has been difficult with a frequency shift keying demodulator using a PLL circuit, accurate demodulation can be performed.
[0063]
Also, when generating a digitized demodulated signal from the signal from the sample-and-hold circuit, the voltage to be compared can be automatically adjusted to a suitable value, so that a frequency offset occurs in the input frequency shift keying modulation signal. But I can cope.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a frequency shift keying demodulator according to a first embodiment of the present invention. Figure It is.
FIG. 2 is a block diagram showing a configuration of a phase difference integrator 105.
FIG. 3 is a diagram illustrating an example of an operation waveform of each component of the phase difference integrator 105.
FIG. 4 is a diagram illustrating an example of operation waveforms of main signals of the frequency shift keying demodulator according to the first embodiment of the present invention.
FIG. 5 is a block diagram illustrating a configuration of a frequency shift keying demodulator according to a second embodiment of the present invention.
FIG. 6 is a block diagram illustrating a configuration of a frequency shift keying demodulator according to a third embodiment of the present invention. Figure It is.
FIG. 7 is a logic circuit diagram of a fixed oscillation circuit 601.
FIG. 8 is a diagram showing an example of operation waveforms in a fixed oscillation circuit 601.
FIG. 9 is a block diagram illustrating a configuration of a PLL circuit 901 of a frequency shift keying demodulator according to a fourth embodiment of the present invention.
FIG. 10 is a block diagram illustrating a configuration of a frequency shift keying demodulator according to a fifth embodiment of the present invention.
FIG. 11 is a diagram illustrating an example of operation waveforms of main signals of a frequency shift keying demodulator according to a fifth embodiment of the present invention.
FIG. 12 is a block diagram illustrating a configuration of a frequency shift keying demodulator according to a sixth embodiment of the present invention.
FIG. 13 is a block diagram illustrating a configuration of a frequency shift keying demodulator according to a seventh embodiment of the present invention.
FIG. 14 is a diagram illustrating an example of operation waveforms of main signals of the frequency shift keying demodulator according to the seventh embodiment of the present invention.
FIG. 15 is a block diagram showing a configuration of a conventional frequency shift keying demodulator.

Claims (10)

A fixed oscillation circuit that oscillates a fixed frequency reference signal;
A phase difference integrator for detecting an integrated value of a phase difference between a frequency shift keying modulated signal obtained by performing modulation by frequency shift using a digital signal as a baseband signal and the reference signal for each symbol period which defines a section of 1-bit data. When,
A symbol detector for detecting a symbol synchronization signal from the frequency shift keying modulation signal,
A sample-and-hold circuit that samples and holds an output signal from the phase difference integrator with a timing signal generated based on the symbol synchronization signal;
A determiner that generates a demodulated signal by comparing an output signal from the sample and hold circuit with a threshold voltage,
A frequency shift keying demodulator comprising: A first zero-cross detection circuit that detects a zero-cross point of the frequency shift keying modulation signal;
A second zero-crossing detection circuit for detecting a zero-crossing point of the reference signal;
A first zero-cross detection counter that counts a detection signal of the first zero-cross detection circuit for each symbol period;
A second zero-cross detection counter that counts a detection signal of the second zero-cross detection circuit for each symbol period;
A time difference detection circuit that measures a time until the first zero-cross detection counter and the second zero-cross detection counter reach a constant value and obtains a time difference between the two;
A phase difference detection circuit for determining a phase difference per symbol period of the frequency shift keying modulation signal from the time difference;
The frequency shift keying demodulator according to claim 1, comprising: A symbol detector for detecting a symbol synchronization signal from a frequency shift keying modulation signal obtained by performing modulation by frequency shift using a digital signal as a baseband signal;
A zero-crossing detection circuit that detects a zero-crossing point of the frequency shift keying modulation signal, a zero-crossing detection counter that counts a detection signal of the zero-crossing detection circuit for each symbol period that defines a 1-bit data section, A time difference detection circuit that measures a time until the time becomes, and obtains a time difference between the measured time and the fixed time, and a phase difference detection circuit that obtains a phase difference per symbol period of the frequency shift keying modulation signal from the time difference. A phase difference integrator having
A sample-and-hold circuit that samples and holds an output signal from the phase difference integrator with a timing signal generated based on the symbol synchronization signal;
A determiner that generates a demodulated signal by comparing an output signal from the sample and hold circuit with a threshold voltage,
A frequency shift keying demodulator comprising: The fixed oscillation circuit generates two or more oscillation output signals having different phases, selects and outputs, as a reference signal, the oscillation output signal having a minimum phase difference with the symbol synchronization signal. A frequency shift keying demodulator according to claim 1. A phase locked loop (hereinafter, referred to as “PLL”) circuit in place of the fixed oscillation circuit;
A phase comparator for comparing a phase difference between the two signals;
A low-pass filter for integrating the output signal of the phase comparator;
A voltage-controlled oscillator whose oscillation frequency changes according to the output signal of the low-pass filter;
A frequency divider for dividing the output signal of the voltage controlled oscillator,
Has,
The PLL circuit controls the voltage controlled oscillator so that the phase of the symbol synchronization signal matches the output signal of the frequency divider, and outputs the output signal of the voltage controlled oscillator as a reference signal.
The frequency shift keying demodulator according to claim 1 or 3, wherein: The frequency shift keying demodulator according to claim 1 or 3, wherein a voltage obtained by averaging an output signal of the phase difference integrator is used as the threshold voltage. 7. The frequency shift keying demodulator according to claim 6, wherein, as the averaging means, a voltage obtained by smoothing an output signal of the phase difference integrator by a low-pass filter is used as the threshold voltage. 7. The frequency shift keying according to claim 6, wherein the averaging unit detects a maximum value and a minimum value of an output signal from the sample and hold circuit, and sets a middle point of each potential as the threshold voltage. Demodulator. Frequency shift keying demodulator according to claim 1 or claim 3, characterized in that it has a low-pass filter circuit for passing only frequencies lower than a certain frequency between said phase difference integrator the sample-and-hold circuit . Frequency shift keying demodulator according to claim 1 or claim 3 characterized by having a band filter circuit for passing only a frequency of a predetermined frequency range between said sample-and-hold circuit and the phase difference integrator.

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