JPH075703Y2 - Signal generation circuit - Google Patents

Description

[Detailed Description of Device] a. [Purpose of Invention] [Industrial field of application] The present invention mainly relates to a PLL used in a frequency synthesizer.
(Phase locked loop) type signal generating circuit,
The present invention relates to improvement of frequency resolution and response time of output signals.

[Conventional technology]

FIG. 3 shows a conventional signal generating circuit of the PLL system. VCO (vo
ltage controlled oscillator:
It is an oscillation circuit whose frequency continuously changes in a certain range by the applied control signal s4. This VCO1 oscillates at a certain frequency corresponding to the voltage of the applied control signal s4.
Then, the output signal s1 of VCO1 is divided by N by the frequency divider 2 to obtain the signal s2.
And the signal s2 is applied to one input terminal of the phase detector 3.

When the reference frequency signal (hereinafter referred to as the reference signal) sr is applied to the other end of the phase detector 3 in such a state, the error voltage signal is generated according to the frequency difference between the frequency of the signal s2 and the reference signal sr or the phase difference. s3 occurs. The loop filter 3 integrates this error voltage signal s3 and feeds back the control signal s4 of a certain voltage obtained as a result to VCO1.

Here, control signal s4 = for VCO1 to output frequency a
Control signal s4 to output Ea (v) and frequency b
= Eb (v) is required.

When the VCO 1 is oscillating stably at the frequency b, a setting signal (not shown) is added to the frequency divider 2 to change the frequency to the frequency a, and the frequency division ratio N is changed from Nb to Na.

By changing the division ratio from Nb to Na, the phase of the signal s2 immediately changes, and therefore the error voltage signal s3 of the phase detector 3 becomes
The value changes from 0v to a certain value (for example, δv). Since the loop filter 4 integrates this δv, the control signal s4 = (Eb +
Δ) → Ea changes. As a result, the VCO1 frequency is also b →
Change to a. In this way, when the frequency of VCO1 becomes a, the phases of the signals sr and s2 match (become the same frequency), the error voltage signal s3 = 0v again, the PLL locks, and the system stabilizes. Therefore, r = ₈₂ = ₈₅ / Na (1) Here, r is the frequency of the reference signal sr, ₈₂ is the frequency of the signal s2, and ₈₅ is the frequency of the signal s1. In this way, the desired frequency can be changed by the setting signal applied to the frequency divider 2.
Can be retrieved from VCO1.

[Problems to be solved by the invention]

 However, the above means has the following problems.

In a frequency synthesizer including a signal generation circuit as described in this specification, it is necessary to extract a high-resolution frequency signal from the signal generation circuit. Since the output frequency ₈₅ is ₈₅ = N · r (N is a frequency division ratio) from the equation (1), the reference frequency r can be set to a low frequency in order to improve the resolution.

On the other hand, since the signal generation circuit using the PLL circuit has the time delay element of the loop filter 4, the VCO 1 changes the frequency division ratio N of the frequency divider 2 by the setting signal and then the VCO 1 outputs the signal of the desired frequency. There is a considerable time delay before output. According to an experiment by the applicant, it takes several tens of times the period (Ts = 1 / r) of the reference signal sr to switch the frequency.

Therefore, if the frequency r of the reference signal sr is set to a low value (the period Ts becomes large) in order to obtain a high-resolution frequency, when switching the output frequency ₈₅ , the switching is made several tens of times the increased period. Since it takes time, there is a problem that the responsiveness becomes very poor. Further, if the reference frequency r is multiplied, the responsiveness does not deteriorate, but a general multiplication circuit has a tuning circuit for the output frequency, and it is very troublesome to make it variable.

The present invention has been made to solve the above problems, and an object of the present invention is to realize a signal generation circuit which has a good responsiveness and can output a high-resolution frequency signal.

B. [Configuration of Device] [Means for Solving Problems] The signal generation circuit according to the present invention is such that the value is sequentially increased in a constant step corresponding to the frequency setting input in synchronization with the VCO and the output signal of the VCO. An accumulator, a ramp wave generator that is reset at a constant cycle by a reference signal, a comparator that compares the output of this ramp wave generator with the output of the accumulator, and the output of this comparator and the VCO output. A phase detector that detects the phase difference between and, and a loop filter that integrates the output of this phase detector and outputs it to the VCO, and frequency signals obtained by multiplying the frequency of the reference signal corresponding to the frequency setting input. It is characterized by being configured to output.

[Action]

Since the number of steps of the accumulator required to reach the maximum output value of the ramp wave generator changes depending on the frequency setting value, it can be changed at a frequency higher than the reference frequency.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of a signal generating circuit according to the present invention. In the figure, 11 is a VC similar to 1 in FIG.
O, 15 are setting registers for inputting the frequency setting signal, 16 is an adder with the output s15 of the setting register 15 as one input, 1
7 is a register that receives and holds the output s16 of the adder 16 and its output s17 is the other input of the adder 16, 25 is an accumulator composed of the adder 16 and register 17, and 18 is a register of the accumulator 25. Output s17
DA converter for converting D to, 19 is a constant current source, 20 is a constant current source 19
One end of the operational amplifier is connected to its inverting input terminal, C is a capacitor whose both ends are connected to the inverting input terminal and output terminal of the operational amplifier 20, 21 is a switch, 26 is an operational amplifier 20, a capacitor C and a switch 21. Is an integrator that constitutes a random ramp wave generator, 22 is the output s20 of the integrator 26
Is held and the output s22 is the reference input of the DA converter 18, and the sample-and-hold circuit is 23.The output s18 of the DA converter 18 is its inverting input and the output s20 of the ramp generator 26 is its non-inverting. Comparator with input, 13 is a phase detector similar to 3 in FIG. 3 with output s23 of comparator 23 being one input and output s11 of VCO11 being the other input, and 14 is a phase detector
A loop filter that integrates the output s13 of 13 and 24 adds the output of the loop filter 14 and the pretune voltage and outputs s24
Is an adder that becomes the control voltage input of VCO11.

The operation of the apparatus having the above configuration will be described with reference to the time chart of FIG. Here, the case where the frequency multiplication ratio Nm is 10, that is, the output frequency fo is fo = Nmr = 10r (2) is shown. The setting register 15 holds 1 / Nm = 0.1 as data. Also, the data input of the DA converter 18 is 1.0
Then the output s18 is equal to the reference input s22.
Furthermore, the output frequency of the VCO 11 is adjusted to the target frequency in advance by the pretune voltage to prevent erroneous lock. The operation procedure is shown below.

The rising of the reference signal sr clears the contents of the register 17. At the same time, the integrator 26 is reset by the switch 21, and the ramp waveform rises immediately. Then the comparator
Since the input of 23 is large on the non-inverting side, it immediately rises.

The content of the register 17 changes at the falling edge of the output of the VCO 11. Here, new register value = old register value + setting register value (here, 0.1) (3). As a result, the output s23 of the comparator 23 falls.

Next, the non-inverting input side of the comparator 23 is again increased by the integrator 26, and the comparator output s23 rises.

Next, the contents of the register 17 are updated (becomes 0.2) at the fall of the VCO11 output s11. The same operation is repeated thereafter.

The content of register 17 is updated to 1.0.

The integrator output becomes a value corresponding to 1.0, and the comparison output s23 rises. Almost at the same time, the reference signal sr rises, and the peak value of the ramp wave of one cycle of the reference signal sr sampled by the sample and hold circuit 22 at this timing becomes the reference input of the DA converter 18. The same operation is repeated thereafter.

The output s23 of the comparator 23 is output at a timing based on the reference signal sr, and in the above specific example, the period Ts of the reference signal sr = 1 /
It is equal to r divided into 10 equal parts. Therefore this signal
Phase comparison between s23 and VCO11 output s13, loop filter 14,
By feeding back to the VCO 11 via the adder 24 to form a PLL, it is possible to obtain a frequency signal which is synchronized with and multiplied by the reference signal sr as the VCO output s11.

According to the signal generating circuit having such a configuration, since the frequency of the reference signal is multiplied, the input frequency of the phase detector is high and the response is fast.

Also, since the multiplication number is arbitrary, any desired frequency can be set.

In the above embodiment, the output of the VCO 11 of FIG. 1 may be added to the phase detector 13 and the register 17 via the frequency divider. When the M divider is used, the output frequency fo is fo = MNmr (4).

Further, in the above embodiment, if a digital output ramp generator is used and its output is compared with the output of the accumulator 25 by a digital comparator, the DA converter can be omitted.

C. [Advantages of the Invention] As described above, according to the invention, it is possible to realize a PLL type signal generation circuit having a good response and capable of outputting a high-resolution frequency signal with a simple configuration. .

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a signal generating circuit according to the present invention, FIG. 2 is a time chart showing the operation of the device shown in FIG. 1,
FIG. 3 is a diagram showing a conventional signal generating circuit of the PLL system. 11 …… VCO, 13 …… Phase detector, 14 …… Loop filter, 23 …… Comparator, 25 …… Accumulator, 26 …… Ramp wave generator, sr …… Reference signal, sf …… Frequency setting input.

Claims (1)

[Scope of utility model registration request] 1. A voltage-controlled oscillator, an accumulator whose value sequentially increases in synchronization with an output signal of the voltage-controlled oscillator in a constant step corresponding to a frequency setting input, and a ramp reset by a reference signal in a constant cycle. A wave generator, a comparator for comparing the output of the ramp wave generator with the output of the accumulator, and a phase detector for detecting the phase difference between the output of the comparator and the output of the voltage controlled oscillator, A loop filter that integrates the output of the phase detector and outputs it to the voltage controlled oscillator, and is configured to output a frequency signal obtained by multiplying the frequency of the reference signal corresponding to the frequency setting input. Signal generation circuit.