JPH05259904A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To improve the phase lock-in characteristic and to increase the phase lock-in speed by eliminating the higher harmonic of the input voltage of a voltage control oscillator VCO and storing the phase error signal data for each specific frequency. CONSTITUTION:The oscillation output frequency of a VCO 21 is kept in a variable range equal to one channel of the input voltage of the VCO 21 when the VCO 21 is started. Then the input voltage gradually approximate to a point closest to the oscillation frequency in the variable range for a single period T. When the period T is over, the period T is equal to 2T with a phase error signal 104 kept at 0. Then the input voltage range of the VCO 21 is equal to 1/2 channel and the input voltage of the VCO 21 gradually approximate to a point closest to the oscillation output frequency with double accuracy compared with the level of the period T. Therefore the oscillation output signal 108 of the VCO 21 is stabilized and the phase error data is stored in an error data table RAM 24. This error data is referred to in the next frequency setting state and the phase lock-in time can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer, and more particularly to a frequency synthesizer that utilizes the output frequency of a voltage controlled oscillator controlled via a phase locked system.

[0002]

2. Description of the Related Art A conventional frequency synthesizer has a reference signal generator 1, a phase comparator 34, a low-pass filter 35, a VCO (voltage controlled oscillator) 21, and a block diagram shown in FIG. It is configured as a phase-locked system including a switch 22, a programmable counter 36, and a CPU 27, and the oscillation output signal of the VCO 21 is input to the programmable counter 36 controlled by the CPU 27 and divided. , The reference signal 10 input to the phase comparator 34 and output from the reference signal generator 1.
The phase detection output signal that is phase-compared with 1 and is output from the phase comparator 34 through the phase comparison of both signals is integrated in the low-pass filter 35, and the phase error signal corresponding to the phase difference between the both signals is VCO 21. Input to VCO21
The frequency stability of the oscillating output signal output from the output is maintained at a specified value. In this case, program counter 3
The frequency division value in 6 is controlled by the CPU 27, so the frequency of the oscillation output signal of the VCO 21 is set to a desired frequency value via this control action. Then, the oscillation output signal of the VCO 21 is output to the outside via the switch 22 whose on / off is controlled by the CPU 27.

[0003]

In the above-mentioned conventional frequency synthesizer, the frequency switching time of the output signal cannot be shorter than the time constant of the low pass filter 35 in the loop. Generally, several tens of msec
If the frequency switching time is shortened, the frequency stability of the oscillation output signal of the VCO 21 deteriorates. There is a strong correlation between this frequency switching time and the frequency stability of the oscillation output signal of the VCO 21, and the bandwidth of the low-pass filter 35 is set in order to remove harmonic components and obtain a stable output signal. If it is narrowed, there is a drawback that the time constant becomes large and the frequency switching time is delayed.

Further, as a method of improving the frequency pull-in characteristic in the phase locked system shown in FIG. 6, a method of decreasing the time constant only at the time of pulling in, a method of increasing the loop gain only at the time of pulling in, and switching the phase comparison frequency. , The method of effectively switching the loop gain, and the D / A converter superimposes the DC voltage corresponding to the desired output frequency on the VCO input voltage at the time of switching the division ratio to make the VCO output frequency as much as possible. There is a method of bringing them closer to each other and then pulling in only the difference frequency. However,
The above methods (1) and (2) have the disadvantage that the phase comparison characteristic has a periodicity, so that a phase error signal of opposite polarity is temporarily output during pulling in, and the pulling operation deteriorates. However, if the characteristics cannot be accurately grasped due to the frequency drift of the VCO 21 or the like, there is a drawback that the pull-in time is not improved much.

That is, in either method, since the phase error signal output from the phase comparator 34 contains harmonic components, a fundamental solution to the high-speed pull-in characteristic and frequency stability. There is a drawback that is not.

[0006]

A frequency synthesizer of the present invention is a frequency synthesizer including a phase-locked system formed corresponding to a reference frequency signal output from a predetermined reference frequency generating means, wherein the reference frequency signal is The reference phase component generated by counting and the feedback phase component generated by counting the oscillation output frequency of the voltage controlled oscillator included in the phase-locked system are passed through a predetermined digital arithmetic process, Phase error detecting means for detecting and outputting a phase error component corresponding to the component, zero phase error detecting means for detecting that the phase error component in the phase error detecting means is zero, and zero phase error detecting means Feedback phase control means for controlling and adjusting the cycle of the feedback phase component via a detection signal indicating that the output phase error component is zero; Gain control means for controlling and adjusting the amplification gain of the phase error component in the phase synchronization system via a detection signal indicating that the phase error component output from the zero phase error detection means is zero, and the feedback phase control. Means and a learning storage means for individually storing the phase error signal data corresponding to the plurality of specific frequencies obtained by the gain control means, and when the frequency is set next time, the learning data of the specific frequency is provided. It is characterized by shortening the frequency pull-in time with reference.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, this embodiment includes a reference phase generation circuit 3 including a reference signal generator 1 and a binary counter 2, a compare register 4, a reference frequency counting shift register 5, and a phase comparator 6. , Zero-phase error detection circuit 7, one-shot pulse circuit 8, amplifiers 9, 10, 16 and 18, and adders 11 and 17
And ε setting register (phase error setting register) 12,
Programmable divider 13, binary counter 14, D / A converters 15 and 19, base data register 20, VCO 21, base data table R
OM23, error data table RAM24, NO
The R circuits 25 and 26 and the CPU 27 are provided.

In FIG. 1, a reference phase signal 102 output from a reference phase generator circuit 3 including a reference signal generator 1 and a binary counter 2 is a reference frequency f _r of a reference signal 101 output from the reference signal generator 1. Corresponding to
slide into change for each _s / f _r. The oscillation output signal 108 of the VCO 21 is counted by the binary counter 14, and its output signal 110 is input to the programmable divider 13 and divided by M to match the dimension of the reference phase signal 102. Where VC
The oscillation frequency of O21 is f _n, and N = 0, 1, 2, 3,
.., M = (f _n / f _r ) * 2 ^N. The frequency-divided signal 111 divided by M in the programmable divider 13 is input to the phase comparator 6. Phase comparator 6
, The phase comparison between the reference phase signal 102 and the frequency-divided signal 111 divided by M in the programmable divider 13 is performed through arithmetic processing, and the phase error signal 1
04 is output. The phase error signal 104 is amplified by the amplifiers 9 and 10, is input to the adder 11, and is added to the value of the phase error setting signal 105 output from the ε setting register 12. The addition output signal 106 of the adder 11 is converted into an analog signal in the D / A converter 15, amplified by the amplifier 16, and input to the adder 17.

On the other hand, the CPU 27 transfers the data signal 114 corresponding to the designated frequency channel preset in the base data table ROM 23 to the base data register 20 and the D / A via the base data register 20. It is converted into an analog signal by the converter 19, amplified by the amplifier 18, and input to the adder 17. In the adder 17, the signal output from the amplifier 16 is added, and the added output signal 107 is added to the VCO 21.
Entered in.

Now, the phase component of the reference phase signal 102 is φ _r
(T), the phase component of the M divided signal 111 output from the programmable divider 13 is ψ (t),
The phase error component of the phase error signal 104 output from the phase comparator 6 is represented by ε (t) (φ (t) −φ (t)) and the amplifier 9
When the gains of 10 and 10 are G ₄ and G ₃ , respectively, and the value of the phase error setting signal 105 output from the ε setting register 12 is d ₁ (t), the value d of the addition output signal 106 output from the adder 11 is d. ₂ (t) is given by the following equation.

D ₂ (t) = d ₁ (t) + G ₃ · G ₄ · ε (t) = d ₂ (t−1) + G ₃ · G ₄ · ε (t) ………… (1) This added value d ₂ (t) is an analog signal of G ₂ · d ₂ (t), where the gain of the amplifier 16 is G _2.
7 is input to the base data table ROM described above.
The data value set in 23 is d _ch (t), and the amplifier 1
When the gains of 6 and 18 are G ₂ and G ₁ , respectively, the addition value d ₃ of the addition output signal 107 by the adder 17 is
(T) is given by the following equation.

D ₃ (t) = G ₁ · d _ch (t) + G ₂ · d ₂ (t) (2) where the phase components φ _r (t) and ψ (t) Is a periodic function in which the value N set in the reference frequency counting shift register 5 is 2π radians. This is because the binary counter 2 and the binary counter 14 are reset when the value N of the reference frequency counting shift register 5 and the value φ (t) of the binary counter 2 match. The value N of the reference frequency counting shift register 5 changes depending on the state of the value ε (t) of the phase error signal 104. That is, the value of ε (t) is calculated by the zero-phase error detection circuit 7 at every 1 / _fr time.
The state of = 0 is monitored, and when ε (t) = 0, φ
When (t) = N, the output of the one-shot pulse circuit 8 is accepted, the shift is performed in the reference frequency counting shift register 5, and the value N is doubled.
This behavior is as seen in the timing diagrams shown in FIGS. 2 (a) and 2 (b), where φ (t) (FIG. 2 (a)
2) if the period of the reference) is 0 according to the phase error signal 104,
It can be seen that it does not change unless doubled or 0. This cycle is related to the frequency measurement accuracy of the oscillation output signal 108 output from the VCO 21, and the frequency measurement accuracy of the oscillation output signal 108 improves as the cycle increases. This is
There is a similar relationship within one cycle, and the measurement accuracy of the reference frequency rises with time. The correction for that is performed in the amplifiers 9 and 10. The amplifier 9 functions for correction within one cycle, and the binary counter 2
As the count value of increases, its amplification rate decreases. Further, the amplifier 10 also acts as a correction for each cycle, and as the count value of the reference frequency counter shift register 5 increases, the amplification rate thereof decreases.

The phase error component ε of the phase error signal 104
(T) is expressed by the above-mentioned equation (1).
And 10 and a value d ₂ (t) of the addition output signal 106 output from the adder 11 via the adder 11 as the following equation.

D ₂ (t) = d ₁ (t) + G ₃ · G ₄ · ε (t) The phase error component ε (t) of the phase error signal 104 is set as a specified frequency from the error data table RAM 24 for initial setting. The data corresponding to the channel is set by the CPU 27, but after that, it is updated by d ₂ (t) in the above equation every 1 / _fr time. Then, when the desired frequency measurement accuracy of the oscillation output signal 108 of the VCO 21 is obtained, the value of the phase error setting register 12 is used as update data and the error data table RAM 24 is used.
The CPU 27 performs an operation of rewriting the contents of the above. Since the resolution problem in the D / A converter 19 is involved, the one-shot pulse circuit 8 is prohibited from outputting after the designated number of pulses have been transmitted after the start.

FIGS. 3A and 3B show the contents of the base data table ROM 23 and the error data table RAM 24, respectively. In Figure (a),
Base data is written for each channel, and phase error data ε (t) is written for each channel in FIG. The relationship between these two data is that the base data is coarse adjustment data and the ε data is fine adjustment data. This will be specifically described with reference to FIG. FIG. 4 shows that when the ε data is 0 and the designated frequency of the VCO 21 is desired to be set to f _n1 , the frequency is set to V _n.
It shows how the fluctuation range of the input voltage of the CO 21 becomes, and the base data d _ch is ½ of the band for one channel centered on the specified frequency even when the ε data is 0. It is supposed to be set to enter.

The oscillation output frequency f _n of the VCO 21 at the time of start is the input voltage [d
The variable range of ₃ (t)] is ₁ centered on G ₁ · d _chn
It is within the channel range. And one cycle (= T)
During this period, the input voltage gradually approaches the position closest to f _n1 in the variable range. Then, when ε = 0 at the end of one cycle, one cycle = 2T, and the input voltage range of the VCO 21 becomes 1/2 of one channel.
The input voltage to the VCO 21 gradually approaches the position closest to f _n1 with double accuracy as compared with the case of the cycle = T. Thereafter, such an operation is repeatedly performed, and the VCO
The input voltage to 21, that is, the value d ₃ (t) of the addition output signal 107 output from the adder 17 finally becomes the following expression.

D ₃ (t) = G ₁ · d _ch (t) + G ₂ · {d (t) + G ₃ · G ₄ · ε (t)} = G ₁ · d _ch (t) + G ₂ · d ( t) = G ₁ · d _ch (t) + G ₂ · dε _n Therefore, the oscillation output frequency of the oscillation output signal 108 of the VCO 21 stabilizes at f _n1 , and dε _n is stored in the error data table RAM 24.

The switch 22 acts so as not to send the oscillation output signal 108 of the VCO 21 to the outside until the time when the frequency becomes stable.

Next, FIG. 6 is a block diagram showing a second embodiment of the present invention. As shown in FIG. 6, in this embodiment, a reference phase generation circuit 3 including a reference signal generator 1 and a binary counter 2, a compare register 4, a phase comparator 6, a zero phase error detection circuit 7, A one-shot pulse circuit 8, amplifiers 9, 10, 16 and 18, adders 11 and 17, a phase error setting register 12,
Programmable divider 13, binary counter 14, D / A converters 15 and 19, base data register 20, VCO 21, base data table R
OM23, error data table RAM24, NO
R circuits 25 and 26, CPU 27, data setting register 28, reference frequency count register 33 corresponding to this data setting register 28, data setting register 30, and gain control register corresponding to this data setting register 30. 29, a data setting register 32,
A divider data register 31 corresponding to this data setting register is provided.

The difference between this embodiment and the first embodiment is C
Corresponding to the data setting by the PU 27, the data setting register 28 and the reference frequency counting register 33 corresponding to the data setting register 28, the data setting register 30 and the gain control register 29 corresponding to the data setting register 30, and the data setting The divide data register 31 corresponding to the data register 32 and the data setting register 32 is added, whereby the length of one cycle and the gains of the amplifiers 10 and 18 are
It can be arbitrarily set by the CPU 27, and has an advantage that the oscillation frequency accuracy of the VCO 21 can be further improved as compared with the first embodiment.

[0022]

As described above, according to the present invention, the VCO
For the input voltage to, the unnecessary harmonics are removed, so there is no need to insert a low-pass filter, and there is the effect that the phase pull-in characteristic in the phase-locked system is greatly improved. Since the learning function of storing the phase error signal data for each is provided, it becomes possible to narrow the input voltage range of the VCO from the beginning by adopting the value when the frequency is set next time. Has the effect of being speeded up.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a phase of a reference phase signal in the first embodiment.

FIG. 3 is a base data table R in the first embodiment.
It is a figure which shows the content of OM and an error data table.

FIG. 4 is a VCO input voltage and VCO in the first embodiment.
It is a figure which shows the relationship of an oscillation output frequency.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

FIG. 6 is a block diagram showing a conventional example.

[Description of Reference Signs] 1 reference signal generator 2, 14 binary counter 3 reference phase generation circuit 4 compare register 5 reference frequency counter shift register 6, 34 phase comparator 7 phase error detection circuit 8 one-shot pulse generation circuit 9, 10, 16, 18 Amplifier 11, 17 Adder 12 ε setting register 13 Programmable divider 15, 19 A / D converter 20 Base data register 21 VCO 22 Switch 23 Base data table ROM 24 Error data table RAM 25, 26 NOR circuit 27 CPU 28, 30, 32 Data setting register 29 Gain setting register 31 Divide data register 33 Reference frequency count register 35 Low-pass filter 36 Programmable counter

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 9182-5J H03L 7/10 A

Claims (1)

[Claims] 1. A frequency synthesizer including a phase synchronization system formed corresponding to a reference frequency signal output from a predetermined reference frequency generating means, and a reference phase component generated by counting the reference frequency signal, The feedback phase component generated by counting the oscillation output frequency of the voltage-controlled oscillator included in the phase-locked system is detected through the predetermined digital arithmetic processing to detect the phase error component corresponding to the both phase components. Phase error detecting means for outputting, zero phase error detecting means for detecting that the phase error component in the phase error detecting means is zero, and phase error component output by the zero phase error detecting means being zero Feedback phase control means for controlling and adjusting the cycle of the feedback phase component, and a phase error output from the zero phase error detection means via a detection signal indicating A gain control means for controlling and adjusting the amplification gain of the phase error component in the phase synchronization system via a detection signal indicating that the minute is zero, the feedback phase control means, and a plurality of gain control means obtained by the gain control means. Learning storage means for individually storing phase error signal data corresponding to a specific frequency, and shortening the frequency pull-in time by referring to the learning data of the specific frequency when setting the frequency next time. A frequency synthesizer featuring.