JPH0733467Y2 - Digital phase locked loop circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital phase locked loop circuit, and more particularly to a digital phase locked loop circuit used for a tuner local oscillator, a music synthesizer, or the like.

2. Description of the Related Art FIG. 3 shows a block diagram of an example of a conventional phase locked loop (PLL) circuit. In the figure, voltage-controlled oscillator (VCO)
_{Reference numeral} 1 is an oscillator whose output frequency f _VCO is variable depending on the input voltage. The output of VCO1 is taken out as the output of the entire PLL circuit and supplied to the prescaler 2 to be a pulse signal, and the frequency is 1 / P (the value of P is, for example,
128) is divided.

The output of the prescaler 2 is further divided into 1 / N in the frequency dividing circuit 3, but the value of this N is variable, and by changing the value of this N, the output frequency of the VCO 1 can be set to any value, as will be described later. Can be set to the value of.

The reference frequency oscillator (f _ref oscillator) 4 has a reference frequency (f _ref
ref ) is a high-precision crystal oscillation circuit that oscillates the signal
This output is frequency-divided into 1 / R by the frequency dividing circuit 5 and then input to the phase comparison circuit 6.

The phase comparison circuit 6 compares the phases of the output signals of the frequency dividing circuits 3 and 5, and outputs a pulse (phase error signal) having a width corresponding to the comparison result. The phase comparison circuit 6 is, for example, a circuit having an exclusive OR gate as a center, and the frequency dividing circuits 3 and 5 are provided.
When the outputs of 1 are at the same level, a high level signal is output, and when the outputs of the frequency dividing circuits 3 and 5 are at different levels, a low level signal is output.

The low pass filter (LPF) 7 integrates the output pulse signal of the phase comparison circuit 6 and supplies it to VCO1. Therefore, the phase comparison circuit 6
The pulse width change of the output pulse signal is supplied to the VCO 1 as a voltage value change, and the VCO 1 oscillates and outputs a signal having a frequency corresponding to the voltage value.

From the above, the output frequency f _{VCO of} VCO1 is Oscillation is stably continued at the frequency represented by, and the output frequency f _VCO can be set to a desired frequency by changing N as described above.

Problems to be Solved by the Invention However, since the conventional circuit shown in FIG. 3 is composed only of hardware, phase noise (f _VCO fluctuation phenomenon due to changes in ambient temperature or changes in circuit elements over time). ) Occurs, the stability is not sufficient, and when changing the frequency, it is difficult to shorten the time (lock-up time) until a signal of that frequency is stably output. was there.

The present invention has been made in view of the above points, and an object of the present invention is to provide a digital phase locked loop circuit capable of improving phase noise and shortening lock-up time.

The present invention includes a variable frequency oscillator circuit, a variable frequency divider circuit that divides the output signal of the variable frequency oscillator circuit, and a software program. A first digital signal related to the first digital signal relating to the frequency division ratio of the variable frequency dividing circuit, which stores the first digital signal relating to Digital / analog conversion means for outputting an analog signal for changing the oscillation frequency of the variable frequency oscillation circuit by supplying the second digital signal from the outside after the digital signal is supplied, and the software program described above. The frequency is detected by counting the number of output pulses of the variable frequency divider circuit, and the difference between the frequency and the reference frequency is detected. The second digital signal corresponding to the frequency division ratio is generated, and after the frequency division ratio of the variable frequency dividing circuit is changed, the first digital signal corresponding to the frequency division ratio is stored based on the address value of the storage means. A second digital signal which is read from the means and supplied to the digital / analog converting means, and when the output frequency of the variable frequency dividing circuit differs from the reference frequency, the output frequency of the variable frequency dividing circuit becomes equal to the reference frequency. And a control means for controlling the supply to the digital / analog conversion means.

When the frequency division ratio of the variable frequency dividing circuit is changed, the first digital signal output from the storage means is also changed to a predetermined signal,
The oscillation frequency of the variable frequency oscillating circuit changes due to the change in the output analog signal of the digital / analog converting means.

After that, the frequency of the output signal of the variable frequency dividing circuit is detected by the frequency detecting means and compared with the reference frequency. When this frequency is different from the reference frequency, the output level of the digital / analog conversion means is further changed by the second digital signal, thereby changing the oscillation frequency of the variable frequency oscillation circuit. When the frequency of the variable frequency dividing circuit becomes equal to the reference frequency, the oscillation frequency of the variable frequency oscillating circuit is determined to be a predetermined frequency, and this frequency is maintained.

The operation in which the first digital signal is read from the storage means and supplied to the digital / analog conversion means, and the second digital signal in which the output frequency of the variable frequency dividing circuit becomes equal to the reference frequency is digital / analog converted. The operation supplied to the means is controlled by the control means which operates based on the software program stored in the storage means.

Embodiment FIG. 1 shows a block diagram of an embodiment of the present invention. In the figure, the same components as those in FIG. 3 are designated by the same reference numerals, and the description thereof will be omitted. The pulse signal oscillated by the voltage controlled oscillator (VCO) 1 and made into a pulse signal by the prescaler 2 and having the frequency reduced to P / 1 is further frequency reduced to 1 / N by the frequency dividing circuit 3. The frequency dividing ratio N of the frequency dividing circuit 3 is variable. When the value of this N changes, the central processing circuit (CPU) 10 causes the read only memory (RO
M) 11 address is changed and supplied to ROM11, ROM11
Outputs digital data corresponding to this address and supplies it to the digital / analog conversion circuit (D / A converter) 12.

In the present embodiment, the ROM 11 has C
The software for operating the PU10 is also stored, and this software program causes the CPU10 to execute the second
The operation is performed according to the flowchart shown in the figure. This software program and the CPU 10 constitute a control means.

The clock pulse signal of the clock oscillator 13 connected to the CPU 10 not only becomes the clock pulse of the CPU 10, but also serves as a reference signal for detecting the pulse width, that is, the frequency of the output pulse signal of the frequency dividing circuit 3. Random access
The memory (RAM) 14 is a storage device that can temporarily store the data that appears during the operation of the CPU 10 and can read it out as needed. The interface circuit (I / O) 15 includes various switches and display devices and the CPU 10 and the like. Interface with.

The output pulse signal of the frequency dividing circuit 3 is supplied to the interrupt terminal INT of the CPU 10, and the clock pulse generated during one pulse of this output pulse signal is counted to determine the output pulse width of the frequency dividing circuit 3 or the frequency from this. To detect. Digital data corresponding to the detected frequency is supplied to the D / A converter 12, and the D / A converter 12 outputs analog data having a voltage value corresponding to the input digital data. The output voltage of this D / A converter is smoothed by the low pass filter (LPF) 7 and supplied to VCO1, and the change in this voltage value causes VCO1 to output a signal of a predetermined frequency.

FIG. 2 is a flow chart showing the operation of this embodiment, and the operation of this flow chart is executed by the control means constituted by the software program stored in the ROM 11 of FIG. 1 and the CPU 10. This flowchart will be described below.

In step 1 (hereinafter abbreviated as S ₁ etc.), preset initial value data is sent from the ROM 11 to the D / A converter 12,
VCO1 oscillates at a frequency corresponding to the output voltage of this D / A converter.

At S ₂ , it is judged whether the frequency has been changed,
If the frequency is not changed, in S ₃ , processing other than the frequency change is performed. With processing other than this frequency change,
For example, when this device is used in a tuner of a television receiver, it is detection of channel input.

If it is determined in S ₂ that the frequency has been changed, the digital data corresponding to the new N value of the frequency dividing circuit 3 is stored in the ROM 11
It is read out and supplied to the D / A converter 12. This N
The digital data corresponding to the value of is not the digital data that finally determines the oscillation frequency of VCO1, but is the approximate data for promptly approaching the desired frequency.

In S ₄ , the number of clock pulses generated in one pulse of the output pulse signal of the frequency dividing circuit 3 is counted, and when the number of clock pulses is larger than a predetermined number (when the frequency is low), the D / A converter in S ₆ When the output level of 12 is increased and the number of clock pulses generated in one pulse of the output pulse signal of the frequency dividing circuit 3 is less than the predetermined number (when the frequency is high), the output of the D / A converter 12 in S ₇ Decrease the level. or,
When the number of clock pulses in one pulse of the output pulse signal of the frequency dividing circuit 3 reaches a predetermined number, the output of the D / A converter is kept constant.

By repeating the above operation, the pulse width of the output pulse signal of the frequency dividing circuit 3 is immediately set to the predetermined pulse width (that is, set to the predetermined frequency), and the VCO 1 outputs the output pulse signal of the predetermined frequency. It will be.

In the present embodiment, the frequency is changed by changing the frequency division ratio N of the frequency dividing circuit 3, but in addition, the frequency division ratio of the prescaler 2 is changed (for example, 1 / P → 1 /).
Even in the so-called pulse swallow method (which is changed to (P + 1)), the prescaler 2 directly from the CPU 10
By controlling the division ratio of, the same effect as above can be obtained.

In addition, the superposition AF used in the tuner of a TV receiver
When the present invention is applied to C, it is possible to first determine the center frequency by a synthesizer and then operate the superposition AFC. In the case of such a configuration, higher stability can be realized as compared with the case of combining the conventional voltage control type synthesizer and the AFC.

Effect of the Invention As described above, according to the present invention, the data corresponding to the predetermined frequency is selected by software according to the result of the frequency comparison, so that the ambient temperature changes or the circuit element changes with time. Even in this case, the phase noise is small and stable, the lockup time can be shortened, and the circuit configuration can be simplified. Further, it has a feature that the plan change such as the change of the center frequency can be easily performed by rewriting the software program stored in the storage means.

[Brief description of drawings]

FIG. 1 is a block diagram of a circuit of an embodiment of the present invention, FIG. 2 is a flow chart showing the operation of the circuit of FIG. 1, and FIG. 3 is a block diagram of a conventional circuit. 1 ... Voltage controlled oscillator (VCO), 2 ... Prescaler,
3, 5 ...... Divider circuit, 7 ...... Low pass filter (LPF), 10
...... Central processing circuit (CPU), 11 …… Read only memory (ROM), 12 …… D / A converter, 14 …… Random access memory (RAM).

Claims (1)

[Scope of utility model registration request] 1. A variable frequency oscillating circuit, a variable frequency dividing circuit for dividing an output signal of the variable frequency oscillating circuit, and a software program are stored. A storage unit that stores a digital signal in advance and reads out the predetermined first digital signal whose address value is changed according to the frequency division ratio of the variable frequency dividing circuit; and the first unit read out from the storage unit. Digital / analog conversion means for outputting an analog signal for changing the oscillation frequency of the variable frequency oscillation circuit by being supplied with a second digital signal from the outside after being supplied with the digital signal, and the above software program. The frequency is detected by counting the number of output pulses of the variable frequency dividing circuit, and the frequency is detected according to the difference between the frequency and the reference frequency. The second digital signal is generated, and after the frequency division ratio of the variable frequency dividing circuit is changed, the first digital signal corresponding to the frequency division ratio based on the address value of the storage means. From the storage means to read the digital /
The second frequency is supplied to the analog converting means, and when the output frequency of the variable frequency dividing circuit is different from the reference frequency, the output frequency of the variable frequency dividing circuit becomes equal to the reference frequency.
And a control means for controlling the digital signal to be supplied to the digital / analog conversion means.