JPS6048618A - Frequency synthesizer circuit - Google Patents
Frequency synthesizer circuitInfo
- Publication number
- JPS6048618A JPS6048618A JP58157444A JP15744483A JPS6048618A JP S6048618 A JPS6048618 A JP S6048618A JP 58157444 A JP58157444 A JP 58157444A JP 15744483 A JP15744483 A JP 15744483A JP S6048618 A JPS6048618 A JP S6048618A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- frequency
- voltage
- control
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/187—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
- H03L7/189—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop comprising a D/A converter for generating a coarse tuning voltage
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は、通信機器の周波数源として適する周波数シン
セサイザ回路の改良に関する。特に、指定周波数の切換
が高速に行われる周波数シンセサイザ回路に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to an improvement in a frequency synthesizer circuit suitable as a frequency source for communication equipment. In particular, the present invention relates to a frequency synthesizer circuit in which switching of designated frequencies is performed at high speed.
通信周波数を通信の都度指定変更して使用する通信装置
では、その周波数源として位相同期形の周波数シソセサ
イザ回路が広く使用されている。2. Description of the Related Art In communication devices that use a communication frequency that is changed each time a communication is made, a phase-locked frequency selector circuit is widely used as a frequency source.
第１図にこのための従来例回路を示す。第１図で端子１
は周波数指定信号の入力端子であり、端子２は出力信号
端子である。水晶などの安定な素子により制御された基
準発振回路３の出力は位相比較回路４の一方の入力に与
えられ、その位相比較回路４の出力信号は低域濾波器５
を介して電圧制御発振回路６の制御入力に印加される。FIG. 1 shows a conventional circuit for this purpose. Terminal 1 in Figure 1
is an input terminal for a frequency designation signal, and terminal 2 is an output signal terminal. The output of the reference oscillation circuit 3 controlled by a stable element such as a crystal is given to one input of a phase comparison circuit 4, and the output signal of the phase comparison circuit 4 is passed through a low-pass filter 5.
The voltage is applied to the control input of the voltage controlled oscillation circuit 6 via the voltage controlled oscillation circuit 6.
電圧制御発振回路６の出力は出力端子２に与えられると
ともに分岐されて、分周回路７に導かれＮ分の１に分周
されて位相比較回路４の他方の入力に与えられる。分周
回路７の分周比は端子１に与えられる周波数指定信号に
応じて制御回路８により切替え制御される。The output of the voltage controlled oscillation circuit 6 is applied to the output terminal 2, branched off, guided to the frequency divider circuit 7, frequency-divided by N/N, and applied to the other input of the phase comparator circuit 4. The frequency dividing ratio of the frequency dividing circuit 7 is switched and controlled by the control circuit 8 according to a frequency designation signal applied to the terminal 1.
このような回路は、基準発振回路３の出力信号に同期す
る位相制御ループが構成されて、出力周波数の安定度を
極めて高くすることができる。また、基準発振回路３の
出力周波数をｆｏとすると、電圧制御発振回路６の出力
周波数ｆは、ｆ −Ｎ ｆ ｏ ・・・・・・（１）と
なるので、分周比Ｎを変更することにより基準周波数ｒ
ｏの整数倍の出力周波数を得ることができる優れた特長
があり、移動無線通信装置の周波数源として広く使用さ
れている。In such a circuit, a phase control loop synchronized with the output signal of the reference oscillation circuit 3 is configured, and the stability of the output frequency can be made extremely high. Furthermore, if the output frequency of the reference oscillation circuit 3 is fo, the output frequency f of the voltage controlled oscillation circuit 6 becomes f - N f o (1), so the frequency division ratio N is changed. Therefore, the reference frequency r
It has the excellent feature of being able to obtain an output frequency that is an integer multiple of o, and is widely used as a frequency source for mobile radio communication devices.
しかし、電圧制御発振回路６の電圧−周波数特性は第２
図に例示するような特性であって、出力周波数に応じて
その制御入力電圧を大きく変化させなければならない。However, the voltage-frequency characteristics of the voltage controlled oscillation circuit 6 are
The characteristics are as illustrated in the figure, and the control input voltage must be changed significantly depending on the output frequency.
すなわち指定周波数を変更することによりこの位相制御
ループに大きい外乱を与えることになる。しかも、電圧
制御発振回路６の制御入力の回路には低域濾波器６が挿
入されるなど、この位相同期ループの制御時定数はかな
り大きく設定されているので、分周回路７が分周比を変
更しても、電圧制御発振回路６の入力制御電圧が変化す
るまでには、この制御時定数に相当する時間を要するこ
とになる。この制御時定数はループの制御特性を安定に
するために別の要因で定まるものであって、ある程度の
大きい制御時定数を設定することが必要であり、これを
単純に短く設定することはできない。したがって、指定
される通信周波数を頻繁にかつ高速に変更するような、
多数の加入者が少ないチャンネルを共用する移動無線通
信装置では、周波数の変更のために要する時間が長くな
って、スムーズな周波数制御が実行できなくなる欠点が
あった。In other words, by changing the designated frequency, a large disturbance is given to this phase control loop. Moreover, the control time constant of this phase-locked loop is set to be quite large, such as by inserting a low-pass filter 6 into the control input circuit of the voltage controlled oscillator circuit 6, so that the frequency dividing circuit 7 Even if the input control voltage of the voltage controlled oscillation circuit 6 changes, it will take a time corresponding to this control time constant. This control time constant is determined by another factor in order to stabilize the control characteristics of the loop, and it is necessary to set a relatively large control time constant; it cannot simply be set short. . Therefore, if the specified communication frequency is changed frequently and quickly,
A mobile radio communication device in which a large number of subscribers share a small number of channels has the disadvantage that it takes a long time to change the frequency, making it impossible to perform smooth frequency control.
本発明はこれを改良するもので、出力周波数の変更を高
速に行うことができる周波数シンセサイザ回路を提供す
ることを目的とする。The present invention improves this, and aims to provide a frequency synthesizer circuit that can change the output frequency at high speed.
本発明の回路は、位相同期ループとは別に、指定された
周波数に応じて電圧制御発振回路の制御電圧を固定的に
発生ずる制御電圧発生手段を設け、この手段の出力電圧
を位相同期ループの制御電圧に加算して電圧制御発振回
路の制御入力に与えるように構成されたことを特徴とす
る。The circuit of the present invention is provided with a control voltage generating means that fixedly generates a control voltage for the voltage controlled oscillation circuit according to a specified frequency, separately from the phase-locked loop, and the output voltage of this means is applied to the output voltage of the phase-locked loop. It is characterized in that it is configured to be added to the control voltage and applied to the control input of the voltage controlled oscillation circuit.
さらに具体的には、上記制御電圧発生手段は、指定され
た周波数に対応するアドレスの指定信号を発生するアド
レス制御回路と、このアドレス制御回路の出力をアドレ
ス入力とし、上記指定された周波数に対応するアドレス
に電圧制御発振回路のその周波数に対応する制御電圧の
近僚値がディジタル信号で記録された続出専用メモリと
、この続出専用メモリの出力ディジタル信号をアナログ
信号に変換するディジタル・アナログ変換回路（以下ｒ
ＤＡ変換回路」という。）とを含む構成とすることがで
きる。More specifically, the control voltage generating means includes an address control circuit that generates an address designation signal corresponding to a designated frequency, and an output of this address control circuit as an address input, which corresponds to the designated frequency. a digital-only memory in which the neighbor value of the control voltage corresponding to the frequency of the voltage-controlled oscillator circuit is recorded as a digital signal at the address to which the voltage-controlled oscillator circuit corresponds; and a digital-to-analog conversion circuit that converts the output digital signal of the sequential-only memory into an analog signal. (hereinafter r
DA conversion circuit. ).
第３図は本発明実施例回路のブロック構成図である。端
子１は周波数指定信号の入力端子であり、端子２は出力
信号端子である。水晶により制御された発振周波数の安
定な基準発振回路３の出力は位相比較回路４の一方の入
力に与えられ、その位相比較回路４の出力信号は低域濾
波器５を介して電圧制御発振回路６の制御入力に印加さ
れる。電圧制御発振回路６の出力は出力端子２に与えら
れるとともに分岐されて、分周回路７に導かれＮ分の１
に分周されて位相比較回路４の他方の入力に与えられる
。分周回路７の分周比は端子１に与えられる周波数指定
信号に応じて制御回路８により切替え制御される。FIG. 3 is a block diagram of a circuit according to an embodiment of the present invention. Terminal 1 is an input terminal for a frequency designation signal, and terminal 2 is an output signal terminal. The output of the reference oscillation circuit 3 with a stable oscillation frequency controlled by a crystal is given to one input of the phase comparison circuit 4, and the output signal of the phase comparison circuit 4 is passed through the low-pass filter 5 to the voltage controlled oscillation circuit. 6 control inputs. The output of the voltage controlled oscillator circuit 6 is given to the output terminal 2, branched off, and guided to the frequency dividing circuit 7, which divides the output into 1/N.
The frequency of the signal is divided into two and applied to the other input of the phase comparator circuit 4. The frequency dividing ratio of the frequency dividing circuit 7 is switched and controlled by the control circuit 8 according to a frequency designation signal applied to the terminal 1.
ここで本発明の特徴とするところは、低域濾波器５の出
力と電圧制御発振回路６の制御入力との間に電圧加算回
路９を設け、指定周波数に対応する電圧制御発振回路６
の制御電圧をループ制御電圧に加えて直接印加するよう
に構成されたところにある。このための回路は、周波数
指定信号の入力する端子ｌの信号によりアドレス指定信
号を発生するアドレス制御回路１０と、このアドレス制
御回路の出力をアドレス入力とする読出専用メモリ１１
と、この読出専用メモリ１】の出力信号をアナログ信号
に変換するＤＡ変換回路１２とを備え、このＤＡ変換回
路１２の出力アナログ信号を電圧制御発振回路６の制御
入力に加算するように構成される。Here, the feature of the present invention is that a voltage adder circuit 9 is provided between the output of the low-pass filter 5 and the control input of the voltage-controlled oscillation circuit 6, and the voltage-controlled oscillation circuit 6 corresponding to the designated frequency is provided.
is configured to directly apply a control voltage in addition to the loop control voltage. The circuit for this purpose includes an address control circuit 10 that generates an address designation signal based on a signal at a terminal l to which a frequency designation signal is input, and a read-only memory 11 that uses the output of this address control circuit as an address input.
and a DA conversion circuit 12 that converts the output signal of the read-only memory 1 into an analog signal, and is configured to add the output analog signal of the DA conversion circuit 12 to the control input of the voltage controlled oscillation circuit 6. Ru.
この続出専用メモ１月１には、入力端子ｌから指定され
た周波数に対応するアドレスに電圧制御発振回路のその
周波数に対応する制御電圧の近似値が、あらかじめディ
ジタル信号の制御電圧指定コードとして記録されている
。表はこの実施例装置の制御電圧と制御電圧指定コード
との対応を示す。On January 1st, this special memo is written in advance by recording an approximate value of the control voltage corresponding to the frequency of the voltage controlled oscillation circuit at the address corresponding to the frequency specified from the input terminal l as a control voltage specification code of the digital signal. has been done. The table shows the correspondence between the control voltages and control voltage designation codes of this embodiment device.
例えば、周波数１１を指定する制御電圧指定コードｌ；
ｌ：ｒｏ００１０１Ｊであ’ｌ、周波数ｆ ２ ’ｃｔ
ｒ１定する制御電圧指定コードはｒｏｏｌ、ｏｏｏＪで
ある。For example, control voltage designation code l that designates frequency 11;
l:ro00101J, frequency f2'ct
The control voltage designation codes for r1 are rool and oooJ.
このように構成された回路の動作を説明すると、いま入
力端子１に周波数指定入力が印加されると、制御回路８
は従来例回路と同様に分周回路７に対応する分周比を与
えるとともに、アドレス制御回路１０ばその周波数指定
入力に対応する続出専用メモリＩＩのアドレス信号を与
えて、制御電圧指定コードを読出専用メモリ１１から読
出す。この制御電圧指定コードはＤＡ変換回路１２で直
流電圧に変換されて、電圧加算回路９で電圧制御発振回
路６の制御電圧に加算される。これらの動作はすべてデ
ィジタル信号処理であり極めて短時間に実行することが
できる。したがって、電圧制御発振回路６はただちに指
定された周波数の出力信号を送出することになる。位相
同期ループはＤＡ変換回路Ｉ２から与えられる直流電圧
のわずかなずれを補償してループ制御を行うことになる
。電源電圧変動、温度変動その他の外乱による出力周波
数の変動は、このループ制御によりひきつづき補償され
て、出力周波数は基準発振回路３の出力周波数に基づい
て安定に制御される。すなわち本発明の回路では、位相
同期ループが補償する制御量は指定周波数が変更されて
も原則的に変化しない。したがって、本発明の回路では
、指定周波数の変更による制御ループ安定までの時間は
、従来例回路に比べて極めて短くなる。To explain the operation of the circuit configured in this way, when a frequency designation input is now applied to the input terminal 1, the control circuit 8
Similar to the conventional circuit, the circuit gives the frequency division ratio corresponding to the frequency divider circuit 7, and the address control circuit 10 gives the address signal of the successive memory II corresponding to the frequency designation input to read the control voltage designation code. Read from the dedicated memory 11. This control voltage designation code is converted into a DC voltage by the DA conversion circuit 12 and added to the control voltage of the voltage controlled oscillation circuit 6 by the voltage addition circuit 9. All of these operations are digital signal processing and can be executed in an extremely short time. Therefore, the voltage controlled oscillation circuit 6 immediately sends out an output signal of the specified frequency. The phase-locked loop performs loop control by compensating for slight deviations in the DC voltage applied from the DA conversion circuit I2. Fluctuations in the output frequency due to power supply voltage fluctuations, temperature fluctuations, and other disturbances are continuously compensated for by this loop control, and the output frequency is stably controlled based on the output frequency of the reference oscillation circuit 3. That is, in the circuit of the present invention, the control amount compensated by the phase-locked loop does not change in principle even if the designated frequency is changed. Therefore, in the circuit of the present invention, the time required for the control loop to stabilize due to a change in the specified frequency is extremely short compared to the conventional circuit.
以上説明したように、本発明の周波数シンセサイザ回路
は、従来の位相同期ループに加えて周波数変更に伴い制
御電圧を高速に発生する手段を設け、その発生した制御
電圧をを制御ループにフィードホワード結合する回路で
ある。したがって、上記実施例回路に説明の制御電圧発
生手段は、この構成によらなくともそのほかの構成によ
っても同様に実施することができる。As explained above, the frequency synthesizer circuit of the present invention is provided with a means for rapidly generating a control voltage as the frequency changes, in addition to the conventional phase-locked loop, and feed-forward coupling the generated control voltage to the control loop. This is a circuit that does this. Therefore, the control voltage generating means described in the above embodiment circuit can be similarly implemented not only by this configuration but also by other configurations.
以上説明したように、本発明によれば指定周波数の変更
に伴い、出力に新しい指定周波数が送出されるまでの時
間は、位相同期ループの制御時定数とは無関係に、極め
て短い時間に短縮された周波数シンセサイザ回路が得ら
れる。本発明の回路は、多数の加入者が少ない周波数チ
ャンネルを共用し、指定周波数の変更切替えを高速に行
う必要がある移動無線通信方式に実施すれば、交換接続
のための所要時間が短縮されて極めて大きい効果がある
。As explained above, according to the present invention, when the designated frequency is changed, the time until the new designated frequency is sent to the output is shortened to an extremely short time, regardless of the control time constant of the phase-locked loop. A frequency synthesizer circuit is obtained. If the circuit of the present invention is implemented in a mobile radio communication system in which a large number of subscribers share a small number of frequency channels and it is necessary to change designated frequencies at high speed, the time required for switching connection can be reduced. It has an extremely large effect.
第１図は従来例回路のブロック構成図。
第２図は電圧制御発振回路の特性図。
第３図は本発明実施例回路のブロック構成図。
１・・・指定周波数の信号が入力する端子、２・・・出
力周波数信号の端子、３・・・基準発振回路、４・・・
位相比較回路、５・・・濾波器、６・・・電圧制御発振
回路、７・・・分周回路、８・・・制御回路、９・・・
電圧加算回路、１０・・・アドレス指定回路、１１・・
・続出専用メモリ、１２・・・ディジタル・アナログ変
換回路（ＤＡ変換回路）。
特許出願人 日本電信電話公社
代理人弁理士 井 出 直 孝
第 １ Ｍ
尾 ２ 図
尾 ３図
第１頁の続き
＠発明者 中 １） 忠 明 横須賀市武１丁１通信研
究所内FIG. 1 is a block diagram of a conventional circuit. Figure 2 is a characteristic diagram of the voltage controlled oscillation circuit. FIG. 3 is a block diagram of a circuit according to an embodiment of the present invention. 1...Terminal to which a signal of a specified frequency is input, 2...Terminal of an output frequency signal, 3...Reference oscillation circuit, 4...
Phase comparison circuit, 5... Filter, 6... Voltage controlled oscillation circuit, 7... Frequency dividing circuit, 8... Control circuit, 9...
Voltage addition circuit, 10...Address designation circuit, 11...
・Memory for continuous use, 12...Digital-to-analog conversion circuit (DA conversion circuit). Patent Applicant Nippon Telegraph and Telephone Public Corporation Patent Attorney Nao Takashi Ide 1 M O 2 Fig O 3 Continuation of Figure 1, page 1 @ Inventor Naka 1) Tadaki Akira Telecommunications Research Institute, 1-1 Takeshi, Yokosuka City
Claims (1)
路と、 この位相比較回路の出力信号が通過する濾波器と、 この濾波器の出力信号を制御入力とする電圧制御発振回
路と、 この電圧制御発振回路の出力周波数を指定された周波数
に対応する分周比で分周して上記位相比較回路の他方の
入力に与える分周回路とを備えた位相同期形の周波数シ
ンセサイザ回路において、 上記指定された周波数に対応する上記電圧制御発振回路
の制御電圧の近似値を発生ずる制御電圧発生手段を備え
、 この手段の出力電圧を上記電圧制御発振回路の制御電圧
に加算するように構成されたことを特徴とする周波数ジ
ンセザイザ回路。 （２） 制御電圧発生手段は、 上記指定された周波数に対応するアドレスの指定信号を
発生するアドレス制御回路と、このアドレス制御回路の
出力をアト１／ス入力とし、上記指定された周波数に対
応するアドレスに上記電圧制御発振回路のその周波数に
対応する制御電圧の近似値がディジタル信号で記録され
た続出専用メモリと、 この続出専用メモリの出力ディジタル信号をアナログ信
号に変換するディジタル・アナログ変換回路と を含む特許請求の範囲第（１）項に記載の周波数シンセ
サイザ回路。[Claims] (11) A reference oscillation circuit, a phase comparison circuit whose one input is the output of this reference oscillation circuit, a filter through which the output signal of this phase comparison circuit passes, and an output signal of this filter. a voltage controlled oscillator circuit which takes as a control input, and a frequency divider circuit which divides the output frequency of this voltage controlled oscillator circuit by a frequency division ratio corresponding to a specified frequency and supplies it to the other input of the phase comparator circuit. A phase-locked frequency synthesizer circuit comprising a control voltage generating means for generating an approximate value of the control voltage of the voltage controlled oscillation circuit corresponding to the specified frequency, A frequency generator circuit characterized in that the frequency generator circuit is configured to be added to a control voltage of the circuit. (2) The control voltage generating means includes an address control circuit that generates an address designation signal corresponding to the designated frequency; The output of this address control circuit is used as the at1/s input, and an approximation value of the control voltage corresponding to the frequency of the voltage controlled oscillation circuit is recorded as a digital signal at the address corresponding to the specified frequency. The frequency synthesizer circuit according to claim 1, comprising: a digital-to-analog conversion circuit that converts the output digital signal of the continuous-only memory into an analog signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58157444A JPS6048618A (en) | 1983-08-29 | 1983-08-29 | Frequency synthesizer circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58157444A JPS6048618A (en) | 1983-08-29 | 1983-08-29 | Frequency synthesizer circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6048618A true JPS6048618A (en) | 1985-03-16 |
Family
ID=15649786
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58157444A Pending JPS6048618A (en) | 1983-08-29 | 1983-08-29 | Frequency synthesizer circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6048618A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62146020A (en) * | 1985-12-20 | 1987-06-30 | Yokogawa Medical Syst Ltd | Pll frequency synthesizer |
| JPS62181525A (en) * | 1986-02-05 | 1987-08-08 | Yokogawa Electric Corp | Signal generating circuit |
| EP0273031A1 (en) * | 1986-06-03 | 1988-07-06 | Information Resources Inc | Characterized fast tuning control for a television system. |
| JPS6432537A (en) * | 1987-07-28 | 1989-02-02 | Fujitsu Ten Ltd | Pll receiver |
| JPH01144726A (en) * | 1987-11-30 | 1989-06-07 | Japan Radio Co Ltd | Frequency synthesizer |
| JPH01105227U (en) * | 1987-12-29 | 1989-07-14 | ||
| EP0373750A2 (en) * | 1988-12-16 | 1990-06-20 | Tektronix Inc. | Phase-offset signal generator |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50155115A (en) * | 1974-06-03 | 1975-12-15 | ||
| JPS5536656B1 (en) * | 1970-03-25 | 1980-09-22 | ||
| JPS5843044B2 (en) * | 1980-12-16 | 1983-09-24 | 川辺農研産業株式会社 | How to grow long things |
-
1983
- 1983-08-29 JP JP58157444A patent/JPS6048618A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5536656B1 (en) * | 1970-03-25 | 1980-09-22 | ||
| JPS50155115A (en) * | 1974-06-03 | 1975-12-15 | ||
| JPS5843044B2 (en) * | 1980-12-16 | 1983-09-24 | 川辺農研産業株式会社 | How to grow long things |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62146020A (en) * | 1985-12-20 | 1987-06-30 | Yokogawa Medical Syst Ltd | Pll frequency synthesizer |
| JPS62181525A (en) * | 1986-02-05 | 1987-08-08 | Yokogawa Electric Corp | Signal generating circuit |
| EP0273031A1 (en) * | 1986-06-03 | 1988-07-06 | Information Resources Inc | Characterized fast tuning control for a television system. |
| JPS6432537A (en) * | 1987-07-28 | 1989-02-02 | Fujitsu Ten Ltd | Pll receiver |
| JPH01144726A (en) * | 1987-11-30 | 1989-06-07 | Japan Radio Co Ltd | Frequency synthesizer |
| JPH01105227U (en) * | 1987-12-29 | 1989-07-14 | ||
| EP0373750A2 (en) * | 1988-12-16 | 1990-06-20 | Tektronix Inc. | Phase-offset signal generator |
| EP0373750A3 (en) * | 1988-12-16 | 1991-05-29 | Tektronix Inc. | Phase-offset signal generator |
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