JPH04274617A - Pll circuit - Google Patents

Abstract

PURPOSE:To accurately control a frequency division value of a 2nd frequency divider being a component of the PLL circuit. CONSTITUTION:A frequency division value of a 2nd frequency divider 5 is fluctuated with staticelectricity or a voltage drop or the like. The PLL circuit 1 is unlocked by the fluctuation. Then an additional circuit 20 is provided to the PLL circuit 1 to solve the problem. A signal detector 21 of the additional circuit 20 detects the leading and trailing of a phase error signal outputted from a phase comparator 6 and a counter 22 is used to count the phase error signal from the start of its leading till the trailing is detected. A frequency division control circuit 23 compares the count of the counter 22 with a count reference value written in a memory 24 and when the count is larger, a frequency division value set to the said 2nd frequency divider 5 is controlled.

Description

[Detailed description of the invention]

[Purpose of the invention]

0001

[Industrial Application Field] The present invention relates to PLL (Phase
This relates to a locked loop (locked loop) circuit.

0002

2. Description of the Related Art Generally, a PLL circuit is used in electronic devices and the like as a circuit for synchronizing a predetermined phase and frequency. A conventional example of this PLL circuit will be explained with reference to FIGS. 4 to 6. In FIG. 4, 1 is a PLL circuit, 2 is an oscillator, and a reference signal is oscillated. 3 is PL
This PLLIC 3 is composed of a first frequency divider 4 to which a frequency division value R is set, a second frequency divider 5 to which a frequency division value N is set, and a phase comparator 6. ing. Note that the second frequency divider 5 is constituted by a programmable counter, and the frequency division value N can be changed as necessary.

When the reference signal is introduced into the first frequency divider 4, it is frequency-divided by a frequency division value R, and a first frequency-divided signal is output. Further, when an oscillation signal is introduced into the second frequency divider 5, the frequency is divided by a frequency division value N, and a second frequency division signal is output. When this second frequency-divided signal and the first frequency-divided signal are introduced into the phase comparator 6, the phases of both signals are compared and a phase error signal corresponding to the phase difference is output. The phase error signal becomes a DC control signal via the loop filter 7 and is introduced into the voltage controlled oscillator 8. In the voltage controlled oscillator 8, the frequency is adjusted so that the phase difference between the phase error signals outputted from the phase comparator 6 is eliminated, and the oscillation signal is oscillated. This oscillation signal is output to the next stage and is also introduced into the second frequency divider 5, where it is divided by a frequency division value N.

However, in the PLL circuit 1, the frequency division value N
may vary from the frequency division value N to N1 due to static electricity, voltage drop, etc., which has the disadvantage that the operation of the PLL circuit 1 becomes unstable. Therefore, an additional circuit 9 is added to prevent instability of operation caused by fluctuations in the frequency division value N. This additional circuit 9 will be explained below.

The phase error signal output from the phase comparator 6 is introduced into a loop filter 7 and also into a smoothing circuit 10. The phase error signal is smoothed in the smoothing circuit 10 and introduced into the comparator 11. Note that a reference value E0 is applied to the comparator 11 so that it can be determined whether the PLL circuit 1 is in an unlocked state. and,
The level of the reference value E0 is compared with the level of the output signal of the smoothing circuit 10, and if it is determined that the level of the output signal of the smoothing circuit 10 is high, the signal "
1”, and if it is determined to be smaller, the signal “
A binary signal of 0'' is output from the comparator 11. This binary signal is introduced into a frequency division value control circuit 12 that controls the value of the frequency division value N. The control circuit 12 stores a control signal for keeping the frequency division value of the second frequency divider 5 at N.

When the signal "1" is introduced into the frequency division value control circuit 12, assuming that the frequency division value N has changed to N1,
The control signal is output. Then, the frequency division value N1 of the second frequency divider 5 is changed to N by the control signal stored in the frequency division value control circuit 12. On the other hand, the signal “0”
is introduced into the frequency division value control circuit 12, the control signal is not output and the frequency division value is not changed.

Next, referring to FIGS. 5 and 6, the PLL
The locked and unlocked states of circuit 1 will be explained. FIG. 5 shows an example of an unlocked state, in which the frequency division value N fluctuates and becomes N1, so that the phase comparator 6
outputs a phase error signal with an increased phase difference. The phase error signal shown in FIG. 5(A) is smoothed as shown in FIG. 5(B) via the smoothing circuit 10 and introduced into the comparator 11. When the level of the output signal of the smoothing circuit 10 increases and exceeds the level of the reference value E0, the comparator 11 outputs a signal "1" as shown in FIG. 5(C).

In the frequency division value control circuit 12, the signal "1"
is introduced, the control signal is output to the second frequency divider 5. Then, according to this control signal, the frequency division value is N
1 to N, and the frequency of the oscillation signal is again divided by the frequency division value N.

Further, even when the oscillation signal oscillated from the voltage controlled oscillator 8 has some error, the unlocked state is reached as described above, and the phase error signal with an increased phase difference is output from the phase comparator 6. is output. In this case, the frequency division value N is controlled, and the voltage controlled oscillator 8 adjusts the frequency so that there is no phase difference, and eventually synchronizes and oscillates the oscillation signal in a stable state.

On the other hand, FIG. 6 shows an example of the locked state. The phase error signal shown in FIG. 6(A) is smoothed as shown in FIG. 6(B) via the smoothing circuit 10, and the comparator 1
1 will be introduced. Since the level of the output signal of the smoothing circuit 10 is lower than the level of the reference value E0, the comparator 11 outputs a signal "0" as shown in FIG. 6(C).

In the frequency division value control circuit 12, the signal "0"
is introduced, the control signal is not output, and the frequency division value of the second frequency divider 5 is not changed. Note that the frequency of the voltage controlled oscillator 8 was adjusted so that the same phase was maintained, and the oscillation signal was oscillated.

0012

[Problem to be Solved by the Invention] As mentioned above, the above PL
In the L circuit, the frequency division value of the second frequency divider fluctuates due to static electricity, voltage drop, etc., resulting in unstable operation. Therefore, an additional circuit is added to prevent instability of operation caused by this fluctuation, and the frequency division value of the second frequency divider is controlled.

However, the reference value applied to the comparator of the additional circuit may have errors due to temperature changes and the like. When an error occurs in the reference value in this way, the frequency division value control circuit has a problem in that it cannot accurately control the frequency division value.

[0014] Therefore, in the present invention, this problem is removed, and
A PL with an additional circuit that can accurately control the frequency division value without causing malfunction due to temperature changes, etc.
The purpose is to provide an L circuit. [Structure of the invention]

[
0015

[Means for Solving the Problems] The present invention provides an oscillator that oscillates a reference signal, and a first frequency divider that divides this reference signal by a first frequency division value and outputs a first frequency division signal. a voltage-controlled oscillator that adjusts the frequency of an oscillation signal and oscillates using a DC control signal; and a second divider that divides this oscillation signal by a second frequency division value and outputs a second frequency division signal. a frequency generator, a phase comparator that compares the phases of the second frequency-divided signal and the first frequency-divided signal, and outputs a phase error signal according to the phase difference; A loop filter that outputs the DC control signal to the voltage controlled oscillator, a signal detector that detects the rise and fall of the phase error signal, and a count from the rise to the fall of the phase error signal detected by this signal detector. a counter to which a predetermined count reference value is written; a frequency division value that compares the count reference value with the count value of the counter and controls the second frequency division value when the count value is large; This is a PLL circuit characterized by comprising a control means.

[0016]

According to the present invention, the reference signal oscillated from the oscillator is frequency-divided via the first frequency divider, and the first frequency-divided signal is output. On the other hand, the oscillation signal oscillated from the voltage controlled oscillator is frequency-divided via a second frequency divider, and a second frequency-divided signal is output. This second frequency divided signal and the first
The phases of the frequency-divided signals are compared through a phase comparator, and a phase error signal corresponding to the phase difference is output. The phase error signal becomes a DC control signal via a loop filter and is introduced into the voltage controlled oscillator.

Furthermore, the signal detector detects the rising and falling edges of the phase error signal. If a rising edge is detected, a signal indicating that it has been detected is output to the counter, and counting continues until a falling edge is detected. After counting with the counter, the frequency division value control means compares the reference value written in the memory with the count value, and when the count value is large, the frequency division value of the second frequency divider is changed. be done.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to FIGS. 1 to 3. Note that PLL circuits 1 and 2 in Figure 1
8 to 8 correspond to the PLL circuit configuration in FIG. 4,
The same reference numerals are used to omit the explanation.

In FIG. 1, 20 is an additional circuit added to the PLL circuit 1. In FIG. Reference numeral 21 denotes a signal detector included in the additional circuit 20, and each detection circuit for detecting the rising edge and falling edge of the phase error signal output from the phase comparator 6 is provided. When the signal detector 21 detects the rising edge of the phase error signal, this detection signal is sent to the counter 2.
2 will be introduced. The counter 22 continues counting from the rising edge of the phase error signal until the falling edge is detected. The count value obtained by the counter 22 is introduced into the frequency division value control circuit 23. Note that the frequency division value control circuit 23 stores in advance a control signal for holding the frequency division value of the second frequency divider 5 at N.

When the count value is introduced into the frequency division value control circuit 23, the count reference value written in the memory 24 is called out to the frequency division value control circuit 23. As an example, it is assumed that "3" is written as the count reference value. Then, the count reference value and the count value are compared by the frequency division value control circuit 23, and when the count value is large, the frequency division value of the second frequency divider 5 is changed.

Next, referring to FIGS. 2 and 3, the PLL
The locked and unlocked states of circuit 1 will be explained. FIG. 2 shows an example in the unlocked state, in which the frequency division value N set in the second frequency divider 5 fluctuates and becomes N1.
The phase comparator 6 outputs a phase error signal with an increased phase difference. The phase error signal shown in FIG. 2(A) is introduced into the signal detector 21. The signal detector 21 detects the rising and falling edges of the phase error signal, and furthermore, a signal indicating that the phase error signal has been detected is introduced into the counter 22. The counter 22 continues counting using the clock pulse shown in FIG. 2(B) starting from the rising edge of the phase error signal until the falling edge is detected. The count value counted by the counter 22 is
From FIG. 2, it is "4", for example, and the frequency division value control circuit 23
will be introduced in

When the count value is introduced, the frequency division value control circuit 23 reads the count reference value "3" written in the memory 24 and compares it with the count value "4". As a result of this comparison, it is determined that the count value is large, and the frequency division value control circuit 23 outputs the control signal to maintain the frequency division value N1 at N. When this control signal is introduced into the second frequency divider 5, which is a programmable counter, the frequency division value N1 is changed to N by the control signal.

Furthermore, even when the oscillation signal oscillated from the voltage controlled oscillator 8 has some error, the unlocked state is established as described above, and the phase comparator 6 outputs a phase error signal with an increased phase difference. be done. In such a case, the frequency division value N is controlled, and the voltage controlled oscillator 8 adjusts the frequency so that there is no phase difference, and eventually synchronizes and oscillates the oscillation signal in a stable state. Ru.

On the other hand, FIG. 3 shows an example of the locked state. The phase error signal shown in FIG. 3(A) is introduced into the signal detector 21. The signal detector 21 detects the rising and falling edges of the phase error signal, and furthermore, a signal indicating that the phase error signal has been detected is introduced into the counter 22. At the counter 22, FIG.
Using the clock pulse shown in (B), counting is continued from the rising edge of the phase error signal until the falling edge is detected. The count value counted by the counter 22 becomes, for example, "1" from FIG. 3, and is introduced into the frequency division value control circuit 23.

When the count reference value is introduced, the frequency division value control circuit 23 reads the count reference value "3" written in the memory 24 and compares it with the count value "1". As a result of this comparison, it is determined that the count value is small, and the frequency division value control circuit 23 does not output the control signal. Further, the voltage controlled oscillator 8 adjusts the frequency so that the same phase is maintained, and the oscillation signal is oscillated.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but can be practiced without changing the gist. For example, the additional circuit 20 includes a CPU (C
internalProcessing Unit).

[0027]

[Effects of the Invention] As explained above, in the present invention, the PLL
Additional circuits are added to the circuit. In this additional circuit,
The rising and falling edges of the phase error signal output from the phase comparator are detected by a signal detector, and a counter counts the detected phase error signal from rising edge to falling edge, and this count value is used to control the frequency division value. Output to the circuit. In addition, since the count reference value written in the memory does not change even when there is a temperature change, the frequency division value control circuit can accurately compare this count reference value with the count value. Comparisons can be made. Therefore, the frequency division value control circuit is
Without causing malfunction even when there is a temperature change,
The frequency division value of the second frequency divider can be controlled.

[Brief explanation of the drawing]

[Fig. 1] A PL with an additional circuit added in an embodiment of the present invention.
It is a block diagram of an L circuit.

FIG. 2 is a waveform diagram related to an embodiment of the present invention;
A) shows a phase error signal output from a phase comparator when the PLL circuit is in an unlocked state, and (B) shows a clock pulse for counting by a counter.

FIG. 3 is a waveform diagram related to an embodiment of the present invention;
A) shows a phase error signal output from a phase comparator when the PLL circuit is in a locked state, and (B) shows a clock pulse for counting by a counter.

FIG. 4 is a block diagram of a conventional example of a PLL circuit with an additional circuit added.

FIG. 5 is a waveform diagram related to a conventional example, in which (A) shows a phase error signal output from a phase comparator when the PLL circuit is in an unlocked state, and (B) shows an output signal of a smoothing circuit. and (C) shows the output signal of the comparator.

FIG. 6 is a waveform diagram related to a conventional example, in which (A) shows a phase error signal output from a phase comparator when the PLL circuit is in a locked state, and (B) shows an output signal of a smoothing circuit. , (C) show the output signal of the comparator.

[Explanation of symbols]

1... PLL circuit, 2... Oscillator, 4... First frequency divider, 5...
2nd frequency divider, 6...phase comparator, 7...loop filter,
8... Voltage controlled oscillator, 21... Signal detector, 22... Counter, 23... Frequency division value control circuit, 24... Memory.

Claims (1)

[Claims] Claim 1: An oscillator that oscillates a reference signal, a first frequency divider that divides this reference signal by a first frequency division value and outputs a first frequency division signal, and a DC control signal, a voltage controlled oscillator that adjusts the frequency of an oscillation signal and oscillates; a second frequency divider that divides this oscillation signal by a second frequency division value and outputs a second frequency division signal; a phase comparator that compares the phases of the frequency-divided signal and the first frequency-divided signal and outputs a phase error signal according to the phase difference; a loop filter that outputs a signal, a signal detector that detects rising and falling edges of the phase error signal, a counter that counts from the rising edge to the falling edge of the phase error signal detected by the signal detector, and a predetermined counting standard. comprising a memory in which a value is written, and frequency division value control means that compares the count reference value with the count value of the counter and controls the second frequency division value when the count value is large. A PLL circuit featuring: