KR20020046482A - A charge pump type analogue phase locked loop - Google Patents

Abstract

PURPOSE: A charge pump-type analog PLL(Phase Locked Loop) is provided to prevent a failed operation by stably supplying an output clock signal to PLL in spite of noises. CONSTITUTION: A charge pump-type analog PLL comprises a phase frequency detecting part(20), a charge pump(21), a loop filter(22) and a VCO(Voltage Controlled Oscillator)(23). The charge pump-type analog PLL additionally comprises a phase locking detector(24) for detecting whether a phase and a frequency of a reference clock signal(ref_clk) and output clock signal(Fout) are fixed or not by responding a fail signal(Up,Down) supplied from the phase frequency detecting part(20), a voltage level detector(25) for detecting an output voltage of the loop filter(22), a register(26) connected with the voltage level detector(25) for storing the detected output voltage level of the loop filter(22), and a voltage level generator(27) for generating a defined level voltage by responding a phase locking detecting signal(lockedb).

Description

Charge pump type analog phase locked loop

TECHNICAL FIELD The present invention relates to electronic circuit technology, and more particularly, to a charge pump type analog phase locked loop (PLL).

The phase lock loop is a circuit for fixing a signal input from the outside to a desired frequency, and is widely used in a semiconductor device requiring high speed synchronous operation. Most analog PLLs use a charge pump type.

1 is a block diagram of a charge pump type analog phase locked loop according to the related art, which will be described below with reference to the drawings.

The phase-locked loop according to the prior art detects the phase difference between the reference clock signal ref_clk and the feedback output clock signal Fout input from the outside as shown in the figure, and outputs an error signal; A charge pump 11 for charging / discharging the capacitor of the loop filter 12 according to the error signal output from the phase frequency detector 10 and a charge pump 11 as a low pass filter (LPF) The loop filter 30 for controlling the bias voltage of the voltage controlled oscillator 13 for removing the high frequency component of the output signal of the output signal and the frequency of the output clock signal Fout proportional to the output voltage of the loop filter 12. It consists of a voltage controlled oscillator (VCO) 13 for oscillating with Here, the phase frequency detector 10 outputs a down signal when the phase of the feedback frequency Fout is faster than the phase of the reference frequency ref_clk or slows up.

The conventional phase locked loop as described above determines the frequency of the output clock signal Fout in the voltage controlled oscillator 13 in proportion to the input voltage of the voltage controlled generator 13, that is, the output voltage of the loop filter 12. . To this end, the phase frequency 10 and the charge pump 11 compare the phase and the frequency of the reference clock signal ref_clk and the feedbacked output clock signal Fout, and according to the comparison result, input voltage of the voltage controlled oscillator 13. When the frequency of the output clock signal Fout is fixed after adjusting the voltage, the input voltage of the voltage controlled oscillator 13 is kept constant.

However, due to noise generated on the board outside the chip, the phase and frequency of the output clock signal Fout fluctuate for several cycles until the phase is fixed again with respect to the reference clock signal ref_clk.

As a result, the conventional PLL outputs an output clock signal that is changed according to the shaking of the reference clock signal ref_clk due to noise after the phase is fixed, which may cause chip malfunction due to an incorrect output clock signal Fout. Several cycles of time are required to generate an output clock signal that is phase-locked again to the changed reference clock signal ref_clk.

The present invention has been proposed to solve the above problems of the prior art, to provide a charge pump type analog phase locked loop that can supply a stable clock to minimize the effects of noise generated on the board outside the chip. There is this.

1 is a block diagram of a charge pump type analog phase locked loop according to the prior art.

Figure 2 is a block diagram of a charge pump type analog phase locked loop according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

20: phase frequency detector 21: charge pump

22 loop filter 23 voltage controlled oscillator

24: phase locked detector 25: voltage level detector

26: register 27: voltage level generator

In accordance with another aspect of the present invention, a charge pump type analog phase locked loop includes: phase frequency detection means for detecting a phase and frequency difference between a reference clock signal applied from an external source and a feedback output clock signal; Charge pumping means for performing a charge / discharge operation in response to an error signal and a bias signal output from said phase frequency detecting means; Loop filtering means for removing high frequency components from an output signal of the charge pumping means; Phase lock detection means for detecting whether phase lock has been performed in response to the error signal; Voltage level detection means for detecting a voltage level at an output of the loop filtering means; Voltage level storage means for storing the voltage level of the output terminal of the loop filtering means detected by the voltage level detecting means; Voltage level generating means for driving the output terminal of the loop filtering means to a predetermined voltage level corresponding to the voltage level stored in the voltage level storing means in response to the phase fixed detecting signal output from the phase fixing detecting means; And voltage controlled oscillation means for oscillating the output clock signal at a frequency proportional to the voltage level of the output stage of the loop filtering means.

Preferably, while the phase lock detection signal is active, the charge pumping means is disabled by the bias signal, and the voltage level generating means is enabled by the phase lock detection signal.

Preferably, a register controlled by the phase-locked detection signal is used as the voltage level storing means.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

2 is a block diagram illustrating a charge pump type analog phase locked loop according to an exemplary embodiment of the present invention.

The phase-locked loop according to the present embodiment includes a phase frequency detector 20, a charge pump 21, a loop filter 22, and a voltage controlled oscillator 23, and outputs an error signal (outputted from the phase frequency detector 20). In response to Up and Down, the output voltage levels of the phase lock detector 24 and the loop filter 22 for detecting whether the phase and the frequency of the reference clock signal ref_clk and the output clock signal Fout are fixed. A voltage level detector 25 for detecting, a register 26 for storing the output voltage level of the detected loop filter 22 connected to the voltage level detector 25, and responding to a phase-locked detection signal lockedb. And a voltage level generator 27 for generating a voltage of a predetermined level.

Here, the error signals Up and Down output from the phase frequency detector 200 are high active signals and fall to low at the moment of phase fixation. The output stage LFO of the loop filter 22 is driven by the charge pump 21 or the voltage level generator 27.

The operation of the phase locked loop of the present embodiment as described above will be described below.

First, the phase voltage detector 20 compares the phase and frequency of the reference clock signal ref_clk and the output clock signal Fout to determine the error signals Up and Down and the bias voltage of the charge pump 21. output (bias) At this time, the phase frequency detector 20 outputs error signals Up and Down of levels opposite to each other until the phase is fixed.

Thereafter, the charge pump 21 performs a charge / discharge operation according to the error signals Up and Down and the output voltage bias, and the high frequency component of the signal output from the charge pump 21 in the loop filter 22 is obtained. Remove

On the other hand, the phase locked detector 24 is a high level phase locked detection signal (lockedb) indicating that phase locking is not performed in response to error signals Up and Dwon having opposite levels output from the phase frequency detector 20. ), The voltage level detector 25 detects the output voltage level of the loop filter 22 and stores the voltage level value in the register 26. In addition, the voltage level generator 27 is in a state in which the output stage LFO of the loop filter 22 cannot be driven, that is, disabled when the high level phase locked detection signal lockedb is applied.

The voltage controlled oscillator 23 generates an output clock signal Fout having a frequency proportional to the output voltage of the loop filter 220.

Subsequently, when the reference clock signal ref_clk and the output clock signal Fout are fixed in phase by repeatedly performing the above operation, the phase frequency detector 20 outputs low level error signals Up and Down. The phase locked detector 24 outputs a low level locked phase locked signal (lockedb) to indicate that phase locked has been performed. The output stage LFO of the loop filter 22 is no longer driven by the charge pump 21. Will not be.

On the other hand, the output voltage level of the loop filter 22 at the time of phase lock stored in the register 26 is transferred to the voltage level generator 27 in response to the output low level phase lock detection signal lockedb. The level generator 27 is enabled by the phase locked detection signal lockedb to drive the output stage LFO of the loop filter 22 at the voltage level generated using the voltage input from the register 26. That is, after the phase fixing is performed, the output voltage of the voltage level generator 27 is input to the voltage controlled oscillator 23, whereby the voltage controlled oscillator 23 is a constant frequency proportional to the voltage level stored in the register 26. Generates an output clock signal Fout.

Therefore, once the phase lock is performed, the output voltage of the loop filter 22 is not applied to the input voltage of the voltage controlled oscillator 23, but instead of the loop filter 22 at the phase lock stored in the register 26. The output voltage level is always applied as the input voltage of the voltage controlled oscillator 23. Therefore, even when the reference clock signal ref_clk is shaken due to the noise after the phase fixing is performed and the output voltage of the loop filter 22 is changed, the voltage level stored in the register 26 is changed to the input voltage of the voltage controlled oscillator 23. The output clock signal Fout at the time of phase fixing can be stably supplied.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The present invention made as described above has an effect of stably supplying the output clock signal at the time of phase fixation even when the reference clock signal is shaken due to the noise generated on the board outside the chip generated after the phase fixation. The effect of preventing the malfunction can be expected.

Claims (3)

Phase frequency detecting means for detecting a phase and frequency difference between the reference clock signal applied from the outside and the output clock signal fed back; Charge pumping means for performing a charge / discharge operation in response to an error signal and a bias signal output from said phase frequency detecting means; Loop filtering means for removing high frequency components from an output signal of the charge pumping means; Phase lock detection means for detecting whether phase lock has been performed in response to the error signal; Voltage level detection means for detecting a voltage level at an output of the loop filtering means; Voltage level storage means for storing the voltage level of the output terminal of the loop filtering means detected by the voltage level detecting means; Voltage level generating means for driving the output terminal of the loop filtering means to a predetermined voltage level corresponding to the voltage level stored in the voltage level storing means in response to the phase fixed detecting signal output from the phase fixing detecting means; And Voltage controlled oscillation means for oscillating the output clock signal at a frequency proportional to the voltage level of the output stage of the loop filtering means Charge pump type analog phase locked loop having a. The method of claim 1, The charge pumping means is disabled by the bias signal while the phase fixing detection signal is active, and the voltage level generating means is enabled by the phase fixing detection signal. Fixed loop. The method according to claim 1 or 2, The voltage level storing means, A charge pump type analog phase locked loop, characterized in that the register is controlled by the phase fixed detection signal.