KR101413917B1 - Phase locked loop - Google Patents

Abstract

A phase locked loop according to the present invention comprises a phase frequency detector which compares a phase of a feedback signal divided from an output signal with that of a reference signal and generates a comparison result signal according to a result of the comparison; a charge pump which provides a current corresponding to the comparison result signal; a loop filter which provides a charging/discharging voltage corresponding to the current of the charge pump; a loop band control unit which receives the charging/discharging voltage from the loop filter, receives the comparison result signal from the phase frequency detector to detect a phase locked state, and supplies a control voltage and a control signal according to a result of the detection; a voltage controlled oscillator which includes a first input end receiving the control voltage and a second input end receiving the control signal from the loop band control unit and provides the output signal by adjusting a gain in response to the control signal; and a divider which generates the feedback signal by dividing the output signal and provides the feedback signal to the phase frequency detector.

Description

PHASE LOCKED LOOP}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop, and more particularly, to a phase locked loop operating as a fine loop after selecting a band in an analog band selected loop.

A phase locked loop (PLL) is a circuit that continuously compares the phases of a reference signal and an output signal, and corrects the frequency based on the result, thereby maintaining the output signal at a constant frequency at all times. It is one of the basic circuits commonly found in electronic systems. The phase locked loop is composed of a phase frequency detector (PFD), a charge pump (CP), a loop filter (LP), a voltage controlled oscillator (VCO) and a divider ).

1 is a block diagram illustrating a phase locked loop including a secondary loop filter in accordance with the prior art.

The phase frequency detector 10 compares the phase of the feedback signal F _{DIV obtained} by dividing the output signal Fvco of the voltage controlled oscillator 40 through the frequency divider 50 with the phase of the reference signal F _REF , When the comparison result signals UP and DN are generated, the charge pump 20 provides a current corresponding to the comparison result signals UP and DN to the second loop filter 30. The second loop filter 30 provided with the current of the charge pump 20 first charges the second capacitor Cp according to the RC delay to increase the charge / discharge voltage V _LPF during the activation period of the comparison result signal Down). The second loop filter 30 is provided with a resistor Rz and a first capacitor Cz to which a current charged in the second capacitor Cp is connected in series during the inactivation period of the comparison result signals UP and DN (Or raises) the charging / discharging voltage (V _LPF ). The voltage-controlled oscillator 40 provides the output signal Fvco based on the charge / discharge voltage V _LPF provided in the second-order loop filter 30.

Although the phase locked loop is designed to have a wide band characteristic by increasing the gain of the voltage controlled oscillator in order to increase the phase fixing time, the voltage controlled oscillator having a large gain has a problem that the noise characteristic of the phase locked loop is deteriorated. In addition, the phase locked loop is designed to have a narrow band characteristic by reducing the gain of the voltage controlled oscillator to improve the noise characteristic, but the voltage controlled oscillator having a small gain has a problem that the phase fixing time of the phase locked loop is lengthened .

Therefore, the conventional phase locked loop has a limitation in having good noise characteristics at the same time with a fast phase fixing time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems of the prior art. That is, a phase locked loop having a fast phase fixing time and a good noise characteristic is provided.

The phase locked loop according to the present invention includes a phase frequency detector for comparing phases of a reference signal and a feedback signal obtained by dividing an output signal and generating a comparison result signal according to a result of the comparison, A loop filter for providing a charging and discharging voltage corresponding to the current of the charge pump, a phase filter for receiving the charge and discharge voltage from the loop filter, receiving a comparison result signal from the phase frequency detector, A loop bandwidth control unit for providing a control voltage and a control signal in accordance with the detection result, a first input terminal receiving the control voltage from the loop bandwidth control unit, and a second input terminal receiving the control signal, A voltage-controlled oscillator for adjusting the gain to provide an output signal; and a voltage-controlled oscillator for frequency- Sex and includes a frequency divider to provide the feedback signal to the phase frequency detector.

In one embodiment, when the phase-locked state is not detected as a result of detection of the phase-locked state, the control voltage is fixed by a bias power source, and the control signal is generated corresponding to the charge / discharge voltage of the loop filter Performing an operation of matching the charging / discharging voltage of the loop filter with the control voltage fixed to the bias power source through the bias power supply when the phase locking is detected as a result of detection of the phase locking state, And connects the charge / discharge voltage of the loop filter to the control voltage.

In one embodiment, the loop bandwidth control unit includes a switching signal generation unit that receives the comparison result signal and detects a phase locked state, and provides a switching signal according to a detection result, and a switching signal generation unit that receives the charging / And a loop band selection unit for providing the control voltage and the control signal in accordance with the switching signal provided from the unit.

In one embodiment, the switching signal generation unit includes a phase locked state indicator that receives the comparison result signal to detect a phase locked state, and provides a detection result signal according to a detection result, and a detection result signal from the phase locked state indicator And a calculator for providing the first, second, and third switching signals, which are the switching signals, to the loop band selection unit through an operation to be provided.

In one embodiment, the operator includes a first AND gate, a second AND gate, a first inverter, a second inverter, and a buffer, wherein the first switching signal is the detection result signal, Wherein the detection result signal and the detection result signal are inverted through the first inverter to a first AND gate, and the third switching signal is a signal for delaying the detection result signal through the buffer, And the second AND gate receives the inverted signal of the second switching signal through the second inverter and outputs the calculated signal.

In one embodiment, the loop band selection unit comprises a first switch connected between the bias power supply and the output of the loop filter, the first switch being switched in correspondence with the second switching signal, the first switch being switched in response to the first switching signal, A third switch connected between the output of the loop filter and a first input of the voltage controlled oscillator and being switched in response to the third switching signal, A fourth switch connected between the first input terminal of the voltage controlled oscillator and switched in accordance with the third switching signal and a second switch connected to the other end of the second switch and the second input terminal of the voltage controlled oscillator, Comparing a reference voltage with an input voltage at which a discharge voltage is generated in response to the switching of the second switch, and providing the control signal according to a comparison result Day includes a log band selector.

In one embodiment, the analog band selector includes a plurality of resistors connected in series to a reference voltage source to provide first to eighth reference voltages, respectively, the first to eighth reference voltages, the first to eighth reference voltages, A plurality of comparators connected to the outputs of the plurality of comparators and providing the respective comparison values corresponding to the first switching signal and a plurality of comparators respectively connected to the outputs of the plurality of comparators, And a plurality of latches respectively connected to the outputs of the plurality of fifth switches and storing or providing the respective comparison values to provide the first to eighth control signals as the control signals.

In one embodiment, the voltage controlled oscillator includes a plurality of PMOS transistors that are respectively provided with the first to eighth control signals provided from the analog band selector.

The phase locked loop according to the present invention includes a phase frequency detector for comparing phases of a reference signal and a feedback signal obtained by dividing an output signal and generating a comparison result signal according to a result of the comparison, A loop filter for providing a charging and discharging voltage corresponding to the current of the charge pump, a phase filter for receiving the charge and discharge voltage from the loop filter, receiving a comparison result signal from the phase frequency detector, A first input terminal receiving the control voltage from the loop band control unit, a second input terminal receiving the control signal, and a third input terminal receiving the feedback voltage, A voltage controlled oscillator that adjusts the gain to provide an output signal in accordance with the control signal, A frequency-to-voltage converter that generates the feedback voltage corresponding to the output signal provided from the oscillator and feeds the feedback voltage to the voltage-controlled oscillator to remove noise of the voltage-controlled oscillator, And providing a feedback signal to the phase frequency detector.

In one embodiment, when the phase-locked state is not detected as a result of detection of the phase-locked state, the control voltage is fixed by a bias power source, and the control signal is generated corresponding to the charge / discharge voltage of the loop filter Performing an operation of matching the charging / discharging voltage of the loop filter with the control voltage fixed to the bias power source through the bias power supply when the phase locking is detected as a result of detection of the phase locking state, And connects the charge / discharge voltage of the loop filter to the control voltage.

In one embodiment, the loop bandwidth control unit includes a switching signal generation unit that receives the comparison result signal and detects a phase locked state, and provides a switching signal according to a detection result, and a switching signal generation unit that receives the charging / And a loop band selection unit for providing the control voltage and the control signal in accordance with the switching signal provided from the unit.

In one embodiment, the switching signal generation unit includes a phase locked state indicator that receives the comparison result signal to detect a phase locked state, and provides a detection result signal according to a detection result, and a detection result signal from the phase locked state indicator And a calculator for providing the first, second, and third switching signals, which are the switching signals, to the loop band selection unit through an operation to be provided.

In one embodiment, the operator includes a first AND gate, a second AND gate, a first inverter, a second inverter, and a buffer, wherein the first switching signal is the detection result signal, Wherein the detection result signal and the detection result signal are inverted through the first inverter to a first AND gate, and the third switching signal is a signal for delaying the detection result signal through the buffer, And the second AND gate receives the inverted signal of the second switching signal through the second inverter and outputs the calculated signal.

In one embodiment, the loop band selection unit comprises a first switch connected between the bias power supply and the output of the loop filter, the first switch being switched in correspondence with the second switching signal, the first switch being switched in response to the first switching signal, A third switch connected between the output of the loop filter and a first input of the voltage controlled oscillator and being switched in response to the third switching signal, A fourth switch connected between the first input terminal of the voltage controlled oscillator and switched in accordance with the third switching signal and a second switch connected to the other end of the second switch and the second input terminal of the voltage controlled oscillator, Comparing a reference voltage with an input voltage at which a discharge voltage is generated in response to the switching of the second switch, and providing the control signal according to a comparison result Day includes a log band selector.

In one embodiment, the analog band selector includes a plurality of resistors connected in series to a reference voltage source to provide first to eighth reference voltages, respectively, the first to eighth reference voltages, the first to eighth reference voltages, A plurality of comparators connected to the outputs of the plurality of comparators and providing the respective comparison values corresponding to the first switching signal and a plurality of comparators respectively connected to the outputs of the plurality of comparators, And a plurality of latches respectively connected to the outputs of the plurality of fifth switches and storing or providing the respective comparison values to provide the first to eighth control signals as the control signals.

In one embodiment, the voltage controlled oscillator includes a plurality of PMOS transistors that are respectively provided with the first to eighth control signals provided from the analog band selector.

According to an embodiment of the present invention, when the phase locked loop detects that the phase locked state is not established, the gain of the voltage controlled oscillator is increased to have a wide band characteristic, Is provided. According to an embodiment of the present invention, when the phase locked loop is phase locked as a result of detection of the phase locked state, the gain of the voltage controlled oscillator is reduced to have a narrow band characteristic, And the spur can be further suppressed. Also, according to the embodiment of the present invention, the phase locked loop provides a fast phase locking time and a good catching characteristic at the same time. In addition, according to an embodiment of the present invention, the phase locked loop constitutes another sub feedback loop composed of a frequency-voltage converter and a voltage controlled oscillator, thereby providing an effect that the phase locked loop can operate more stably . In addition, according to an embodiment of the present invention, a phase-locked loop provides an effect of further removing noise by using a frequency-to-voltage converter that operates even in a fine loop.

However, the effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned can be clearly understood by those skilled in the art from the following description.

1 is a block diagram illustrating a phase locked loop including a secondary loop filter in accordance with the prior art.
2 is a block diagram illustrating the overall structure of a phase locked loop according to an embodiment of the present invention.
FIG. 3 is a block diagram showing (a) a switching signal generating unit according to an embodiment of the present invention, and (b) a switching signal generating unit for explaining the operation of the switching signals generated in the switching signal generating unit of FIG. Timing diagram.
4 is a block diagram illustrating an analog band selector in accordance with an embodiment of the present invention.
5 is a graph showing a correlation between a control voltage and an output signal of a phase locked loop according to an embodiment of the present invention.
6 is a circuit diagram showing a voltage-controlled oscillator of a ring structure according to an embodiment of the present invention.
FIG. 7 is a circuit diagram showing a detailed structure of a frequency-voltage converter according to an embodiment of the present invention, and FIG. 7B is a circuit diagram showing a control signal generator for generating a control signal provided to the frequency-to- c is a timing chart for explaining the operation of the control signals generated by the control signal generator of FIG. 7 (b).
8 is a conceptual diagram illustrating a phase locked loop according to an embodiment of the present invention.
9 is a linear model illustrating a phase locked loop according to an embodiment of the present invention.
10 shows a board diagram of an open loop transfer function when operating in an analog band selection loop depending on whether a frequency-to-voltage converter is used or not.
11 shows a board diagram of an open loop transfer function when operating as a fine loop depending on whether a frequency-voltage converter is used or not.
12 is a linear model illustrating all internal noise sources of a phase locked loop according to an embodiment of the present invention.
13 is a graph comparing noise analysis of (a) a general phase locked loop using a second loop filter and (b) a phase locked loop including a frequency-to-voltage converter according to an embodiment of the present invention.
FIG. 14 is a graph showing the output change when the phase locked loop according to an embodiment of the present invention operates as an analog band selection loop. FIG.
15 is a graph showing a change in charge / discharge voltage of a loop filter when a phase locked loop according to an embodiment of the present invention operates as an analog band selection loop.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Hereinafter, a phase locked loop according to an embodiment of the present invention will be described with reference to the accompanying drawings.

First Embodiment

2 is a block diagram illustrating the overall structure of a phase locked loop according to an embodiment of the present invention.

Referring to FIG. 2, a phase locked loop according to an embodiment of the present invention includes a phase frequency detector 100, a charge pump 200, a loop filter 300, a loop band controller 400, a voltage controlled oscillator 500, And a frequency divider (600).

The phase frequency detector (PFD: Phase Frequency Detector) (100) the reference signal (F _REF), and being provided a feedback signal (F _DIV) provided by the frequency divider 600 to be described later, provided reference signal (F _REF), and The phase of the feedback signal F _DIV is compared and the comparison result signals UP and DN are generated according to the comparison result. That is, the phase frequency detector 100 detects whether the phase of the reference signal F _REF is higher than the phase of the feedback signal F _DIV by a lead or a lag, (DN). In one example, the phase frequency detector 100 is a comparison result signal corresponding to the phase difference of the two signals when the phase of the reference signal F _REF is faster than the phase of the feedback signal F _DIV , Up signal UP. In another example, the phase frequency detector 100 determines whether the phase of the reference signal F _REF is slower than the phase of the feedback signal F _DIV , i.e., in the case of a lag, To generate a down signal (DN).

A charge pump (CP) 200 receives the comparison result signals UP and DN generated from the phase frequency detector 100 and outputs a current corresponding to the comparison result signals UP and DN to a loop To the filter (300).

A loop filter (LP) 300 is connected to the output of the charge pump 200. The loop filter 300 is supplied with current from the charge pump 200 and provides a charge / discharge voltage V _LPF corresponding to the current of the provided charge pump 200. In addition, the loop filter 300 may include a resistor Rz, a first capacitor Cz, and a second capacitor Cp. The resistor Rz and the first capacitor Cz are connected in series and the second capacitor Cp is connected in parallel with the resistor Rz and the first capacitor Cz.

The loop bandwidth control unit 400 is connected to the output of the loop filter 300 and the output of the phase frequency detector 100 to receive the charge and discharge voltage V _LPF from the loop filter 300, And receives the comparison result signals UP and DN. The loop bandwidth control unit 400 receives the comparison result signals UP and DN from the phase frequency detector 100 to detect the phase locked state and generates the control voltage Vcon and the control signal F _Eff in accordance with the detection result do.

That is, the loop bandwidth controller 400 in case of interruption of the detection result of the phase-locked in a phase-locked state control voltage (Vcon) is fixed by a bias power supply (Vbias2), control signals (F _Eff) is charged in the loop filter 300 And performs an operation corresponding to the discharge voltage (V _LPF ). Hereinafter, this operation is referred to as an analog band selection loop (loop2).

The loop bandwidth control unit 400 controls the charging / discharging voltage V _LPF of the loop filter 300 via the bias power supply Vbias1 when the phase locking is detected as a result of detection of the phase locked state by a control fixed to the bias power supply Vbias2 And performs an operation to match the voltage Vcon.

Further, the loop bandwidth control unit 400 connects the matched charge / discharge voltage V _LPF and the control voltage Vcon when the phase is fixed as a result of detection of the phase locked state. Hereinafter, such operation is referred to as a fine loop loop1.

The control voltage Vcon of the loop bandwidth control unit 400 is provided to the first input terminal K _LPF of the voltage controlled oscillator 500 and the control signal F _Eff of the loop bandwidth control unit 400 is supplied to the voltage controlled oscillator 500. [ _Lt ; / RTI > is provided at a second input (K _Eff )

As described above, the phase locked loop according to an embodiment of the present invention selects the analog band selection loop and the fine loop according to the phase locked state, and thereby, the phase of the closed loop structure in which the dual loop structure operates in a single loop according to the phase locked state It is a fixed loop. That is, the phase locked loop according to an embodiment of the present invention operates as an analog band selection loop to select a band, and then operates as a fine loop.

In addition, the loop bandwidth control unit 400 may include a switching signal generation unit 410 and a loop bandwidth selection unit 420.

The switching signal generation unit 410 is connected to the phase frequency detector 100. The switching signal generation unit 410 receives the comparison result signals UP and DN from the phase frequency detector 100 to detect the phase locked state, generates a switching signal according to the detection result, And provides it to the selection unit 420.

FIG. 3 is a block diagram showing (a) a switching signal generating unit according to an embodiment of the present invention, and (b) a switching signal generating unit for explaining the operation of the switching signals generated in the switching signal generating unit of FIG. Timing diagram.

Referring to FIG. 3, the switching signal generating unit 410 may include a LSI (Locking Status Indicator) 412 and a calculator 414.

The phase locked state indicator 412 receives the comparison result signals UP and DN from the phase frequency detector 100 to detect the phase locked state and provides a detection result signal in accordance with the detected result. Specifically, the phase locked state indicator 412 provides a low signal "0 ", which is a detection result signal, to the calculator 414 when phase locking is not detected as a result of detection of the phase locked state. In addition, the phase locked state indicator 412 provides a high signal "1 ", which is the detection result signal, to the calculator 414 when it is close to the phase fixing result of detection of the phase locked state.

The calculator 414 is connected to the phase locked status indicator 412. The calculator 414 receives the detection result signal from the phase locked state indicator 412 and outputs the first, second and third switching signals signal1, 2 and 3, which are switching signals, to the loop band selection unit 420, .

The computing unit 414 includes a first AND gate AND1, a second AND gate AND2, a first inverter INV1, a second inverter INV2, and a buffer BUF, Second, and third switching signals (signal1, 2, 3). That is, the first switching signal signal1 of the calculator 414 may be a detection result signal of the phase locked state indicator 412. [ The second switching signal signal2 of the computing unit 414 is a signal for receiving the detection result signal and the detection result signal inverted through the first inverter INV1 by the first AND gate AND1, . The third switching signal signal3 of the computing unit 414 is a signal obtained by delaying the detection result signal delayed through the buffer BUF and the signal obtained by inverting the second switching signal signal2 through the second inverter INV2, And the AND gate AND2 may receive the input signal and output it. The operation of the first, second and third switching signals signal1, 2, and 3 generated in the switching signal generating unit 410 according to the phase locked state is as shown in FIG. 3 (b).

2, the loop band selection unit 420 is supplied with the charge / discharge voltage V _LPF from the loop filter 300. [ The loop band selection unit 420 receives the switching signal from the switching signal generation unit 410 and outputs the control voltage Vcon and the control signal F _Eff to the voltage controlled oscillator 500 in accordance with the supplied switching signal to provide. In particular, the control voltage Vcon of the loop-band selection unit 420 is provided to the first input (K _LPF ) of the voltage-controlled oscillator 500. The control signal F _Eff of the loop band selection unit 420 is also provided as a second input (K _Eff ) of the voltage controlled oscillator 500.

The loop band selection unit 420 may also include a first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4 and an analog band selector 422. The first switch SW1 is connected between the bias power supply Vbias1 and the output of the loop filter 300 and can be switched in response to the second switching signal signal2 provided from the switching signal generating unit 410. [ The other end of the second switch SW2 is connected to the output of the loop filter 300 and the other end of the second switch SW2 is connected to the analog band selector 422. The first switch SW2 is provided with a first switching signal signal1 ). ≪ / RTI > The third switch SW3 is connected between the output of the loop filter 300 and the first input terminal (K _LPF ) of the voltage-controlled oscillator 500, and the third switching signal (signal3). < / RTI > The fourth switch SW4 is connected between the bias power supply Vbias2 and the first input terminal K _LPF of the voltage controlled oscillator 500 and receives the third switching signal signal3 ). ≪ / RTI > The analog band selector 422 is connected to the other end of the second switch SW2 and the second input terminal K _eff of the voltage controlled oscillator 500.

The operation states of the switches SW1, SW2, SW3, and SW4 of the loop band selection unit 420 according to the phase locked state can be represented as shown in Table 1 below.

SW status
Loop status ON OFF Out-of-lock SW2, SW4 SW1, SW3 Near-in-lock < RTI ID = 0.0 > SW1, SW4 SW2, SW3 Lock status SW3 SW1, SW2, SW4

That is, when the phase is not fixed as a result of detection of the phase locked state, the second switch SW2 and the fourth switch SW4 of the loop band selection unit 420 are short-circuited and the first switch SW1 and the third switch SW3 Is opened. Therefore, the control voltage Vcon of the loop bandwidth control unit 400 is fixed by the bias power supply Vbias2 connected to the fourth switch SW4, and the operation of the analog band selection loop loop2 by the second switch SW2 The entire phase locked loop operates. Thereafter, when the phase lock is approached, the first switch SW1 and the fourth switch SW4 of the loop band selection unit 420 are short-circuited, and the second switch SW2 and the third switch SW3 are opened. Therefore, in order to match the charge / discharge voltage V _LPF of the loop filter 300 with the control voltage Vcon of the loop-band control unit 400 fixed by the bias power supply Vbias2, the first switch SW1 And a bias power source Vbias1 connected to the bias power source Vbias1. When the operation of matching the two voltages through the first switch SW1 is completed, the third switch SW3 is short-circuited and the first switch SW1, the second switch SW2, and the fourth switch SW4 are turned on, Lt; / RTI > Accordingly, the two voltages are connected to each other through the third switch SW3, and finally operate as a fine loop loop1.

4 is a block diagram illustrating an analog band selector in accordance with an embodiment of the present invention.

4, the analog band selector 422 compares the charging voltage V _LPF of the loop filter 300 with an input voltage Vcoarse generated according to the switching of the second switch SW2 and a reference voltage And generates the control signal F _Eff according to the comparison result and provides the generated control signal F _Eff to the second input terminal K _Eff of the voltage controlled oscillator 500.

The analog band selector 422 may include a plurality of resistors R1 to R9, a plurality of comparators C1 to C8, a plurality of fifth switches SW5_1 to SW5_8, and a plurality of latches Latch1 to Latch8 have. (R9 R1 to) a plurality of resistors can provide a reference voltage source (V _DD) is connected in series to distribute the voltage of the reference power source (V _DD), the first to eighth reference voltage (Vref1 to Vref8) on. The plurality of comparators C1 to C8 are controlled such that the charging and discharging voltage V _LPF of the loop filter 300 is distributed from the reference voltage V _DD and the input voltage Vcoarse generated according to the switching of the second switch SW2 It is possible to compare the first to eighth reference voltages Vref1 to Vref8 respectively and to provide the respective comparison values Fc1 to Fc8 according to the comparison result. The plurality of fifth switches SW5_1 to SW5_8 are respectively connected to the outputs of the plurality of comparators C1 to C8 and are connected to the output of each of the comparators C1 to C8 corresponding to the first switching signal signal1 provided from the switching signal generating unit 410 Fc1 to Fc8 may be provided to the plurality of latches Latch1 to Latch8. The plurality of latches Latch1 to Latch8 are connected to the outputs of the plurality of fifth switches SW5_1 to SW5_8 to receive the respective comparison values Fc1 to Fc8 and to compare the supplied comparison values Fc1 to Fc8 with each other And generates the first to eighth control signals BS1 to BS8 by storing or providing the first to eighth control signals BS1 to BS8 to the second input terminal K _Eff of the voltage controlled oscillator 500 .

The analog band selector 422 outputs the input voltage Vcoarse and the first to eighth reference voltages Vref1 to Vref8 to the respective comparators C1 to C8 when the phase is not locked, C8), and outputs the respective comparison values Fc1 to Fc8 according to the comparison result. The output comparison values Fc1 to Fc8 are stored through the respective latches Latch1 to Latch8 and the first to eighth control signals BS1 to BS8, which are the outputs of the latches Latch1 to Latch8, To the second input (K _Eff ) of the control oscillator (500). In addition, when the phase locking is close, the analog band selector 422 opens each of the fifth switches SW5_1 to SW5_8 to block the latches (Latch1 to Latch8) and the loop filter (300). The first to eighth control signals BS1 to BS8 set in the analog band selector 422 are fixed to the respective latches Latch1 to Latch8 before the respective latches Latch1 to Latch8 and the loop filter 300 are cut off The input voltage Vcoarse is varied, and even if the comparison values Fc1 to Fc8, which are the outputs of the comparators C1 to C8, are changed, no further band movement occurs.

5 is a graph showing a correlation between a control voltage and an output signal of a phase locked loop according to an embodiment of the present invention.

5, when the phase locked loop operates in the analog band selection loop (loop 2), that is, whenever the control signal F _Eff of the analog band selector 422 changes, the band is selected and the control voltage Vcon is selected. The phase locked loop can be finally switched to the fine loop operation (loop 1) and finally operate stably when a certain band is finally selected and becomes close to the phase lock.

 That is, when operating in the analog band selection loop (loop 2), the phase locked loop has gain for all bands, and thus has a gain of a large voltage controlled oscillator. In addition, when operating as a fine loop (loop 1), the phase locked loop has a gain of a low voltage controlled oscillator as shown in Equation (1) below, thereby suppressing the spur size.

 As described above, the phase locked loop according to an embodiment of the present invention increases the gain of the voltage controlled oscillator when the phase locked state is not detected as a result of detection of the phase locked state, so that it has a wide band characteristic, The effect is provided. Further, when the phase locked loop according to an embodiment of the present invention detects the phase locked state and the phase locked state is obtained, the gain of the voltage controlled oscillator is reduced to have a narrow band characteristic to further improve the noise characteristic of the phase locked loop , And the spur can be further suppressed. Therefore, the phase locked loop according to one embodiment of the present invention can have a good hold characteristic simultaneously with a fast phase hold time.

Referring to FIG. 2, a voltage controlled oscillator (VCO) 500 is connected to the loop bandwidth control unit 400. A voltage controlled oscillator 500, a second input terminal that receive a control signal (F _Eff) from the first input terminal (K _LPF) and a loop bandwidth controller 400 supplied a control voltage (Vcon) from the loop bandwidth controller 400 ( K _Eff ). The voltage controlled oscillator 500 may adjust the gain according to the control signal F _Eff provided from the loop bandwidth control unit 400 to provide the output signal F out. The voltage controlled oscillator 500 may include a plurality of PMOS transistors provided with the first to eighth control signals BS1 to BS8 provided from the analog band selector 422, respectively.

A frequency divider (DIV: Divider) (600) is a voltage controlled oscillator the provided by the (500) divides the output signal (Fout) to the frequency division ratio preset to generate a feedback signal (F _DIV) and the resulting feedback signal (F _DIV) To the phase frequency detector (100).

Second Example

2 is a circuit diagram illustrating a phase locked loop according to an embodiment of the present invention.

Referring to FIG. 2, a phase locked loop according to an embodiment of the present invention includes a phase frequency detector 100, a charge pump 200, a loop filter 300, a loop band controller 400, a voltage controlled oscillator 500, A frequency-to-voltage converter 700, and a frequency divider 600. In the following description, the overlapped portions of the phase frequency detector 100, the charge pump 200, the loop filter 300, the loop bandwidth controller 400, and the frequency divider 600 are omitted for the sake of explanation. do.

A voltage controlled oscillator (VCO) 500 is connected to the loop bandwidth control unit 400 and the frequency-to-voltage converter 700. A voltage controlled oscillator 500, a second input terminal that receive a control signal (F _Eff) from the first input terminal (K _LPF), a loop bandwidth controller 400 supplied a control voltage (Vcon) from the loop bandwidth controller 400 ( K _Eff and a third input K _FVC that is provided with a feedback voltage V _FVC from the frequency-to-voltage converter 700. The voltage controlled oscillator 500 may adjust the gain according to the control signal F _Eff provided from the loop bandwidth control unit 400 to provide the output signal F out. The voltage controlled oscillator 500 may include a plurality of PMOS transistors provided with the first to eighth control signals BS1 to BS8 provided from the analog band selector 422, respectively.

6 is a circuit diagram showing a voltage-controlled oscillator of a ring structure according to an embodiment of the present invention.

Referring to FIG. 6, the voltage controlled oscillator 500 may include three inputs: a first input K _LPF , a second input K _Eff , and a third input K _FVC . The first input terminal K _LPF is supplied with the control voltage Vcon from the loop band control unit 400 and the second input terminal K _eff is input from the analog band selector 422 of the loop band control unit 400, 8 control signals BS1 to BS8 and the third input terminal K _FVC is provided with a feedback voltage V _FVC from the frequency-to-voltage converter 700.

The voltage controlled oscillator 500 also has two voltage control resistors VCR1 and VCR2 in a differential ring structure that is highly resistant to high frequency oscillation and noise characteristics and has control signals BS1 to BS8 provided from the analog band selector 422, A plurality of transistors may be provided. In particular, the voltage-controlled oscillator 500 is an eight PMOS transistor to transfer to a higher band Each additional low signal "0" in the first to the eighth control signal (BS1 to BS8), a control signal (F _Eff) Can be included in the inner cell. In addition, the voltage-controlled oscillator 500 selects the highest frequency band when the eight PMOS transistors are turned on as the frequency of the current increases as the current flows in the internal cells. However, since the voltage-controlled oscillator 500 does not perform a normal operation when a large amount of current flows at the same time, the voltage controlled oscillator 500 adjusts the size so that the current flowing in the plurality of PMOS transistors is small.

In addition, the voltage control resistors VCR1 and VCR2 of the voltage controlled oscillator 500 can be used to control the output signal Fout. That is, the control voltage Vcon, which is the output of the loop bandwidth control unit 400, and the feedback voltage V _FVC , which is the output of the frequency-to-voltage converter 700, are input to the voltage controlled oscillator 500 And the output signal Fout of the output terminal OUT. Particularly, the voltage control resistors VCR1 and VCR2 can change the change of the input voltage to the change of the large current, so that the voltage controlled oscillator 500 of the ring structure can have a wide output signal Fout range.

A frequency-to-voltage converter (FVC) 700 is provided with an output signal Fout provided from the voltage-controlled oscillator 500 and generates a feedback voltage V _FVC corresponding to the output signal Fout. The frequency-to-voltage converter 700 may feed back the generated feedback voltage V _FVC to the voltage-controlled oscillator 500 to remove noise from the voltage-controlled oscillator 500.

FIG. 7 is a circuit diagram showing a detailed structure of a frequency-voltage converter according to an embodiment of the present invention, and FIG. 7B is a circuit diagram showing a control signal generator for generating a control signal provided to the frequency-to- c is a timing chart for explaining the operation of the control signals generated by the control signal generator of FIG. 7 (b).

Referring to FIG. 7A, the frequency-to-voltage converter 700 includes two NMOS transistors mn and a PMOS transistor mp, two capacitors Cx and Cy, and one sampling switch . Here, the two NMOS transistors mn and the PMOS transistor mp are constituted by an inverter circuit having drain terminals connected to each other and one terminal connected to the ground potential, and the PMOS transistor mp has a voltage The NMOS transistor mn is switched through the output signal Fout provided from the control oscillator 500 and the NMOS transistor mn is switched through the second control signal 2 generated in the control signal generator input to the gate terminal.

The sampling switch is composed of a CMOS transmission gate in which at least one compensation transistor is added to both of the compensation transistors, one side of which is connected to the drain terminal of the NMOS transistor mn and the PMOS transistor mp, and the other side of which is connected to a voltage controlled oscillator 500 To the output terminal. And is switched through the inverters of the first control signal (1) and the first control signal (1) generated in the control signal generator input to the gate stage.

The two capacitors Cx and Cy may be connected at one end to the front end and at the rear end of the sampling switch, respectively, and the other end may be connected to the ground potential.

7 (b), the control signal generator includes three inverters and two AND gates. The control signal generator receives the output signal Fout output from the voltage-controlled oscillator 500 as input, A first control signal 1 and a second control signal 2 delayed by a predetermined time from the first control signal 1 are generated. The first control signal 1 and the second control signal 2 are generated by making the first control signal 1 and the second control signal 2 not overlap each other. In this way, the control signal generator uses a simple two-division period so that the high / low ratio of the output of the voltage-controlled oscillator 500 becomes constant.

As described above, the phase locked loop according to an embodiment of the present invention provides another negative feedback loop composed of a frequency-to-voltage converter and a voltage controlled oscillator, so that the phase locked loop can operate more stably. Also, the phase-locked loop according to an embodiment of the present invention provides the effect of further removing noise by using a frequency-to-voltage converter operating in a fine loop.

Loop analysis

8 is a conceptual diagram illustrating a phase locked loop according to an embodiment of the present invention.

8, a phase locked loop according to an embodiment of the present invention includes a phase frequency detector 100, a charge pump 200, a secondary loop filter 300, an analog band selection circuit 400, a voltage controlled oscillator 500, a frequency-to-voltage converter 700, and a frequency divider 600. In particular, the frequency-to-voltage converter 700 generates a feedback voltage V _FVC corresponding to the output signal Fout of the voltage controlled oscillator 500 and forms a further negative feedback loop with the voltage controlled oscillator 500 .

The phase locked loop may become unstable when phase locking is not achieved, i.e., when it has a wide bandwidth. However, the phase locked loop can operate more stably by constituting another sub feedback loop composed of the multi-phase frequency-voltage converter and the voltage controlled oscillator by the phase locked loop according to an embodiment of the present invention.

9 is a linear model illustrating a phase locked loop according to an embodiment of the present invention.

Referring to FIG. 9, the open loop transfer function when the phase locked loop is phase locked, that is, when operating in the analog band selected loop, is expressed by Equation 2 below, and the closed loop transfer function is expressed by Equation Lt; / RTI >

Also, the open loop transfer function when the phase locked loop is phase locked, that is, when operating as a fine loop, is expressed by Equation (4) below, and the transfer function of the closed loop is expressed by Equation (5).

이고 p는

이며, K는 주파수-전압변환기의 이득이다. 또한, K_LPF는 루프필터(300)의 출력에 대한 전압제어발진기의 이득이고, K_Eff는 아날로그대역선택루프의 출력에 대한 이득이며, K_FVC는 주파수-전압변환기에 대한 전압제어발진기의 이득이다.Referring to Equations (2) to (5) above, z is

And p is

And K is the gain of the frequency-to-voltage converter. Also, K _LPF is the gain of the voltage controlled oscillator for the output of the loop filter 300, K _Eff is the gain for the output of the analog band selection loop, and K _FVC is the gain of the voltage controlled oscillator for the frequency-to-voltage converter .

10 shows a board diagram of an open loop transfer function when operating in an analog band selection loop depending on whether a frequency-to-voltage converter is used or not.

Referring to FIG. 10, an open loop transfer function of a phase locked loop according to an embodiment of the present invention is added to an open loop transfer function of a general phase locked loop by a frequency-to-voltage converter.

Therefore, as shown in FIG. 10, when the gain of the voltage controlled oscillator is increased, the phase margin of the conventional PLL using the conventional second-order loop filter without the frequency-to-voltage converter becomes small and becomes unstable . On the other hand, it can be seen that the PLL according to the embodiment of the present invention has a sufficient phase margin as shown in FIG.

Thus, the frequency-to-voltage converter is controlled so that the feedback voltage corresponding to the output signal (output frequency) of the voltage controlled oscillator, that is, the output signal (output frequency) Fout of the voltage controlled oscillator becomes smaller Or larger) so that the entire PLL can operate more stably.

11 shows a board diagram of an open loop transfer function when operating as a fine loop depending on whether a frequency-voltage converter is used or not.

Referring to FIG. 11, when the phase locked loop operates as a fine loop, since the gain of the voltage controlled oscillator is smaller than that of the analog band selected loop, the phase locked loop And has a phase margin enough to be stable.

However, the phase locked loop according to an embodiment of the present invention provides a noise cancellation by using a frequency-to-voltage converter that operates even in a fine loop.

.

Noise analysis

12 is a linear model illustrating all internal noise sources of a phase locked loop according to an embodiment of the present invention.

Referring to FIG. 12, when the phase locked loop is phase locked, that is, when it operates as a fine loop, a linear model as shown in FIG. 12 can be used. In particular, the noise of each block was considered as added noise at the output of the block.

Further, a transfer function is obtained by using a linear model as shown in FIG. 12, and it is represented by the following Equations (6) to (10).

Referring to Equation (6) to Equation (10), the transfer functions show the effect of the internal feedback loop in terms of noise suppression. That is, the frequency-to-voltage converter term in the denominator of Equations (6) to (10) reduces the size of noise.

13 is a graph comparing noise analysis of (a) a general phase-locked loop using a second-order loop filter and (b) a phase-locked loop including a frequency-to-voltage converter according to an embodiment of the present invention Assuming that the magnitude of the noise in Eq.

As shown in FIG. 13, FIG. 13 shows how the transfer function of each noise source varies as the frequency changes. In particular, it is assumed that the sizes of the respective noise are the same.

Referring to FIG. 13, it can be seen that the phase locked loop according to an embodiment of the present invention has no peak in the transfer function of each noise, unlike the noise transfer function of the conventional phase locked loop. Also, as shown in FIG. 13, it can be seen that a phase noise reduction of 50 dB occurs in a wide frequency band. That is, as the gain of the frequency-to-voltage converter increases, the phase noise reduction increases. Thus, the gain of the higher frequency-to-voltage converter results in more phase noise reduction.

simulation

The phase locked loop according to an embodiment of the present invention was simulated by HSPICE using a CMOS process variable of a supply voltage of 1.8V and 0.18 mu m to verify its operation.

FIG. 14 is a graph showing the output change when the phase locked loop according to an embodiment of the present invention operates as an analog band selection loop. FIG.

14 and 15 are time charts showing the relationship between the charging / discharging voltage V _LPF of the loop filter 300 and the first to eighth control signals BS1 to BS8 of the analog band selector 422 of 11111100 And how it changes with time. At this time, the output frequency of the voltage-controlled oscillator 500 is 953.8 MHz.

As shown in FIG. 14 (a), the phase locked loop according to an embodiment of the present invention operates as an analog band selection loop (loop 2) up to about 13 μs, and after the phase fixed state determination of the phase locked state indicator 412 The first switch SW1 operates and is switched to the fine loop loop1 so that the charging / discharging voltage V _LPF of the loop filter 300 is instantaneously raised to a constant bias voltage and then stabilized . 14 (b) shows that the values of BS1-BS8 change with time.

15 is a graph showing a change in charge / discharge voltage of a loop filter when a phase locked loop according to an embodiment of the present invention operates as an analog band selection loop.

15 (a) shows the operation when BS1-BS8 is 11110000, and the output frequency of the voltage-controlled oscillator 500 is 1 GHz. As shown in FIG. 15 (a), the phase locked loop according to an embodiment of the present invention operates in an analog band selection loop (loop 2) to about 3 μs, and thereafter, It can be seen that the charge / discharge voltage V _LPF is stable after the phase fixing determination of the step 412.

15 (b) is an operation when BS1-BS8 is 11000000, and the output frequency of the voltage-controlled oscillator 500 is 1024 MHz. Figure 15 (b) the V phase-locked loop according to one embodiment of the present invention, after the operation to the analog band selection loop (loop2) to about 17㎲ discharge voltage changes to a micro-loop (loop1) _(LPF, as shown in ) Is stable.

100: phase frequency detector 200: charge pump
300: Loop filter 400: Loop band control unit
410: Switching signal generating unit 412: Phase locked state indicator
414: Operator 420: Loop band selection unit
422: Analog band selector 500: Voltage controlled oscillator
600: frequency divider 700: frequency-to-voltage converter

Claims (16)

A phase frequency detector for comparing phases of a reference signal and a feedback signal obtained by dividing the output signal and generating a comparison result signal according to a comparison result;
A charge pump to provide a current corresponding to the comparison result signal;
A loop filter for providing a charge / discharge voltage corresponding to a current of the charge pump;
A loop bandwidth control unit receiving the charge / discharge voltage from the loop filter, receiving a comparison result signal from the phase frequency detector to detect a phase locked state, and providing a control voltage and a control signal according to a detection result;
A voltage controlled oscillator including a first input terminal receiving the control voltage from the loop bandwidth control unit and a second input terminal receiving the control signal and adjusting the gain according to the control signal to provide an output signal; And
A frequency divider for dividing the output signal to generate the feedback signal and providing the feedback signal to the phase frequency detector. The method according to claim 1,
Wherein the loop band selection control unit comprises:
Wherein the control voltage is fixed by a bias power supply when the phase locked state is not detected as a result of detection of the phase locked state and the control signal is generated in accordance with the charge and discharge voltage of the loop filter,
Performing a function of matching the charge / discharge voltage of the loop filter with the control voltage fixed to the bias power source through a bias power source when phase fixing is detected as a result of detection of the phase locked state,
And connecting the charge / discharge voltage of the loop filter to the control voltage when phase locking is achieved as a result of detection of the phase locked state. The method according to claim 1,
Wherein the loop-
A switching signal generating unit for receiving the comparison result signal to detect a phase locked state and providing a switching signal according to a detection result; And
And a loop band selection unit provided with the charge / discharge voltage and providing the control voltage and the control signal in accordance with the switching signal provided from the switching signal generation unit. The method of claim 3,
The switching signal generating unit includes:
A phase locked state indicator for receiving the comparison result signal to detect a phase locked state and providing a detection result signal according to a detection result; And
And a calculator for receiving the detection result signal from the phase locked state indicator and providing the first, second and third switching signals, which are the switching signals, to the loop band selection unit through calculation. The method of claim 4,
The computing unit includes:
A first AND gate, a first inverter, a second inverter, and a buffer,
The first switching signal is the detection result signal,
And the second switching signal is a signal obtained by receiving the detection result signal and the signal obtained by inverting the detection result signal through the first inverter by the first AND gate,
Wherein the third switching signal is a signal obtained by receiving a signal delayed through the buffer by the detection result signal and a signal obtained by inverting the second switching signal through the second inverter by the second AND gate. The method of claim 5,
Wherein the loop band selection unit comprises:
A first switch connected between a bias power supply and an output of the loop filter, the first switch being switched in accordance with the second switching signal;
A second switch that is switched in response to the first switching signal and has one end connected to the output of the loop filter;
A third switch connected between the output of the loop filter and a first input of the voltage controlled oscillator, the third switch being switched in response to the third switching signal;
A fourth switch connected between a bias power supply and a first input of the voltage controlled oscillator, the fourth switch being switched in response to the third switching signal; And
Wherein the loop filter is connected to the other end of the second switch and to the second input of the voltage controlled oscillator, and the charging / discharging voltage of the loop filter is compared with an input voltage generated in response to switching of the second switch, And an analog band selector for providing said control signal. The method of claim 6,
Wherein the analog band selector comprises:
A plurality of resistors connected in series to a reference power supply to provide the first to eighth reference voltages, respectively, as the reference voltages;
A plurality of comparators for comparing the input voltage with the first to eighth reference voltages, respectively, and providing respective comparison values according to a comparison result;
A plurality of fifth switches respectively connected to the outputs of the plurality of comparators to provide the respective comparison values corresponding to the first switching signal; And
And a plurality of latches respectively connected to outputs of the plurality of fifth switches and storing or providing the respective comparison values to provide the first to eighth control signals as the control signals. The method of claim 7,
Wherein the voltage-
And a plurality of PMOS transistors provided respectively to the first to eighth control signals provided from the analog band selector. A phase frequency detector for comparing phases of a reference signal and a feedback signal obtained by dividing the output signal and generating a comparison result signal according to a comparison result;
A charge pump to provide a current corresponding to the comparison result signal;
A loop filter for providing a charge / discharge voltage corresponding to a current of the charge pump;
A loop bandwidth control unit receiving the charge / discharge voltage from the loop filter, receiving a comparison result signal from the phase frequency detector to detect a phase locked state, and providing a control voltage and a control signal according to a detection result;
A first input terminal receiving the control voltage from the loop bandwidth control unit, a second input terminal receiving the control signal, and a third input terminal receiving the feedback voltage, wherein the gain control unit adjusts the gain according to the control signal, A voltage controlled oscillator;
A frequency-to-voltage converter that generates the feedback voltage corresponding to the output signal provided from the voltage-controlled oscillator and feeds back the feedback voltage to the voltage-controlled oscillator to remove noise of the voltage-controlled oscillator; And
A frequency divider for dividing the output signal to generate the feedback signal and providing the feedback signal to the phase frequency detector. The method of claim 9,
Wherein the loop band selection control unit comprises:
Wherein the control voltage is fixed by a bias power supply when the phase locked state is not detected as a result of detection of the phase locked state and the control signal is generated in accordance with the charge and discharge voltage of the loop filter,
Performing a function of matching the charge / discharge voltage of the loop filter with the control voltage fixed to the bias power source through the bias power supply when phase fixing is detected as a result of detection of the phase locked state,
And connecting the charge / discharge voltage of the loop filter to the control voltage when phase locking is achieved as a result of detection of the phase locked state. The method of claim 9,
Wherein the loop-
A switching signal generating unit for receiving the comparison result signal to detect a phase locked state and providing a switching signal according to a detection result; And
And a loop band selection unit provided with the charge / discharge voltage and providing the control voltage and the control signal in accordance with the switching signal provided from the switching signal generation unit. The method of claim 11,
The switching signal generating unit includes:
A phase locked state indicator for receiving the comparison result signal to detect a phase locked state and providing a detection result signal according to a detection result; And
And a calculator for receiving the detection result signal from the phase locked state indicator and providing the first, second and third switching signals, which are the switching signals, to the loop band selection unit through calculation. The method of claim 12,
The computing unit includes:
A first AND gate, a first inverter, a second inverter, and a buffer,
The first switching signal is the detection result signal,
And the second switching signal is a signal obtained by receiving the detection result signal and the signal obtained by inverting the detection result signal through the first inverter by the first AND gate,
Wherein the third switching signal is a signal obtained by receiving a signal delayed through the buffer by the detection result signal and a signal obtained by inverting the second switching signal through the second inverter by the second AND gate. 14. The method of claim 13,
Wherein the loop band selection unit comprises:
A first switch connected between a bias power supply and an output of the loop filter, the first switch being switched in accordance with the second switching signal;
A second switch that is switched in response to the first switching signal and has one end connected to the output of the loop filter;
A third switch connected between the output of the loop filter and a first input of the voltage controlled oscillator, the third switch being switched in response to the third switching signal;
A fourth switch connected between a bias power supply and a first input of the voltage controlled oscillator, the fourth switch being switched in response to the third switching signal; And
Wherein the loop filter is connected to the other end of the second switch and to the second input of the voltage controlled oscillator, and the charging / discharging voltage of the loop filter is compared with an input voltage generated in response to switching of the second switch, And an analog band selector for providing said control signal. 15. The method of claim 14,
Wherein the analog band selector comprises:
A plurality of resistors connected in series to a reference power supply to provide the first to eighth reference voltages, respectively, as the reference voltages;
A plurality of comparators for comparing the input voltage with the first to eighth reference voltages, respectively, and providing respective comparison values according to a comparison result;
A plurality of fifth switches respectively connected to the outputs of the plurality of comparators to provide the respective comparison values corresponding to the first switching signal; And
And a plurality of latches respectively connected to outputs of the plurality of fifth switches and storing or providing the respective comparison values to provide the first to eighth control signals as the control signals. 16. The method of claim 15,
Wherein the voltage-
And a plurality of PMOS transistors provided respectively to the first to eighth control signals provided from the analog band selector.

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