JP3386026B2 - PLL circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a PLL (Phase-Lock).
ed loop) circuit, and more particularly, to a technique for preventing malfunction at the time of starting a PLL circuit in which some of the constituent elements are provided outside.

[0002]

2. Description of the Related Art Conventionally, a PLL circuit is known as one of the basic technologies used in the fields of information processing and communication. This PLL circuit is often integrated in one device and provided by the manufacturer. However, in order to be applied to various applications, some of the components of the PLL circuit can be connected to the outside of the device. PLL circuits are also provided.

FIG. 6 shows an example in which such a conventional PLL circuit is applied to a part of an auto scan type tuner. This PLL circuit includes a voltage controlled oscillator (VCO) 10
A low pass filter (LPF) 11 is provided outside the device, and includes an input buffer 20, a programmable divider (PD) 21, a phase frequency comparator (Φ / D) 22, a charge pump (CP) 23, an N value register 24, and a reference. The signal generator (REF) 25 and the central processing unit (hereinafter referred to as "C
A PU (abbreviated as “PU”) 30 is provided inside the device. The CPU 30 may be provided outside the device.

First, the structure and operation of the basic part of the PLL circuit will be described. The phase frequency comparator 22 compares the phase and frequency of the reference signal f _REF from the reference signal generator 25 and the feedback signal f _FB from the programmable divider 21, and increments the increment signal UP and the decrement representing the error between these signals. The signal DOWN is generated and supplied to the charge pump 23.
The phase frequency comparator 22 also has a lock signal LOCK indicating that the PLL circuit has entered the locked state.
Is generated and supplied to the CPU 30.

The charge pump 23 generates a current pulse corresponding to each pulse width of the increment signal UP and the decrement signal DOWN, and the low pass filter 1 provided outside the device.
Supply to 1. The low-pass filter 11 generates a voltage according to the current pulse supplied from the charge pump 23 and supplies it to the voltage controlled oscillator 10.

The voltage controlled oscillator 10 generates an output signal f _OUT oscillating at a frequency according to the magnitude of the voltage supplied from the low pass filter 11 and supplies it to the programmable divider 21 via the input buffer 20. The oscillation frequency of the output signal f _OUT is the reference signal f _{REF in the} locked state.
N times the frequency of. Programmable divider 21
Outputs the output signal f _OUT to 1 / N and supplies it to the phase frequency comparator 22.

The N value register 24 stores the N value for determining the frequency division ratio of the programmable divider 21. This N value is set by the CPU 30. When auto-scanning is performed by this tuner, the CPU 30 increments the N value that sequentially increases when scanning upward, and the N value that sequentially decreases when scanning downward, at the N value register 24 at predetermined time intervals (cycles). Set to. The N value stored in the N value register 24 is the programmable divider 2
1 is supplied. As a result, the frequency division ratio in the programmable divider 21 is determined.

The conventional PLL circuit configured as described above operates as follows. Now, the feedback signal f input from the programmable divider 21 to the phase frequency comparator 22
Assuming that the phase of _FB lags the phase of the reference signal f _REF , the phase frequency comparator 22 generates an increment signal UP having a pulse width corresponding to the frequency decrease and the phase delay,
Supply to the charge pump 23. As a result, the charge pump 23 outputs a current according to the increment signal UP. As a result, the voltage generated by the low-pass filter 11 increases, the oscillation frequency of the output signal f _OUT from the voltage controlled oscillator 10 increases, and the phase of the output signal f _OUT advances and approaches the phase of the reference signal f _REF. .

On the other hand, the feedback signal f_FBIs the reference signal f
_REFIf it is ahead of the phase of, the phase frequency comparator 2
2 has a pulse width corresponding to the amount of frequency rise and phase advance
Generates a decrement signal DOWN, and supplies it to the charge pump 23.
To pay. By this. The charge pump 23 uses the decrement signal D
A current corresponding to OWN is drawn. As a result, lowpass
The voltage output from the filter 11 becomes low and the voltage control
Output signal f from shaker 10_OUTThe oscillation frequency of
Together with the output signal f_OUTOf the reference signal f _REFof
It approaches the phase.

As described above, in the PLL circuit, the output signal f
The phase and frequency of _{OUT and} the phase and frequency of the reference signal f _{R EF} are constantly compared, and the output signal f with respect to the reference signal f _REF is compared.
If there is a phase delay or phase lead of _OUT , feedback control is performed to correct them. Then, when the phase delay and the phase lead converge within a predetermined range, the PLL circuit enters a lock state, and a lock signal LOC indicating that effect is generated.
Output K. In this locked state, the output signal f
The phase of _OUT matches the phase of the reference signal f _REF .

Next, the operation when the PLL circuit is applied to an auto scan type tuner will be described.

FIG. 7 is a timing chart showing the operation when the PLL circuit operates normally, that is, when the device and the voltage controlled oscillator start operating at substantially the same time in response to power-on. In this case, the voltage controlled oscillator 10
As shown in FIG. 7A, the CPU 30 sets the N value register 2
When the N value can be set to 4, oscillation starts at approximately the same time or before that. The waveform of the output signal f _OUT shown in FIG. 7A is a schematic one, and the actual waveform of the output signal f _{OUT is} a waveform which oscillates at a higher frequency than the waveform shown.

In a predetermined cycle after the power is turned on,
As shown in FIG. 7B, the CPU 30 sets the N value register 2
Setting the "n" as the N value to 4, the programmable divider 21, as shown in FIG. 7 (C), oscillates at a frequency of 1 / n of the oscillation frequency of the output signal f _{OU T} from the voltage controlled oscillator 10 Output the feedback signal f _FB .

Now, the frequency of this feedback signal f _FB is as shown in FIG.
Assuming that the frequency is lower than the frequency of the reference signal f _REF shown in (D) (the high level period is long), the phase frequency comparator 22 corresponds to the difference in the high level period as shown in FIG. 7 (E). Incremental signal UP having a pulse width for
In this case, as shown in FIG. 7 (F), the decrement signal DOWN
Is not output. As a result, the oscillation frequency of the voltage controlled oscillator 10 increases by the amount corresponding to the pulse width of the increment signal UP. Further, in this state, since the PLL circuit is not in the lock state, the lock signal LOCK is not output as shown in FIG.

In the next cycle, when the CPU 30 determines that the lock signal LOCK is not output, it sets the N value "n + 1" in the N value register 24. As a result, the programmable divider 21 has the configuration shown in FIG.
As shown in, the output signal f from the voltage controlled oscillator 10
_The feedback signal f _FB that oscillates at a frequency of 1 / (n + 1) of the oscillation frequency of _OUT is output. The frequency of the feedback signal f _FB is still lower (the high-level period is longer) than the frequency of the reference signal f _REF shown in FIG. 7D, so the phase frequency comparator 22 shows in FIG. 7E. Thus, the increment signal UP having a pulse width corresponding to the difference between the high level periods is output. As a result, the oscillation frequency of the voltage controlled oscillator 10 increases by the amount corresponding to the pulse width of the increment signal UP. Further, in this state, since the PLL circuit is not in the lock state, the lock signal LOCK is not output as shown in FIG.

In the next cycle, when the CPU 30 determines that the lock signal LOCK is not output, it sets the N value "n + 2" in the N value register 24. As a result, the programmable divider 21 has the configuration shown in FIG.
As shown in, the output signal f from the voltage controlled oscillator 10
_The feedback signal f _FB that oscillates at a frequency of 1 / (n + 2) of the _OUT oscillation frequency is output. Since the frequency of the feedback signal f _FB is substantially the same as the frequency of the reference signal f _REF shown in FIG. 7D, the phase frequency comparator 22 is as shown in FIGS. 7E and 7F. Incremental signal UP and decremental signal D
Neither OWN is output. As a result, the phase frequency comparator 22 enters the locked state and outputs the lock signal LOCK as shown in FIG.

In the next cycle, when the CPU 30 determines that the phase frequency comparator 22 outputs the lock signal LOCK, it does not set the N value in the N value register 24. As a result, the update of the contents of the N value register 24 is stopped. The tuner tunes at the frequency of the output signal f _OUT output from the voltage controlled oscillator 10 in this locked state.

[0018]

However, the above-mentioned conventional PLL circuit has the following problems. That is, the device immediately starts operating in response to power-on, but the external voltage-controlled oscillator may start operating after a delay. This phenomenon also occurs in a tuner provided with a plurality of voltage controlled oscillators corresponding to a plurality of frequency bands, when the voltage controlled oscillators are switched according to the change of the frequency band to be tuned.

When this phenomenon occurs, if a minute signal, that is, noise is mixed into the output line of the voltage controlled oscillator before the voltage controlled oscillator starts oscillating, the PLL circuit operates in response to this noise. There is a problem that it starts and falls into an inoperable state. The operation when the PLL circuit causes a problem will be described with reference to the timing chart shown in FIG.

FIG. 8A shows the output signal f _OUT from the voltage controlled oscillator 10. This output signal f _OUT is output to the CPU 30.
When N becomes a state in which the N value can be set in the N value register, it is deformed by noise almost at the same time, and becomes a steady oscillation waveform after that. Note that the waveform of the output signal f _OUT including noise shown in FIG. 8A is a schematic one, and the actual noise and the waveform of the output signal f _OUT oscillate at a higher frequency than the waveform shown. It is a waveform that FIG. 2 described later
(A) and the waveform of the output signal f _{OU T} in FIG. 5 (A) is the same as above.

In a predetermined cycle after the power is turned on,
As shown in FIG. 8B, the CPU 30 sets the N value register 2
When "n" is set as the N value in 4, the programmable divider 21 outputs the feedback signal f _FB that oscillates at a frequency of 1 / n of the noise frequency, as shown in FIG. 8C.

Now, the frequency of this feedback signal f _FB is as shown in FIG.
Assuming that the frequency is higher than the frequency of the reference signal f _REF shown in (D) (the high level period is short), the phase frequency comparator 22 corresponds to the difference between the high level periods as shown in FIG. 8 (F). A decrement signal DOWN having a pulse width of In this case, as shown in FIG. 8 (E), the increment signal UP
Is not output. However, since the voltage controlled oscillator 10 has not yet oscillated, this decrement signal DOWN is ignored. Further, in this state, since the PLL circuit is not in the lock state, the lock signal LOCK is not output as shown in FIG.

In the next cycle, when the CPU 30 determines that the lock signal LOCK is not output from the phase frequency comparator 22, it sets the N value "n + 1" in the N value register 24. However, the voltage controlled oscillator 10
Since the output signal f _OUT from the controller does not change, the feedback signal f _FB output from the programmable divider 21 remains at the low level as shown in FIG. 8 (C). as a result,
The phase frequency comparator 22 outputs a decrement signal DOWN having the same waveform as the reference signal f _REF , as shown in FIG. 8 (F). However, since the voltage controlled oscillator 10 has not yet oscillated, the decrement signal DOWN is ignored. Further, in this state, since the PLL circuit is not in the lock state, the lock signal LOCK is not output as shown in FIG.

The same operation is repeated thereafter, and if the output signal f _OUT from the voltage controlled oscillator 10 does not change, the content of the N value register 24 continues to increase. When the content of the N value register 24 exceeds the maximum N value, an overflow occurs. When this overflow occurs, the PLL circuit does not enter the locked state even if the output signal f _OUT from the voltage controlled oscillator 10 changes thereafter, so that the PLL circuit falls into an inoperable state. In the above, the case of scanning above the frequency with the tuner, that is, the case where the N value increases from “n” has been described. However, underflow occurs due to the same operation as described above, and the PLL circuit becomes inoperable.

The above-mentioned noise is usually at a level that the input buffer cannot sense, but if the manufactured device (input buffer) has high sensitivity, the above-mentioned problems occur. In order to avoid this problem, it is necessary to set the sensitivity allowable value to a narrow value, which causes a problem that the device yield is deteriorated. Further, even if the sensitivity is within the predetermined allowable value, if the noise amplitude is large, the above-mentioned problems cannot be avoided.

In the conventional PLL circuit, even if the device and the voltage-controlled oscillator start up at approximately the same time in response to power-on, the synchronization may be lost for some reason during the subsequent operation. For example, a change in the contents of the programmable frequency divider due to noise causes loss of synchronization. As an invention that solves this problem, for example, Japanese Patent Laid-Open No. 60-72341 discloses "a channel setting system for a PLL synthesizer circuit". The present invention includes a detection circuit for detecting loss of synchronization of a PLL synthesizer circuit, and when this loss of synchronization detection circuit detects loss of synchronization, refresh operation is performed by re-inputting frequency division information to a programmable frequency divider. Let As a result, the loss of synchronization caused by noise is immediately repaired.

Further, JP-A-58-48537 discloses that
It is possible to deal with the case where the oscillation frequency of the voltage controlled oscillator is out of the lock operation range for some reason during operation.
LL circuit "is disclosed. This PLL circuit is provided with an unlock signal generation circuit for generating an unlock signal indicating that when the unlock state is established.
When the signal generated by this unlock signal generation circuit indicates the unlocked state for the time set by the unlock time setting circuit or longer, the control circuit sets the signal voltage of the low pass filter within the lock operable range. A re-pulling operation of controlling is performed. As a result, the oscillation frequency of the voltage controlled oscillator is restored within the lockable range.

However, the techniques disclosed in these publications are intended to repair a loss of synchronism when the PLL circuit is already operating, and to recover the loss of synchronization. It does not address the problems that occur when the circuit is started.

The present invention has been made in order to solve the above-mentioned problem, and its purpose is to always start normally without depending on the characteristics of the device and the characteristics of the components connected to the outside thereof. To provide a circuit.

[0030]

In order to achieve the above object, a PLL circuit according to a first aspect of the present invention is a PLL circuit in which a voltage controlled oscillator is connected to the outside of the device, wherein the device is A register for storing data for designating a division ratio, a programmable divider for dividing a signal from the voltage controlled oscillator at a division ratio according to the data stored in the register, and oscillating at a constant frequency A reference signal generator for generating a reference signal, for determining the oscillation frequency of the voltage controlled oscillator based on the feedback signal obtained by dividing by the programmable divider and the reference signal from the reference signal generator. A control circuit for generating and outputting a control signal, and a control circuit for stopping updating of data stored in the register for a predetermined time after power-on The generation of the control signal is stopped, the processing unit for starting the generation of the control signal to the control circuit starts the updating of the data stored in the register after the predetermined time has elapsed, and a city.

The control circuit in the PLL circuit according to the first aspect responds to the selection signal from the processing section by supplying either the feedback signal from the programmable divider or the reference signal from the reference signal generator. A switch for selection may be provided, and the control signal may be generated and output based on a signal from the switch and a reference signal from the reference signal generator. In this case, the processing unit supplies a selection signal for selecting the reference signal to the switch for a predetermined time after power-on, and a selection signal for selecting the feedback signal after the predetermined time has elapsed. Can be configured to be supplied to the switch.

In the PLL circuit according to the first aspect, the control circuit includes a phase frequency comparator for comparing the phase and frequency of the feedback signal from the programmable divider and the reference signal from the reference signal generator, Passing and blocking of the comparison result signal from the phase frequency comparator,
A switch that controls in response to a selection signal from the processing unit, and the control signal may be generated and output based on the signal from the switch. In this case, the processing unit supplies the switch with a selection signal for blocking passage of the comparison result signal from the phase frequency comparator for a predetermined time after power-on, and after the predetermined time has elapsed, the processing unit supplies the selection signal. It can be configured to supply the switch with a selection signal for passing the comparison result signal.

A PLL circuit according to a second aspect of the present invention is a PLL circuit in which a voltage controlled oscillator is connected to the outside of the device for the same purpose as described above, and the device has a frequency division ratio. A register that stores data for designating, a programmable divider that divides a signal from the voltage controlled oscillator at a division ratio according to the data stored in the register, and a reference signal that oscillates at a constant frequency are generated. A reference signal generator, and a control signal for determining the oscillation frequency of the voltage controlled oscillator based on the feedback signal obtained by dividing by the programmable divider and the reference signal from the reference signal generator. Detecting the difference between the frequency of the feedback signal from the programmable divider and the frequency of the reference signal from the reference signal generator. An output circuit and a process of starting the update of the data stored in the register in response to power-on, and updating the contents of the register according to the detection result of the detection circuit after a lapse of a predetermined time from the power-on Parts and.

The detection circuit in the PLL circuit according to the second aspect includes a first counter that counts the number of times the feedback signal from the programmable divider has changed during the predetermined time after the power is turned on, and a predetermined counter for the predetermined time. A second counter for counting the number of times the reference signal from the reference signal generator has changed, and a comparator for outputting the result of comparison between the contents of the first counter and the contents of the second counter as the difference. Can be configured.

[0035]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the same or corresponding parts as those described in the section of the related art are designated by the same reference numerals, and the description will be simplified or omitted.

(Embodiment 1) In the PLL circuit according to Embodiment 1 of the present invention, a switch is provided in the preceding stage of the phase frequency comparator to stop the operation of the PLL loop, and during a predetermined time from power-on. This is to stop counting up the N value. FIG. 1 is a block diagram showing the configuration of the PLL circuit according to the first embodiment. This P
The LL circuit is configured by further adding switches 40 and 41 inside the device of the PLL circuit (see FIG. 6) described in the section of the related art.

The switch 40 is composed of a changeover switch in which either the first terminal A or the second terminal B is connected to the common terminal C in response to the selection signal SEL from the CPU 30. The switch 40 can be composed of, for example, a transistor. The first terminal A of the switch 40 is connected to the output terminal of the programmable divider 21, and the feedback signal f _FB is supplied from the programmable divider 21. The second terminal B is connected to the output terminal of the reference signal generator 25, and the reference signal f _{REF is supplied} from the reference signal generator 25.
Is supplied. Further, the common terminal C is the phase frequency comparator 2
2 is connected to one of the input terminals and supplies either the feedback signal f _FB or the reference signal f _{REF to} the phase frequency comparator 22.

The switch 41 is composed of an open / close switch that opens / closes between the first terminal D and the second terminal E in response to a selection signal SEL from the CPU 30. The switch 41 can be composed of, for example, a transistor.
The first terminal D of this switch 41 is connected to the phase frequency comparator 22.
, And the lock signal LOCK from the phase frequency comparator 22 is supplied. Further, the second terminal E is connected to the CPU 30, and the lock signal LOCK is sent to the CPU 3
Supply to 0.

Next, the operation of the PLL circuit configured as described above will be described. The operation of the PLL circuit in the normal case where the device and the voltage controlled oscillator 10 start operating at substantially the same time in response to power-on is the same as the operation of the conventional PLL circuit described with reference to FIG. Therefore, in the following, in a case where the device starts up in response to power-on and the voltage-controlled oscillator 10 starts its operation with a delay, and noise is mixed in the output line of the voltage-controlled oscillator 10, an abnormal case occurs. The operation of the PLL circuit will be described with reference to the timing chart shown in FIG.

Immediately after the power is turned on, it is assumed that the common terminal C of the switch 40 is connected to the second terminal B and the switch 41 is opened by the selection signal SEL from the CPU 30. FIG. 2A shows the output signal f _OUT from the voltage controlled oscillator 10. This output signal f _OUT is the same as the output signal f _OUT shown in FIG.

At a predetermined cycle after the power is turned on,
As shown in FIG. 2B, the CPU 30 uses the N value register 2
Set “n” to 4 as the N value. As a result, the programmable divider 21, as shown in FIG.
Feedback signal f oscillating at a frequency of 1 / n of the noise frequency
Output _FB . However, since the common terminal C of the switch 40 is connected to the second terminal B, the feedback signal f _FB from this programmable divider 21 is ignored, and instead,
The reference signal f _REF from the reference signal generator 25 is supplied to the phase frequency comparator 22.

Therefore, the phase frequency comparator 22 is shown in FIG.
As shown in (E) and FIG. 2 (F), neither the increment signal UP nor the decrement signal DOWN is output. In this state,
Since the output signal f _OUT from the voltage controlled oscillator 10 does not change, the programmable divider 21 does not output the feedback signal f _FB and remains at the low level. If, if the output signal f _OUT from the voltage controlled oscillator 10 changes, but the feedback signal f _FB from the programmable divider 21 is output, feedback signal since neither the increment signal UP and the decrement signal DOWN not output f _FB The frequency of does not change. Also,
The phase frequency comparator 22 outputs the lock signal LOCK, but since the switch 41 is opened, it is not supplied to the CPU 30 as shown in FIG.

In the next cycle, the CPU 30 determines that the lock signal LOCK is not output from the phase frequency comparator 22, and it is the timing to set "n + 1" as the N value in the N value register 24. recognize. However, since the predetermined time has not elapsed since the power was turned on, the N value is not updated, and the N value register 24 holds "n".

The above-mentioned predetermined time can be appropriately determined in consideration of the rise time of various voltage controlled oscillators, that is, the difference between the time when the power is turned on and the time when the output signal f _OUT is output. In this case, it is preferable that the predetermined time is set to the voltage controlled oscillator having the longest rise time. The predetermined time can be configured so that the user can instruct the CPU 30. With this configuration, it is possible to set the time most suitable for the type of the voltage controlled oscillator used.

Further, in this cycle, the output signal f _OUT from the voltage controlled oscillator 10 has not changed yet, so that FIG.
As shown in (C), the feedback signal f _FB output from the programmable divider 21 maintains a low level.

When the above-mentioned predetermined time elapses after the transition in the above state, the CPU 30 outputs the selection signal SEL as shown in FIG. 8 (H). As a result, the common terminal C of the switch 40 is connected to the first terminal A, and the switch 41 is closed. At this point, the voltage controlled oscillator 10 is producing the output signal f _OUT .

It is assumed that the frequency of the feedback signal f _FB is lower than the frequency of the reference signal f _REF shown in FIG. 2D (long high level period) when the switches 40 and 41 are switched. , The phase frequency comparator 22 is shown in FIG.
As shown in (E), the incremental signal UP having a pulse width corresponding to the difference between the high level periods is output. In this case, the decrement signal DOWN is not output as shown in FIG. As a result, the oscillation frequency of the voltage controlled oscillator 10 becomes
It rises by an amount corresponding to the pulse width of the increment signal UP. Further, in this state, since the PLL circuit is not in the lock state, as shown in FIG.
K is not output.

The subsequent operation is the same as the operation described in the section of the prior art. That is, when the CPU 30 determines that the lock signal LOCK is not output from the phase frequency comparator 22, the N value register 24 outputs “n +” as the N value.
1 ”is set. As a result, the programmable divider 21, as shown in FIG.
1 / (n + 1) of oscillation frequency of output signal f _OUT from 0
The feedback signal f _FB that oscillates at the frequency is output. The frequency of the feedback signal f _FB is the reference signal f _REF shown in FIG.
2E, the phase frequency comparator 22 outputs the increment signal UP having a pulse width corresponding to the difference between the high level periods, as shown in FIG. 2E. To do. As a result, the oscillation frequency of the voltage controlled oscillator 10 increases by the amount corresponding to the pulse width of the increment signal UP. Further, in this state, since the PLL circuit is not in the lock state, the lock signal LOCK is not output as shown in FIG.

In the next cycle, when the CPU 30 determines that the phase frequency comparator 22 does not output the lock signal LOCK, it sets the N value "n + 2" in the N value register 24. As a result, the programmable divider 21, as shown in FIG. 2C, is 1 / (n) of the oscillation frequency of the output signal f _OUT from the voltage controlled oscillator 10.
The feedback signal f _FB that oscillates at the frequency of +2) is output. Since the frequency of the feedback signal f _FB is substantially the same as the frequency of the reference signal f _REF shown in FIG. 2 (D), the phase frequency comparator 22 operates as shown in FIGS. 2 (E) and 2 (F). In addition, neither the increment signal UP nor the decrement signal DOWN is output. As a result, the phase frequency comparator 22 enters the locked state,
As shown in FIG. 2G, the lock signal LOCK is output.

In the next cycle, when the CPU 30 determines that the phase frequency comparator 22 outputs the lock signal LOCK, it does not set the N value in the N value register 24. As a result, the update of the contents of the N value register 24 is stopped. The tuner tunes at the frequency of the output signal f _OUT output from the voltage controlled oscillator 10 in this locked state.

As described above, according to the PLL circuit of the first embodiment, the switch is provided in the preceding stage of the phase frequency comparator 22 to stop the operation of the PLL loop, and the N value is maintained for a predetermined time. Therefore, even if noise is generated on the output line of the voltage controlled oscillator from the time when the power is turned on until the predetermined time elapses, it is ignored. As a result, the contents of the N-value counter will not overflow or underflow.

(Embodiment 2) The PLL circuit according to Embodiment 2 of the present invention is provided with a switch in the latter stage of the phase frequency comparator to stop the operation of the PLL loop and keep the N value at a predetermined value for a predetermined time. It is designed to stop counting up. FIG. 3 is a block diagram showing the configuration of the PLL circuit according to the second embodiment. This PLL circuit is
It is configured by further adding a switch 50 inside the device of the PLL circuit (see FIG. 6) described in the section of the related art.

The switch 50 is responsive to a selection signal SEL from the CPU 30 to open / close between the first terminal F and the second terminal G, and the first opening / closing switch 51 and the first terminal H and the second terminal G.
The second opening / closing switch 52 is opened and closed between the terminal I and the terminal I. The switch 50 can be composed of, for example, a transistor.

The first terminal F of the first open / close switch 51 is connected to the output terminal of the phase frequency comparator 22, and the increment signal UP from the phase frequency comparator 22 is supplied. Further, the second terminal G is connected to the charge pump 23, and the increment signal U
P is supplied to the charge pump 23. Although not shown, in the first opening / closing switch 51, when the contact is opened, the first terminal F is grounded via the first resistor R1 and the second terminal G is connected to the second resistor R2. Grounded through.

Similarly, the first terminal H of the second open / close switch 52 is connected to the output terminal of the phase frequency comparator 22, and the decrement signal DOWN from the phase frequency comparator 22 is supplied. The second terminal I is connected to the charge pump 23 and supplies the decrement signal DOWN to the charge pump 23. Although not shown, the second opening / closing switch 5
2 indicates that when the contact is opened, the first terminal H
It is grounded through a resistor R3 and the second terminal I is connected to the fourth resistor R4.
Grounded through.

Next, the operation of the PLL circuit configured as described above will be described. When the PLL circuit operates normally,
The operation is the same as that of the conventional PLL circuit described with reference to FIG. Therefore, the operation of the PLL circuit in the abnormal case will be described below with reference to the timing chart shown in FIG.

Immediately after the power is turned on, it is assumed that the first and second open / close switches 51 and 52 included in the switch 50 are both opened by the selection signal SEL from the CPU 30. FIG. 2A shows the output signal f _OUT from the voltage controlled oscillator 10. This output signal f _OUT is the same as the output signal f _OUT shown in FIG.

In a predetermined cycle after the power is turned on,
As shown in FIG. 2B, the CPU 30 sets the N value register 2
Set “n” to 4 as the N value. This allows professionals
The programmable divider 21 has 1 / n of the noise frequency.
Feedback signal f oscillating at frequency _FBIs output. Phase frequency
The comparator 22 outputs the feedback signal f_FBAnd the reference signal f_REFAnd to
Based on either the increment signal UP or the decrement signal DOWN,
Output, but the first open / close switch 51 and the second open / close switch
Charge pump 2 because all of the chi 52 are open
Not transmitted to 3. At this time, two charge pumps 23
The input of is set to low level. Therefore, the charge port
As shown in FIGS. 2 (E) and 2 (F) when viewed from the pump 23.
Both the increment signal UP and the decrement signal DOWN are output.
It is equal to not being forced.

In this state, since the output signal f _OUT from the voltage controlled oscillator 10 does not change, the feedback signal f _FB is not output from the programmable divider 21. If, if the output signal f _OUT from the voltage controlled oscillator 10 changes, but the feedback signal f _FB from the programmable divider 21 is output, feedback signal since neither the increment signal UP and the decrement signal DOWN not output f _FB The frequency of does not change. If the frequency of the feedback signal f _FB generated based on noise does not match the frequency of the reference signal f _REF , the phase frequency comparator 22 outputs the lock signal LOCK as shown in FIG. 2 (G). Even if the lock signal LOCK is output coincidentally without doing so, the CPU 30 ignores it because the predetermined time has not elapsed.

In the next cycle, the CPU 30 determines that the lock signal LOCK is not output from the phase frequency comparator 22 and that the predetermined time has not elapsed even if the lock signal LOCK is output, and the CPU 30 determines that N It is recognized that it is time to set “n + 1” as the N value in the value register 24. However, since the predetermined time has not elapsed since the power was turned on, the N value is not updated and N
The value register 24 holds "n". Here, the predetermined time can be set similarly to the case of the first embodiment.

Further, in this cycle, the output signal f _OUT from the voltage controlled oscillator 10 has not changed yet, so that FIG.
As shown in (C), the feedback signal f _FB output from the programmable divider 21 maintains a low level.

When a predetermined time elapses after the transition in the above state, the CPU 30 causes the selection signal S to be output as shown in FIG.
Output EL. As a result, the first opening / closing switch 52 and the second opening / closing switch 52 are closed. At this point,
The voltage controlled oscillator 10 generates an output signal f _OUT .

Assuming that the frequency of the feedback signal f _FB is lower than the frequency of the reference signal f _REF shown in FIG. 2D at the time when the switch 50 is switched (the high level period is long), the phase The frequency comparator 22 is shown in FIG.
As shown in (E), the incremental signal UP having a pulse width corresponding to the difference between the high level periods is output. In this case, the decrement signal DOWN is not output as shown in FIG. As a result, the oscillation frequency of the voltage controlled oscillator 10 becomes
It rises by an amount corresponding to the pulse width of the increment signal UP. At this point in time, since the PLL circuit is not in the lock state, the lock signal LOC is set as shown in FIG.
K is not output. The subsequent operation is the same as the operation described in the section of the related art.

As described above, according to the PLL circuit of the second embodiment, the switch is provided in the subsequent stage of the phase frequency comparator 22 to stop the operation of the PLL loop, and the N value is maintained for a predetermined time. Therefore, even if noise is generated on the output line of the voltage controlled oscillator from the time when the power is turned on until the predetermined time elapses, it is ignored. As a result, the contents of the N-value counter will not overflow or underflow.

(Third Embodiment) The PLL circuit according to the third embodiment of the present invention resets the N value based on the difference between the frequency of the reference signal f _{REF and} the frequency of the feedback signal f _FB , and thereby the N value register. This allows the PLL circuit to start normally even if the contents of (1) overflow or underflow.

This PLL circuit has X2 inside the device of the PLL circuit (see FIG. 6) described in the section of the prior art.
Counter 61, 1/2 counter 62, REF counter 6
3, X2 comparator 64 and 1/2 comparator 65
Is further added to configure.

The X2 counter 61 counts the frequency obtained by doubling the frequency of the feedback signal f _FB from the programmable divider 21. The X2 counter 61 can be composed of a counter that counts rising or falling changes in the frequency of the feedback signal f _FB and a shifter that shifts the output of this counter in the upper direction. This X2 counter 6
The output of 1 is supplied to the X2 comparator 64.

The 1/2 counter 62 is a programmable counter.
Return signal f from the divider 21_FBHalved the frequency of
Count the frequencies. This 1/2 counter 62 is a feedback signal.
Issue f _FBCounts rising or falling changes in frequency
Counter and the output of this counter in the downward direction.
And a shifter that operates. This 1/2
The output of the counter 62 is supplied to the 1/2 comparator 65.
Be done.

The REF counter 63 is the reference signal generator 2
Count the frequency of the reference signal f _REF from 5. This RE
The output of the F counter 63 is the X2 comparator 64 and 1 /
2 is supplied to the comparator 65.

The X2 comparator 64 has an X2 counter 6
A comparison result signal indicating whether or not the count value from 1 has become equal to or larger than a predetermined multiple of the count value from the REF counter 63 is supplied to the CPU 30. Also, the 1/2 comparator 6
Reference numeral 5 supplies a comparison result signal indicating whether or not the count value from the 1/2 counter 62 is equal to or less than half of the count value from the REF counter 63 to the CPU 30.

Next, the operation of the PLL circuit configured as described above will be described. When the PLL circuit operates normally,
The operation is the same as that of the conventional PLL circuit described with reference to FIG. Therefore, the operation of the PLL circuit in the abnormal case will be described below with reference to the timing chart shown in FIG.

FIG. 5A shows the output signal f _OUT from the voltage controlled oscillator 10. This output signal f _OUT is shown in FIG.
It is the same as the output signal f _OUT shown in FIG. At a predetermined cycle after the power is turned on, as shown in FIG.
When the PU 30 sets "n" as the N value in the N value register 24, the programmable divider 21 is set to the state shown in FIG.
As shown in, the feedback signal f _FB that oscillates at a frequency of 1 / n of the noise frequency is output.

Now, the frequency of this feedback signal f _FB is as shown in FIG.
Assuming that the frequency is higher than the frequency of the reference signal f _REF shown in (D) (the high level period is short), the phase frequency comparator 22 corresponds to the difference in the high level period as shown in FIG. 5 (F). A decrement signal DOWN having a pulse width of In this case, as shown in FIG. 5 (E), the increment signal UP
Is not output. However, since the voltage controlled oscillator 10 has not yet oscillated, this decrement signal DOWN is ignored. Further, in this state, since the PLL circuit is not in the lock state, the lock signal LOCK is not output as shown in FIG. Further, the X2 counter 61 is
The counting of the frequency of the feedback signal f _FB is started, and the REF counter 63 starts counting of the frequency of the reference signal f _REF .

In the next cycle, when the CPU 30 determines that the lock signal LOCK is not output from the phase frequency comparator 22, it sets the N value "n + 1" in the N value register 24. However, the voltage controlled oscillator 10
Since the output signal f _OUT from the programmable divider 21 does not change, the feedback signal f _FB output from the programmable divider 21 maintains a low level, as shown in FIG. 5 (C). As a result, the phase frequency comparator 22 outputs the decrement signal DOWN having the same waveform as the reference signal f _REF , as shown in FIG. 5 (F). However, since the voltage controlled oscillator 10 has not yet oscillated, the decrement signal DOWN is ignored. Further, in this state, since the PLL circuit is not in the lock state, the lock signal LOCK is not output as shown in FIG. In this state, the feedback signal f _FB
Is low level, the operation of the X2 counter 61 is stopped, and only the REF counter 63 continues counting.

In the next cycle, the CPU 30 causes the phase
The lock signal LOCK is output from the wave number comparator 22.
It judges that there is no,
Set "n + 1". Even in this state, voltage control
Output signal f from the oscillator 10 _OUTHasn't changed
Then, as shown in FIG. 5C, the programmable divider
Feedback signal f output from 21_FBKeeps low level
It Therefore, the operation of the X2 counter 61 remains stopped.
Then, only the REF counter 63 continues counting.

The same operation is repeated thereafter, and when a predetermined time elapses, the CPU 30 fetches the comparison result signal from the X2 comparator 61 and the comparison result signal from the 1/2 comparator 5. Here, the predetermined time can be set similarly to the case of the first embodiment. Then, when the comparison result from the X2 comparator 64 indicates that the count value of the X2 counter 61 is equal to or more than a predetermined multiple of the count value of the REF counter 63, or the comparison result from the 1/2 comparator 65 is When the count value of the 1/2 counter 62 is less than half the count value of the REF counter 63, the CPU 30 determines that
As shown in (H), a reset signal is supplied to the N value register 24. In this state, the voltage controlled oscillator 10 is generating the output signal f _OUT .

At the time when the reset signal is output, the frequency of the feedback signal f _FB changes to the reference signal f shown in FIG.
Assuming that the frequency is lower than the frequency of _REF (the high level period is long), the phase frequency comparator 22 outputs the increment signal UP having a pulse width corresponding to the difference between the high level periods, as shown in FIG. Is output. In this case, the decrement signal DOWN is not output as shown in FIG. As a result, the oscillation frequency of the voltage controlled oscillator 10 is increased by the increment signal U
It rises by an amount corresponding to the pulse width of P. At this point, the PLL circuit is not in the locked state,
As shown in FIG. 5G, the lock signal LOCK is not output. The subsequent operation is the same as the operation described in the section of the related art.

As described above, according to the PLL circuit of the third embodiment, the frequency of the reference signal f _REF and the feedback signal f are changed after a predetermined time has passed since the power was turned on.
If the difference from the _FB frequency is more than a certain value, the N value register 24
Since N is reset, even if an overflow or underflow has occurred in the N value register 24 at that time, this can be reset. Therefore, the PLL circuit
The N value does not fall into an impossible state due to overflow or underflow after power-on.

[0079]

As described in detail above, according to the present invention,
It is possible to provide a PLL circuit that can always start normally regardless of the characteristics of the device and the characteristics of the components connected to the outside.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a PLL circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the PLL circuit according to the first and second embodiments of the present invention.

FIG. 3 is a block diagram showing a configuration of a PLL circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a PLL circuit according to a third embodiment of the present invention.

FIG. 5 is a timing chart for explaining the operation of the PLL circuit according to the third embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a conventional PLL circuit.

FIG. 7 is a timing chart for explaining a normal operation of a conventional PLL circuit.

FIG. 8 is a timing chart for explaining an abnormal operation of the conventional PLL circuit.

[Explanation of symbols]

10 Voltage controlled oscillator (VCO) 11 Low-pass filter (LPF) 20 input buffers 21 Programmable Divider (PD) 22 Phase frequency comparator (Φ / D) 23 Charge pump (CP) 24 N value register 25 Reference signal generator (REF) 30 CPU 40, 41, 50-52 switch 61 X2 counter 62 1/2 counter 63 REF counter 64 X2 comparator 65 1/2 comparator

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03L ⁷ /06-7/23

Claims (4)

(57) [Claims] 1. A PLL circuit in which a voltage controlled oscillator is connected to the outside of the device, wherein the device stores a register for storing data for designating a frequency division ratio, and a device for storing data according to the data stored in the register. A programmable divider that divides the signal from the voltage controlled oscillator with a division ratio, a reference signal generator that generates a reference signal that oscillates at a constant frequency, and a feedback signal obtained by dividing the signal with the programmable divider. wherein a control circuit for generating and outputting a control signal for determining the oscillation frequency of the voltage controlled oscillator based on the reference signal from the reference signal generator, to said register after between predetermined time from power has passed the Start updating the stored data and
Outputs a start signal for starting the generation of the control signal, prior to
When the lock signal is input from the control circuit,
Processing unit to stop the updating of the data stored in the static, the city
The control circuit is responsive to the start signal.
And a first switch for electrically connecting the processing unit and the processing unit.
The feedback signal and the reference signal from the reference signal generator
When and match, the lock signal is output to the processing unit.
PLL circuit that applies power . 2. The control circuit comprises a second switch for selecting one of a feedback signal from the programmable divider and a reference signal from the reference signal generator in response to a selection signal from the processing section. from signal and the reference signal generator from said second switch
PLL circuit according to claim 1 that generates and outputs the control signal based on said reference signal. 3. The processing unit supplies a selection signal for selecting the reference signal to the second switch for a predetermined time after power-on, and selects the feedback signal after the predetermined time has elapsed. before the selection signal for the said start signal
PLL circuit according to claim 2 for supplying serial first switch and to said second switch. 4.A voltage controlled oscillator is connected external to the device.
Is a PLL circuit I mean The device is A register for storing data for specifying the division ratio, The frequency division ratio according to the data stored in the register
A programmable device that divides the signal from the voltage-controlled oscillator.
With a vida Reference signal generation that generates a reference signal that oscillates at a constant frequency
A vessel, Obtained by dividing by the programmable divider
The feedback signal and the reference signal from the reference signal generator.
To determine the oscillation frequency of the voltage controlled oscillator based on
A control circuit for generating and outputting the control signal of Stored in the register for a predetermined time after power-on
Stop the update of data and control the control circuit
Stop signal generation, and after
When the update of the data stored in the register is started,
Processing for causing the control circuit to start generating the control signal
Section and The control circuit is Feedback signal from the programmable divider and the reference
Compare the phase and frequency with the reference signal from the signal generator
Phase frequency comparator, Passing and passing of the comparison result signal from the phase frequency comparator
Over-blocking is controlled in response to a selection signal from the processing unit.
Switch, and Generates the control signal based on the signal from the switch
OutputPLL circuit.