CN113098501A - Design method of broadband miniaturization rapid frequency synthesis - Google Patents
Design method of broadband miniaturization rapid frequency synthesis Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The invention relates to the technical field of frequency synthesis processing, in particular to a design method of a broadband miniaturization rapid frequency synthesis, which comprises the following steps: step 1: arranging and combining a plurality of programmable frequency dividers, solving frequency dividing ratios, selecting one combination, and executing the step 2; step 2: connecting the combination in series in a phase-locked loop circuit, setting a working voltage threshold and a working current threshold, setting a vibration-stopping switch according to an actual working voltage value and an actual working current value, and executing the step 3; and step 3: controlling the vibration-stopping switch by starting and stopping to obtain different output frequencies, recording the starting time and the period of each vibration-stopping switch operation, repeatedly checking for many times, eliminating data exceeding a working voltage threshold value and a working current threshold value, and executing the step 4; and 4, step 4: the structure of the frequency synthesizer meeting the requirements is obtained.
Description
Technical Field
The invention relates to the technical field of frequency synthesizers, in particular to a design method of a broadband miniaturization rapid frequency synthesizer.
Background
The frequency synthesizer plays a very important role in the fields of modern communications, radar and aerospace, playing a decisive role in the performance of electronic systems and is therefore also referred to as the "heart" of an electronic system. With the rapid development of modern radar, navigation, electronic countermeasure and communication technologies, more rigorous requirements are put forward on the design of the frequency synthesizer, so that the requirements on indexes such as short, stable, long and stable frequency synthesizer, frequency spectrum quality and the like are higher and higher, and the requirements on miniaturization of the frequency synthesizer are also put forward on the size and the weight of the frequency synthesizer.
Disclosure of Invention
Aiming at the defects of the prior art, the invention discloses a design method of a broadband miniaturization rapid frequency synthesizer, which is used for solving the problems that the existing frequency is not stable enough, the precision is the same as that of a crystal oscillator and the cost is low.
The invention is realized by the following technical scheme:
the invention discloses a design method of a broadband miniaturization rapid frequency synthesizer, which comprises the following steps:
step 1: arranging and combining a plurality of programmable frequency dividers, solving frequency division ratio, selecting each combination in sequence for testing, and executing the step 2;
step 2: the testing process comprises the steps of connecting the combination in series to a phase-locked loop circuit, setting an oscillation frequency threshold and a vibration stopping switch, controlling a power supply period through the vibration stopping switch, and executing the step 3;
and step 3: controlling the vibration-stopping switch by starting and stopping to obtain different output vibration frequencies, recording the starting time and the period of each vibration-stopping switch operation, repeatedly testing and recording, eliminating the combination exceeding the vibration frequency threshold value, and executing the step 4;
and 4, step 4: and connecting the eliminated combination in series to a phase-locked loop circuit, and connecting the output of the phase-locked loop circuit with an amplification filtering unit to obtain the designed frequency synthesizer.
Preferably, the frequency synthesizer further comprises a power supply unit, and the power supply unit supplies power to the frequency synthesizer through the vibration-stopping switch.
Preferably, the frequency synthesizer further comprises a frequency synthesizer controller, a control serial port, a DDS unit and a signal conditioning unit, the frequency synthesizer controller is respectively connected with the DDS unit and the combined frequency divider through the control serial port, the output end of the oscillation stop switch is connected with the signal conditioning unit, and the reference power is output to the phase-locked loop circuit through the signal conditioning unit.
Preferably, the signal conditioning unit comprises a voltage-stabilizing tube, a sound meter filter and a conditioning frequency divider, the voltage-stabilizing tube is sequentially connected with the sound meter filter and the conditioning frequency divider, and the reference power is output to the phase-locked loop circuit through the conditioning frequency divider.
Preferably, a frequency-doubled high-frequency signal is generated by the DDS unit, the input end of the DDS unit is the output end of the oscillation stop switch, and the output end of the DDS unit is connected with the signal conditioning unit.
Preferably, the output end of the oscillation stop switch is provided with a filtering unit, and the output end of the filtering unit is respectively connected with the DDS unit and the signal conditioning unit.
Preferably, the phase-locked loop circuit further comprises a phase detector, a loop filter and a voltage-controlled oscillator, the input end of the combined frequency divider is connected with the voltage-controlled oscillator, the output end of the combined frequency divider is connected with the phase detector, and the output end of the conditioning frequency divider is connected with the input end of the phase detector.
Preferably, the frequency dividing ratio of the conditioning frequency divider is eight frequency dividing.
Preferably, the model of the chip selected by the DDS unit is AD 9951.
The invention has the beneficial effects that:
1. according to the invention, the DDS unit and the phase-locked loop system are adopted to obtain smaller output frequency step, and a broadband frequency synthesizer with higher working frequency, wider bandwidth, smaller step and higher phase noise can be obtained.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a circuit schematic of a frequency synthesizer of the present invention;
FIG. 2 is a schematic diagram of a signal conditioning circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a phase locked loop circuit in one embodiment of the invention;
FIG. 4 is a schematic diagram of a first portion of a combined frequency divider in one embodiment of the invention;
fig. 5 is a schematic diagram of a second part of a combined frequency divider in an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, the present embodiment discloses a design method of a broadband miniaturized fast frequency synthesizer, which includes the following steps:
step 1: arranging and combining a plurality of programmable frequency dividers, solving frequency dividing ratios, selecting one combination, and executing the step 2;
it should be noted that, by placing combinations of different frequency division ratios in this embodiment, further calculating frequency synthesis outputs at different frequency division ratios, and determining an optimal frequency division ratio and a permutation and combination of frequency dividers which meet requirements, the case of the frequency division ratio is described in this embodiment by taking ICl and TC9198 as an example.
Step 2: connecting the combination in series in a phase-locked loop circuit, setting a working voltage threshold and a working current threshold, setting a vibration-stopping switch according to an actual working voltage value and an actual working current value, and executing the step 3;
it should be noted that the purpose of setting the operating voltage threshold and the operating current threshold is to avoid damage to the frequency divider due to excessive current and voltage caused by a fault such as a short circuit.
And step 3: controlling the vibration-stopping switch by starting and stopping to obtain different output frequencies, recording the starting time and the period of each vibration-stopping switch operation, repeatedly checking for many times, eliminating data exceeding a working voltage threshold value and a working current threshold value, and executing the step 4;
it should be noted that the purpose of setting the oscillation stop switch is to output pulses with the same power to the filtering unit in equal time periods, so as to ensure that the frequency dividers of different combinations have the same input condition, and further compare the output powers to intuitively know the effect brought by the frequency dividers of different combinations.
And 4, step 4: the structure of the frequency synthesizer which meets the requirements is obtained by obtaining satisfactory output power and further reserving the combination of the frequency dividers;
it is worth to say that the frequency synthesizer also comprises a power supply and a control serial port, and also comprises a frequency synthesis chip and a power supply control unit, wherein the frequency synthesis chip can continuously output stable voltage values and current values through combination and checking calculation, and the frequency synthesis chip outputs the processed frequency.
It should be noted that, referring to fig. 4 and 5, two parts form the frequency divider and the oscillation stop switch, in the embodiment, ICl and TC9198 are selected, and the frequency divider is a 4-bit programmable frequency divider. By means of 4 BCD dial switches, the frequency dividing ratio can be set arbitrarily between 1 and 9999, the highest working frequency is 30MHz, and the highest working frequency can reach 37MHz practically. The IC2 is a phase-locked loop circuit 74HC4046AE, which has the same function as CD4046, but the working frequency is generally 20MHz, and the power supply voltage is 5V. In the circuit, the lowest working frequency is 70kHz, the circuit can not work normally any more, the highest working frequency is 37MHz, and the working current reaches 40 mA. However, it is noted that the model 74HC4046N is not used, since it is difficult to exceed 30MHz at the highest frequency. The IC 374 HC4060 and the 6.4MHz crystal oscillator form a 10kHz reference frequency source, the frequency dividing ratio of 4060 is 640, and other circuits form a 5-level decimal frequency divider which extends to 0.7Hz through frequency division of the lowest frequency.
It is worth to be noted that, because the frequency range of the phase-locked loop part of the circuit is as wide as 70kHz to 37MHz, the loop has great difficulty in capturing and locking the frequency, and the phenomenon that the frequency division value is changed often occurs, and at this time, the voltage-controlled oscillator cannot work at the highest frequency. Therefore, the circuit is additionally provided with a vibration-stopping switch K. When the frequency needs to be changed, the switch K is closed firstly, the voltage of the ninthly pin of the IC2 is zero, when the voltage-controlled oscillator stops vibrating, the frequency is set, then the switch K is opened, the voltage-controlled oscillator starts vibrating from the lowest end of the frequency, and the work is very reliable. At the same time, the oscillation may also be stopped when no output is needed to reduce the power consumption of the IC274HC 4046. However, the oscillation stop control end of the pin 74HC4046 cannot be used for control, and the oscillation stop control end is used for control in actual measurement, so that the voltage-controlled oscillator still has the phenomenon that the loop cannot be locked and the frequency is the highest frequency.
The TC9198 frequency division ratio can be set by a decimal dial switch or a circuit described in the text, and at the moment, only Ql-Q16 is connected to pins (4) - (19) of the TC 9198.
It is worth to be noted that the above components form the power supply unit, i.e. the crystal oscillator unit, the superposition oscillation stop switch in the core point of the present invention to control the frequency input, and the combined frequency divider can more accurately test the effect of outputting frequencies with different frequency division ratios through the dial switch. When the interval during the off period was 4s, the phase noise at the highest output frequency deviated from the dominant frequency by 1kHz was recorded in table 1,
TABLE 1 phase noise at 4s intervals during off cycle
When the dial switch is driven to determine that the frequency divider after combination is divided by eight, different vibration-off periods are adjusted to obtain the following measurement data, referring to table 2,
TABLE 2 phase noise for a combined divider with eight divisions
It can be known from the type I measurement data and the type II measurement data that the final output oscillation frequency fo is affected by the on-time of the oscillation stop switch regardless of the frequency dividers of different combinations, and the user selects the frequency division ratio as required, and determines the highest working frequency, the wider bandwidth, the smaller step, and the higher phase noise broadband frequency synthesis by controlling the on-time of the oscillation stop switch.
It should be noted that, referring to fig. 2, the circuit further includes a signal conditioning unit, where the signal conditioning unit includes a voltage regulator tube, a sound meter filter and a frequency divider, the voltage regulator tube is sequentially connected to the sound meter filter and the frequency divider, and the signal conditioning unit processes and sends out an input signal, and in the signal conditioning unit, the frequency divider is a fixed eight-frequency divider, and adopts the sound meter filter, and has a sufficiently narrow loop bandwidth, so that the circuit of this embodiment can help the experiment to obtain a better spurious index.
It should be noted that the frequency synthesizer further includes a DDS unit, a frequency-doubled high-frequency signal is generated by the DDS unit, an output end of the DDS unit is connected to the phase-locked loop circuit, an input of the DDS unit is a frequency after frequency division, and a chip selected by the DDS unit is AD 9951.
It is worth noting that the selection of the reference signal frequency is critical. On the one hand, for the phase-locked loop, the higher the phase discrimination frequency is, the better the phase noise of the output radio frequency signal is, and the faster the frequency hopping speed is. On the other hand, the closer the DDS output frequency is to the Nyquist frequency, the fewer the sampling points are, the larger the output stray interference is, so that the lower frequency and the narrower bandwidth are selected as much as possible under the condition of ensuring the design index, and the filtering output by the DDS is also convenient.
It should be noted that, referring to fig. 3, the phase-locked loop circuit mainly multiplies the frequency of the reference signal provided by the DDS to a desired frequency band, and in this embodiment, the phase-locked loop circuit mainly includes a low-noise Phase Frequency Detector (PFD), an accurate charge pump (not shown), a combined frequency divider, a programmable A, B counter, and a dual-mode prescaler, and when the combined frequency divider is divided by 4, then, the reference frequency divider R =2, P =8, and the loop output frequency fo is:
the phase discriminator adopted in the embodiment is ADF4107, which is specially matched with phase discriminators of other models and types on the market in the implementation through testing and has a good noise floor, the in-band phase noise PN of the loop output signal is calculated by the following formula,
wherein f isDThe performance of the phase-locked loop circuit is further judged by comparing the oscillation frequency fo of the frequency hopping output with the output value of the PN.
The DDS chip selects AD9951 of ADI company, its highest clock frequency reaches 400MHz, the phase noise at 1KHz is better than-120 dBc/Hz when the output frequency is 160MHz, because the phase noise and spurious can be worsened 201ogN after the reference signal is frequency-locked and multiplied, if the signal produced by DDS is directly used as the reference phase demodulation, it is difficult to guarantee the index requirement of the phase noise and spurious, here, the DDS output signal is up-converted and then frequency-divided by eight to improve the phase noise and spurious of the reference signal so as to meet the index requirement.
The DDS unit clock is generated by frequency multiplication of a high-stability 60MHz crystal oscillator signal. The frequency multiplication is realized by selecting a single chip amplifier with high gain and low saturation power, and the system clock is 360 MHz. Strictly calculated, the DDS output frequency is 58.88 MHz-64.68 MHz, then is subjected to up-conversion with 360 MHz, and a reference signal fr is obtained after filtering, amplification and eight-frequency division and is 52.36 MHz-53.085 MHz. The local oscillator signal and the radio frequency signal of the frequency mixer are filtered for 2 times, DDS stray and mixing stray are well inhibited, and test results show that the module provides an ideal reference signal for PLL.
The design of the loop filter is the key of the phase-locked loop, and influences spurious suppression, phase noise, loop stability, frequency hopping time and the like of the PLL. In order to obtain a relatively short frequency hopping time, the loop bandwidth must be sufficiently wide; to obtain a good spur indicator, the loop bandwidth must be sufficiently narrow. Therefore, the loop bandwidth is selected to take these criteria into account. The design of the loop filter circuit can be conveniently carried out by using a loop filter simulation tool ADIsimPLL provided by ADI company.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (9)
1. A design method of broadband miniaturization fast frequency synthesis is characterized by comprising the following steps:
step 1: arranging and combining a plurality of programmable frequency dividers, solving frequency division ratio, selecting each combination in sequence for testing, and executing the step 2;
step 2: the testing process comprises the steps of connecting the combination in series to a phase-locked loop circuit, setting an oscillation frequency threshold and a vibration stopping switch, controlling a power supply period through the vibration stopping switch, and executing the step 3;
and step 3: controlling the vibration-stopping switch by starting and stopping to obtain different output vibration frequencies, recording the starting time and the period of each vibration-stopping switch operation, repeatedly testing and recording, eliminating the combination exceeding the vibration frequency threshold value, and executing the step 4;
and 4, step 4: and connecting the combination meeting the oscillation frequency threshold value to a phase-locked loop circuit in series, and connecting the output of the phase-locked loop circuit with an amplification filtering unit to obtain the designed frequency synthesizer.
2. The method of claim 1, wherein the method further comprises: the frequency synthesizer also comprises a power supply unit which supplies power to the frequency synthesizer through the vibration-stopping switch.
3. The method of claim 1, wherein the method further comprises: the frequency synthesizer also comprises a frequency synthesis controller, a control serial port, a DDS unit and a signal conditioning unit, wherein the frequency synthesis controller is respectively connected with the DDS unit and the combined frequency divider through the control serial port, the output end of the oscillation stop switch is connected with the signal conditioning unit, and the reference power is output to the phase-locked loop circuit through the signal conditioning unit.
4. The method of claim 3, wherein the method further comprises: the signal conditioning unit comprises a voltage-stabilizing tube, a sound meter filter and a conditioning frequency divider, wherein the voltage-stabilizing tube is sequentially connected with the sound meter filter and the conditioning frequency divider, and the reference power is output to the phase-locked loop circuit through the conditioning frequency divider.
5. The method of claim 4, wherein the method further comprises: the DDS unit generates a frequency-doubled high-frequency signal, the input end of the DDS unit is the output end of the vibration-stopping switch, and the output end of the DDS unit is connected with the signal conditioning unit.
6. The method of claim 5, wherein the method further comprises: the output end of the vibration-stopping switch is provided with a filtering unit, and the output end of the filtering unit is respectively connected with the DDS unit and the signal conditioning unit.
7. The method of claim 4, wherein the method further comprises: the phase-locked loop circuit further comprises a phase discriminator, a loop filter and a voltage-controlled oscillator, the input end of the combined frequency divider is connected with the voltage-controlled oscillator, the output end of the combined frequency divider is connected with the phase discriminator, and the output end of the conditioning frequency divider is connected with the input end of the phase discriminator.
8. The method of claim 7, wherein the method further comprises: the frequency dividing ratio of the conditioning frequency divider is eight frequency dividing.
9. The method of claim 3, wherein the method further comprises: the DDS unit adopts a chip with the model number AD 9951.
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Application publication date: 20210709 |