CN117081583B - Frequency source for improving phase noise - Google Patents
Frequency source for improving phase noise Download PDFInfo
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- CN117081583B CN117081583B CN202311337428.0A CN202311337428A CN117081583B CN 117081583 B CN117081583 B CN 117081583B CN 202311337428 A CN202311337428 A CN 202311337428A CN 117081583 B CN117081583 B CN 117081583B
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/16—Multiple-frequency-changing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/12—Indirect frequency synthesis using a mixer in the phase-locked loop
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention discloses a frequency source for improving phase noise, which mainly solves the technical problem that the traditional frequency source synthesis scheme cannot achieve miniaturization and fine stepping. The frequency-reducing power divider consists of six power dividers, four phase-locked loops, a frequency-reducing mixing circuit, a frequency multiplier, a band-pass filter and a switch selection filter circuit. Through the design, the invention mixes the signals generated by the 2-frequency digital phase frequency detector plus the VCO phase-locked loop with the main signals, reduces the frequency of the main signals to be within the reference input frequency range of the integer/fractional PLL synthesizer (first phase detector), enters the reference input end of the first phase detector, and generates 1GHz signals to enter the radio frequency input end of the first phase detector by adopting the digital phase frequency detector plus the VCO phase-locked loop. The reference input end and the radio frequency input end of the first phase discriminator are used in opposite directions, so that the frequency multiplication times of the main signal are effectively reduced, and the phase noise of the phase-locked loop is improved; the 1GHz may enable a fine step of the frequency source by the fractional mode of the first phase detector.
Description
Technical Field
The invention relates to the technical field of radar communication, in particular to a frequency source for improving phase noise.
Background
The core component of the system is widely applied to the fields of radar, communication, measurement and control, countermeasure, navigation and the like. With the development of modern electronic technology, the performance of electronic equipment is continuously improved, the functions are continuously increased, and simultaneously, higher requirements are also put on the performance of various aspects of frequency sources. The index of the frequency source mainly comprises: miniaturization, small stepping, high stability, ultra wide band, low phase noise, low stray, low power consumption, agile frequency, quick start, etc. The difficulty is comprehensively considered. Meanwhile, the emphasis on the requirements of various indexes of the frequency source in different application fields is also different, so that the frequency source is often required to combine with the actual application scene in design, and various indexes are selected and balanced.
There are various implementations of the existing frequency source, including a Phase Locked Loop (PLL) type frequency source, a direct frequency synthesis type frequency source, a DDS excitation PLL frequency source, etc. A phase-locked loop (PLL) cannot achieve fine step frequency hopping and has poor phase noise; as shown in fig. 1, a Phase Locked Loop (PLL) frequency source has simple circuitry and good spurious suppression, but poor phase noise. Although the DDS can realize fine step frequency hopping and output phase noise well, the DDS is limited by the working principle of the DDS and cannot output signals with higher frequency and wider frequency band, and due to the nonlinear characteristics of a DAC (digital-to-analog converter) in the DDS, output spurious emissions are also very large, so that the signal quality is affected. The DDS output signal is mixed with the frequency multiplication signal, can output high-frequency signals and has good phase noise, but can not output broadband signals, and the spurious suppression is poor. As shown in fig. 2, the direct frequency synthesis type frequency source has a good phase noise, but is bulky and cannot output a wide frequency band signal.
Disclosure of Invention
The invention aims to provide a frequency source for improving phase noise, which mainly solves the technical problems of miniaturization and fine stepping which cannot be achieved by the traditional frequency source synthesis scheme.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
the frequency source for improving phase noise comprises a first power divider, a second phase-locked loop and a third phase-locked loop, wherein the first power divider divides an input clock signal into two paths, the second power divider is connected with one output end of the first power divider, the second phase-locked loop and the third phase-locked loop are respectively connected with two output ends of the second power divider, the input end of the second phase-locked loop is connected with the output end of the second phase-locked loop, one output end of the second phase-locked loop feeds back a signal to a fifth power divider of the second phase-locked loop, the input end of the second phase-locked loop is connected with the other output end of the fifth power divider, the input end of the second phase-locked loop is connected with the output end of the first phase-locked loop, the first output end of the second phase-locked loop directly outputs a sixth power divider of a signal, the input end of the second phase-locked loop is connected with the output end of the third phase-locked loop, the first output end of the first phase-locked loop feeds back a signal to the third power divider, the second phase-locked loop and the fourth phase-locked loop is connected with the fourth phase-locked loop, the input end of the fourth phase-locked loop is connected with the fourth phase-locked loop, and the fourth phase-locked loop is connected with the fourth phase-locked loop.
Further, in the present invention, the main phase lock loop includes a first phase detector having a radio frequency input end RF connected to one output end of the fifth power divider, a main loop filter having one end connected to a clock signal output end CPo of the first phase detector, and a first voltage controlled oscillator VCO1 having a control end connected to the other end of the main loop filter and an output end connected to an input end of the sixth power divider; the reference input end REFin of the first phase discriminator is connected with the down-conversion mixing circuit;
the main loop filter comprises a first operational amplifier OP1, a resistor R1, a capacitor C2, a resistor R2 and a capacitor C3, wherein the first operational amplifier OP1 is connected with a control voltage Vt at a normal phase input end, the resistor R1 is connected with an inverting input end of the first operational amplifier OP1, the other end of the resistor R1 is connected with a clock signal output end CPo of the first phase detector, the capacitor C1 is connected with the clock signal output end CPo of the first phase detector, the other end of the capacitor C1 is grounded, the capacitor C2 is connected between the inverting input end and the output end of the first operational amplifier OP1, the resistor R2 and the capacitor C3 are connected in parallel with two ends of the capacitor C2 after being connected in series, the resistor R3 is connected with the output end of the first operational amplifier OP1, the other end of the resistor R3 is connected with the control end of the first voltage-controlled oscillator VCO1, and the capacitor C4 is connected with the control end of the first voltage-controlled oscillator VCO1 and the other end of the resistor is grounded.
Further, in the present invention, the second phase-locked loop includes a second phase detector with a reference input terminal REFin connected to one output terminal of the second power divider, a second loop filter with one end connected to NU pin and ND pin of the second phase detector, and a second voltage-controlled oscillator VCO2 with a control terminal connected to the other end of the second loop filter and an output terminal connected to the input terminal of the fifth power divider;
the second loop filter comprises a resistor R6, a capacitor C7, a second operational amplifier OP2, a resistor R5, a resistor R8, a resistor R4, a capacitor C9, and a capacitor C9, wherein the resistor R6 and the capacitor C7 are connected to the ground after the normal phase input end is connected in series, the resistor R5 is connected with the normal phase input end of the second operational amplifier OP2, the resistor C6 is connected with the ND pin of the second operational amplifier and the other end is grounded, the resistor R4 is connected with the inverting input end of the second operational amplifier OP2, the other end is connected with the NU pin of the second operational amplifier, the capacitor C5 is connected with the other end of the second operational amplifier OP2, the resistor R7 and the capacitor C8 are connected between the inverting input end and the output end of the second operational amplifier OP2 after the series, the resistor R8 is connected with the output end of the second operational amplifier OP2, the other end of the resistor R8 is connected with the control end of the second voltage-controlled oscillator VCO2, and the other end of the resistor C9 is grounded.
Further, in the present invention, the third phase-locked loop includes a third phase detector with a reference input terminal REFin connected to the other output terminal of the second power divider, a third loop filter with one end connected to the NU pin and the ND pin of the third phase detector, and a third voltage-controlled oscillator VCO3 with a control terminal connected to the other end of the third loop filter and an output terminal connected to the input terminal of the third power divider;
the third loop filter comprises a third operational amplifier OP3 with a resistor R11 and a capacitor C12 which are connected in series with each other at the positive input end, a resistor R10 with one end connected with the positive input end of the third operational amplifier OP3 and the other end connected with the ND pin of the third phase detector, a resistor R9 with one end connected with the ND pin of the third phase detector and the other end grounded, and one end connected with the inverting input end of the third operational amplifier OP3 and the other end connected with the NU pin of the third phase detector, a capacitor C10 with one end connected with the NU pin of the third phase discriminator and the other end grounded, a resistor R12 and a capacitor C13 which are connected in series between the inverting input end and the output end of the third operational amplifier OP3, a resistor R13 with one end connected with the output end of the third operational amplifier OP3 and the other end connected with the control end of the third voltage-controlled oscillator VCO3, and a capacitor C14 with one end connected with the control end of the third voltage-controlled oscillator VCO3 and the other end grounded.
Further, in the present invention, the fourth phase-locked loop includes a fourth phase detector with a reference input terminal REFin connected to the output terminal of the first band-pass filter, a fourth loop filter with one end connected to the NU pin and the ND pin of the fourth phase detector, and a fourth voltage-controlled oscillator VCO4 with a control terminal connected to the other end of the fourth loop filter and an output terminal connected to the input terminal of the fourth power divider;
the fourth loop filter comprises a resistor R16, a capacitor C17, a resistor R15, a capacitor C16, a resistor C14, a capacitor C15, a capacitor C19, a capacitor C18, a capacitor C17, a resistor C18, a capacitor C4, a resistor C4, a capacitor C4, a resistor C18, a capacitor C4, a capacitor C18, a capacitor C4 and a capacitor C19, wherein the resistor R16 is formed by connecting a normal phase input end with the normal phase input end of the fourth operational amplifier OP4 after being connected in series, the resistor R15 is connected with the ND pin of the fourth operational amplifier OP4, the capacitor C18 is connected with the ND pin of the fourth operational amplifier, the capacitor C14 is connected with the other end of the fourth operational amplifier OP4, the capacitor C19 is connected with the control end of the fourth voltage-controlled oscillator VCO4, and the other end of the capacitor C19 is grounded.
Further, in the present invention, the down-conversion mixer circuit includes a ≡2 frequency divider with an input end connected to one output end of the sixth power divider, a first mixer with a local oscillator input end LO connected to an output end of the ≡2 frequency divider and a radio frequency input end RF connected to the switch selection filter circuit, and a second band-pass filter with an input end connected to an intermediate frequency output end IF of the first mixer; the local oscillator input LO is connected with the output end of the second band-pass filter, the radio frequency input RF is connected with one output end of the third power divider, and the low-pass filter is connected between the intermediate frequency output end IF of the second mixer and the reference input end REFin of the first phase discriminator.
Further, in the present invention, the switch selection filter circuit includes a first single-pole double-throw switch K1, a second single-pole double-throw switch K2, and a second x 2 frequency multiplier and a third band-pass filter, wherein the fixed end of the second single-pole double-throw switch K1 is connected with one output end of the fourth power divider, the fixed end of the second single-pole double-throw switch K2 is connected with the radio frequency input end RF of the first mixer, and one free end of the second single-pole double-throw switch K1 is directly connected with one free end of the second single-pole double-throw switch K2, and the second x 2 frequency multiplier and the third band-pass filter are connected between the other free end of the first single-pole double-throw switch K1 and the other free end of the second single-pole double-throw switch K2 after being connected in series.
Compared with the prior art, the invention has the following beneficial effects:
the invention mixes the signal generated by the 2-order digital phase frequency detector plus the VCO phase-locked loop with the main signal, reduces the frequency of the main signal to the reference input frequency range of the integer/fractional PLL synthesizer (phase detector 1), enters the reference input end of the first phase detector, and generates a 1GHz signal by adopting the digital phase frequency detector plus the VCO phase-locked loop to enter the radio frequency input end of the first phase detector. The reference input end and the radio frequency input end of the first phase discriminator are used in opposite directions, so that the frequency multiplication times of the main signal are effectively reduced, and the phase noise of the phase-locked loop is improved; the 1GHz may enable a fine step of the frequency source by the fractional mode of the first phase detector.
Drawings
Fig. 1 is a schematic diagram of a prior art Phase Locked Loop (PLL) frequency source.
Fig. 2 is a schematic diagram of a prior art direct frequency synthesis type frequency source.
Fig. 3 is a schematic block diagram of a frequency source of the present invention.
Fig. 4 is a schematic circuit diagram of a main phase-locked loop according to the present invention.
Fig. 5 is a schematic circuit diagram of a second phase locked loop according to the present invention.
Fig. 6 is a schematic circuit diagram of a third phase locked loop according to the present invention.
Fig. 7 is a schematic circuit diagram of a fourth pll according to the present invention.
Fig. 8 is a schematic diagram of a down-conversion mixer circuit according to the present invention.
Fig. 9 is a schematic diagram of a switch select filter circuit according to the present invention.
Detailed Description
The invention will be further illustrated by the following description and examples, which include but are not limited to the following examples.
As shown in fig. 3, the frequency source for improving phase noise disclosed by the invention comprises a first power divider which divides an input clock signal into two paths, a second power divider which is connected with one output end of the first power divider, a second phase-locked loop and a third phase-locked loop which are respectively connected with two output ends of the second power divider, a down-conversion mixer circuit which is connected with the output end of the second phase-locked loop and is connected with one output end of the second phase-locked loop in a feedback manner to a fifth power divider of the second phase-locked loop, a sixth power divider which is connected with the other output end of the fifth power divider in a power manner, a input end of the sixth power divider which is connected with the output end of the main phase-locked loop and is connected with one output end of the third phase-locked loop in a direct manner, a down-conversion mixer circuit which is connected with the other output end of the sixth power divider and the other output end of the third power divider and a reference input end ren of the main phase-locked loop in a frequency-conversion mixer circuit, a down-conversion mixer circuit which is connected with the other output end of the fourth phase-locked loop in a frequency-conversion mixer circuit, a frequency-conversion mixer circuit which is connected with the other output end of the fourth phase-locked loop in a frequency-conversion device is connected with the fourth phase-locked loop in a frequency-conversion device, and the fourth phase-locked loop is connected with the output end of the fourth phase-locked loop in a frequency-conversion device.
The first power divider divides the input 100MHz reference clock signal into two paths, one path provides the reference clock signal for the first multiplied by 2 frequency multiplier, and the other path provides the input signal for the second power divider. The first x 2 frequency multiplier multiplies the 100MHz reference clock signal to 200MHz. The first band-pass filter is used for filtering out 200MHz frequency multiplication spurs. The third power divider divides the power of the f 10-f 11 signals into 2 paths, 1 path provides radio frequency input signals for the third phase discriminator, and 1 path provides radio frequency input signals for the second mixer. The fifth power divider divides the power of the 1GHz signal into 2 paths, wherein the 1 path provides the radio frequency input signal for the second phase discriminator, and the 1 path provides the radio frequency input signal for the first phase discriminator. The sixth power divider divides the power of the f 1-f 2 signals into 2 paths, the 1 paths directly output the f 1-f 2 signals to the outside, and the 1 paths provide input signals for the frequency divider 2.
As shown in fig. 4, in this embodiment, the main phase lock loop includes a first phase detector having a radio frequency input end RF connected to one output end of the fifth power divider, a main loop filter having one end connected to a clock signal output end CPo of the first phase detector, and a first voltage controlled oscillator VCO1 having a control end connected to the other end of the main loop filter and an output end connected to an input end of the sixth power divider; the reference input terminal REFin of the first phase detector is connected with the down-conversion mixing circuit. The main phase lock loop is used for generating signals with frequencies f 1-f 2.
The main loop filter comprises a first operational amplifier OP1, a resistor R1, a capacitor C2, a resistor R2 and a capacitor C3, wherein the first operational amplifier OP1 is connected with a control voltage Vt at a normal phase input end, the resistor R1 is connected with an inverting input end of the first operational amplifier OP1, the other end of the resistor R1 is connected with a clock signal output end CPo of the first phase detector, the capacitor C1 is connected with the clock signal output end CPo of the first phase detector, the other end of the capacitor C1 is grounded, the capacitor C2 is connected between the inverting input end and the output end of the first operational amplifier OP1, the resistor R2 and the capacitor C3 are connected in parallel with two ends of the capacitor C2 after being connected in series, the resistor R3 is connected with the output end of the first operational amplifier OP1, the other end of the resistor R3 is connected with the control end of the first voltage-controlled oscillator VCO1, and the capacitor C4 is connected with the control end of the first voltage-controlled oscillator VCO1 and the other end of the resistor is grounded.
As shown in fig. 5, in this embodiment, the second phase-locked loop includes a second phase detector having a reference input terminal REFin connected to one output terminal of the second power divider, a second loop filter having one terminal connected to the NU pin and the ND pin of the second phase detector, and a second voltage-controlled oscillator VCO2 having a control terminal connected to the other terminal of the second loop filter and an output terminal connected to the input terminal of the fifth power divider. The second phase locked loop is used to generate a 1GHz signal.
The second loop filter comprises a resistor R6, a capacitor C7, a second operational amplifier OP2, a resistor R5, a resistor R8, a resistor R4, a capacitor C9, and a capacitor C9, wherein the resistor R6 and the capacitor C7 are connected to the ground after the normal phase input end is connected in series, the resistor R5 is connected with the normal phase input end of the second operational amplifier OP2, the resistor C6 is connected with the ND pin of the second operational amplifier and the other end is grounded, the resistor R4 is connected with the inverting input end of the second operational amplifier OP2, the other end is connected with the NU pin of the second operational amplifier, the capacitor C5 is connected with the other end of the second operational amplifier OP2, the resistor R7 and the capacitor C8 are connected between the inverting input end and the output end of the second operational amplifier OP2 after the series, the resistor R8 is connected with the output end of the second operational amplifier OP2, the other end of the resistor R8 is connected with the control end of the second voltage-controlled oscillator VCO2, and the other end of the resistor C9 is grounded.
As shown in fig. 6, in this embodiment, the third phase locked loop includes a third phase detector having a reference input terminal REFin connected to the other output terminal of the second power divider, a third loop filter having one terminal connected to the NU pin and the ND pin of the third phase detector, and a third voltage controlled oscillator VCO3 having a control terminal connected to the other terminal of the third loop filter and an output terminal connected to the input terminal of the third power divider. The third phase-locked loop is used to generate f 10-f 11 signals stepped by 100 MHz.
The third loop filter comprises a third operational amplifier OP3 with a resistor R11 and a capacitor C12 which are connected in series with each other at the positive input end, a resistor R10 with one end connected with the positive input end of the third operational amplifier OP3 and the other end connected with the ND pin of the third phase detector, a resistor R9 with one end connected with the ND pin of the third phase detector and the other end grounded, and one end connected with the inverting input end of the third operational amplifier OP3 and the other end connected with the NU pin of the third phase detector, a capacitor C10 with one end connected with the NU pin of the third phase discriminator and the other end grounded, a resistor R12 and a capacitor C13 which are connected in series between the inverting input end and the output end of the third operational amplifier OP3, a resistor R13 with one end connected with the output end of the third operational amplifier OP3 and the other end connected with the control end of the third voltage-controlled oscillator VCO3, and a capacitor C14 with one end connected with the control end of the third voltage-controlled oscillator VCO3 and the other end grounded.
As shown in fig. 7, in this embodiment, the fourth phase-locked loop includes a fourth phase detector having a reference input terminal REFin connected to the output terminal of the first band-pass filter, a fourth loop filter having one terminal connected to the NU pin and the ND pin of the fourth phase detector, and a fourth voltage-controlled oscillator VCO4 having a control terminal connected to the other terminal of the fourth loop filter and an output terminal connected to the input terminal of the fourth power divider. The fourth phase-locked loop is used to generate f 7-f 8 signals stepped by 1 GHz.
The fourth loop filter comprises a resistor R16, a capacitor C17, a resistor R15, a capacitor C16, a resistor C14, a capacitor C15, a capacitor C19, a capacitor C18, a capacitor C17, a resistor C18, a capacitor C4, a resistor C4, a capacitor C4, a resistor C18, a capacitor C4, a capacitor C18, a capacitor C4 and a capacitor C19, wherein the resistor R16 is formed by connecting a normal phase input end with the normal phase input end of the fourth operational amplifier OP4 after being connected in series, the resistor R15 is connected with the ND pin of the fourth operational amplifier OP4, the capacitor C18 is connected with the ND pin of the fourth operational amplifier, the capacitor C14 is connected with the other end of the fourth operational amplifier OP4, the capacitor C19 is connected with the control end of the fourth voltage-controlled oscillator VCO4, and the other end of the capacitor C19 is grounded.
As shown in fig. 8, in this embodiment, the down-conversion mixer circuit includes a ≡2 frequency divider with an input terminal connected to one output terminal of the sixth power divider, a first mixer with a local oscillator input terminal LO connected to an output terminal of the ≡2 frequency divider and a radio frequency input terminal RF connected to the switch selection filter circuit, and a second band-pass filter with an input terminal connected to an intermediate frequency output terminal IF of the first mixer; the local oscillator input LO is connected with the output end of the second band-pass filter, the radio frequency input RF is connected with one output end of the third power divider, and the low-pass filter is connected between the intermediate frequency output end IF of the second mixer and the reference input end REFin of the first phase discriminator.
The frequency divider/2 divides the frequency of the f 1-f 2 signals to generate f 3-f 4 signals, and provides local oscillation signals for the first mixer. The first mixer mixes the f 3-f 4 signals with the f 7-f 9 signals, and down-converts the f 3-f 4 signals to f 5-f 6 signals. The second band-pass filter is used for filtering the mixing intermodulation spurs of the f 5-f 6 signals. The second mixer mixes the f 5-f 6 signals with the f 10-f 11 signals, and down-converts the f 5-f 6 signals to the f 12-f 13 signals. The low-pass filter is used for providing a reference clock signal for the first phase detector after filtering the mixing intermodulation spurs of the f 12-f 13 signals.
As shown in fig. 9, in this embodiment, the switch selection filter circuit includes a first single-pole double-throw switch K1 with a fixed end connected to one output end of the fourth power divider, a second single-pole double-throw switch K2 with a fixed end connected to the radio frequency input end RF of the first mixer and a free end directly connected to one free end of the first single-pole double-throw switch K1, and a second x 2 frequency multiplier and a third band-pass filter connected in series between the other free end of the first single-pole double-throw switch K1 and the other free end of the second single-pole double-throw switch K2.
The first single-pole double-throw switch K1 selects 2 paths of f 7-f 8 signals, 1 path is straight-through, and 1 path enters the second multiplied by 2 frequency multiplier. The second x 2 frequency multiplier 2 multiplies the f7 signal to the f9 signal. The third band-pass filter is used for filtering frequency multiplication spurious of f9 signals. The second single-pole double-throw switch K2 combines the f 7-f 8 signals and the f9 signals to output f 7-f 9 signals with the step of 1GHz, and a radio frequency input signal is provided for the first mixer.
When the whole circuit operates, the reference clock signal is divided into two paths by the first power divider, and one path of the reference clock signal is subjected to frequency multiplication by a 2-frequency multiplier and band-pass filtering and then output to 200MHz to provide the reference clock signal for the fourth phase discriminator; the other path continues to divide power by 2 paths through the second power divider, one path provides a reference clock signal for the third phase detector, and the other path provides a reference clock signal for the second phase detector. The fourth phase discriminator adopts a digital phase frequency detector, a fourth loop filter is formed by a capacitor C15, a capacitor C16, a resistor R14, a resistor R15, a resistor R16, a capacitor C17, a resistor R17, a capacitor C18, an operational amplifier OP4, a resistor R18 and a capacitor C19, the VCO4 outputs signals with frequencies f 7-f 8 and steps of 1GHz, the power is divided into 2 paths, one path is used as the loop frequency of the fourth phase discriminator, the other path is selected through the first single-pole double-throw switch K1 to be directly output f 7-f 8, f7 is subjected to frequency multiplication by 2, the third band-pass filter outputs f9, f 7-f 8 and f9 are combined through the second single-pole double-throw switch K2 to output f 7-f 9 and steps of 1GHz, and the signals are used as the radio frequency input frequency of the first mixer. The first phase discriminator adopts an integer/fractional PLL synthesizer, a main loop filter is formed by a capacitor C1, a resistor R1, a capacitor C2, a resistor R2, a capacitor C3, a resistor R3, a capacitor C4 and an operational amplifier OP1, the VCO1 outputs frequencies f 1-f 2, the power is divided into 2 paths, one path directly outputs f 1-f 2 fine stepping signals, the other path generates f 3-f 4 signals through frequency division by 2, the signals are used as LO signals of the first mixer, and the LO signals are mixed with f 7-f 9 to generate f 5-f 6 signals. f5 to f6 are filtered by the second band-pass filter and then serve as the LO signal of the second mixer. The third phase discriminator adopts a digital phase frequency detector, a third loop filter is formed by a capacitor C10, a capacitor C11, a resistor R9, a resistor R10, a resistor R11, a capacitor C12, a resistor R12, a capacitor C13, operational amplifiers OP3, R13 and a capacitor C14, the VCO3 outputs signals with frequencies f 0-f 11 and steps of 100MHz, the power is divided into 2 paths, one path is used as the loop frequency of the third phase discriminator, the other path is used as the radio frequency input frequency of the second mixer and mixed with f 5-f 6 to generate f 12-f 13 signals, and the f 12-f 13 signals are filtered by the low-pass filter and then enter the REFin reference input end of the first phase discriminator. The second phase discriminator adopts a digital phase frequency detector, a second loop filter is formed by a capacitor C5, a capacitor C6, a resistor R4, a resistor R5, a resistor R6, a capacitor C7, a resistor R7, a capacitor C8, an operational amplifier 2, a resistor R8 and a capacitor C9, the VCO2 outputs a signal with the frequency of 1GHz, the power is divided into 2 paths, one path is used as the loop frequency of the second phase discriminator, and the other path is output into the RF radio frequency input end of the first phase discriminator. The frequency source in the invention can realize small stepping of the broadband frequency source and improve the phase noise of the broadband frequency source.
The above embodiment is only one of the preferred embodiments of the present invention, and should not be used to limit the scope of the present invention, but all the insubstantial modifications or color changes made in the main design concept and spirit of the present invention are still consistent with the present invention, and all the technical problems to be solved are included in the scope of the present invention.
Claims (6)
1. The frequency source for raising phase noise is characterized by that it includes first power divider for dividing input clock signal power into two paths, second power divider whose input end is connected with one output end of first power divider, second phase-locked loop and third phase-locked loop respectively connected with two output ends of second power divider, input end and second lockA fifth power divider with output end connected to the output end of the phase-locked loop and one output end feeding back signal to the second phase-locked loop, a main phase-locked loop with input end connected to the other output end of the fifth power divider, a sixth power divider with input end connected to the output end of the main phase-locked loop and one output end directly outputting signal, a third power divider with input end connected to the output end of the third phase-locked loop and one output end feeding back signal to the third phase-locked loop, a down-conversion mixer circuit connected to the other output end of the sixth power divider, the other output end of the third power divider and the reference input end REFin of the main phase-locked loop, a first with input end connected to the other output end of the first power divider2 frequency multiplier, via a first band-pass filter and a first +.>The input end of the fourth phase-locked loop is connected with the output end of the fourth phase-locked loop, one output end feeds back a signal to a fourth power divider of the fourth phase-locked loop, and the switch selection filter circuit is connected with the other output end of the fourth power divider and the down-conversion mixer circuit;
the main phase lock loop comprises a first phase discriminator with a radio frequency input end RF connected with one output end of a fifth power divider, a main loop filter with one end connected with a clock signal output end CPo of the first phase discriminator, and a first voltage-controlled oscillator VCO1 with a control end connected with the other end of the main loop filter and an output end connected with the input end of the sixth power divider; the reference input end REFin of the first phase discriminator is connected with the down-conversion mixing circuit;
the main loop filter comprises a first operational amplifier OP1, a resistor R1, a capacitor C2, a resistor R2 and a capacitor C3, wherein the first operational amplifier OP1 is connected with a control voltage Vt at a normal phase input end, the resistor R1 is connected with an inverting input end of the first operational amplifier OP1, the other end of the resistor R1 is connected with a clock signal output end CPo of the first phase detector, the capacitor C1 is connected with the clock signal output end CPo of the first phase detector, the other end of the capacitor C1 is grounded, the capacitor C2 is connected between the inverting input end and the output end of the first operational amplifier OP1, the resistor R2 and the capacitor C3 are connected in parallel with two ends of the capacitor C2 after being connected in series, the resistor R3 is connected with the output end of the first operational amplifier OP1, the other end of the resistor R3 is connected with the control end of the first voltage-controlled oscillator VCO1, and the capacitor C4 is connected with the control end of the first voltage-controlled oscillator VCO1 and the other end of the resistor is grounded.
2. A frequency source for increasing phase noise according to claim 1, characterized in that the second phase locked loop comprises a second phase detector having a reference input REFin connected to one output of the second power divider, a second loop filter having one end connected to the NU pin, ND pin of the second phase detector, and a second voltage controlled oscillator VCO2 having a control end connected to the other end of the second loop filter and an output end connected to the input of the fifth power divider;
the second loop filter comprises a resistor R6, a capacitor C7, a second operational amplifier OP2, a resistor R5, a resistor R8, a resistor R4, a capacitor C9, and a capacitor C9, wherein the resistor R6 and the capacitor C7 are connected to the ground after the normal phase input end is connected in series, the resistor R5 is connected with the normal phase input end of the second operational amplifier OP2, the resistor C6 is connected with the ND pin of the second operational amplifier and the other end is grounded, the resistor R4 is connected with the inverting input end of the second operational amplifier OP2, the other end is connected with the NU pin of the second operational amplifier, the capacitor C5 is connected with the other end of the second operational amplifier OP2, the resistor R7 and the capacitor C8 are connected between the inverting input end and the output end of the second operational amplifier OP2 after the series, the resistor R8 is connected with the output end of the second operational amplifier OP2, the other end of the resistor R8 is connected with the control end of the second voltage-controlled oscillator VCO2, and the other end of the resistor C9 is grounded.
3. A frequency source for increasing phase noise according to claim 2, characterized in that the third phase locked loop comprises a third phase detector having a reference input REFin connected to the other output of the second power divider, a third loop filter having one end connected to the NU pin, ND pin of the third phase detector, and a third voltage controlled oscillator VCO3 having a control end connected to the other end of the third loop filter and an output end connected to the input of the third power divider;
the third loop filter comprises a third operational amplifier OP3 with a resistor R11 and a capacitor C12 which are connected in series with each other at the positive input end, a resistor R10 with one end connected with the positive input end of the third operational amplifier OP3 and the other end connected with the ND pin of the third phase detector, a resistor R9 with one end connected with the ND pin of the third phase detector and the other end grounded, and one end connected with the inverting input end of the third operational amplifier OP3 and the other end connected with the NU pin of the third phase detector, a capacitor C10 with one end connected with the NU pin of the third phase discriminator and the other end grounded, a resistor R12 and a capacitor C13 which are connected in series between the inverting input end and the output end of the third operational amplifier OP3, a resistor R13 with one end connected with the output end of the third operational amplifier OP3 and the other end connected with the control end of the third voltage-controlled oscillator VCO3, and a capacitor C14 with one end connected with the control end of the third voltage-controlled oscillator VCO3 and the other end grounded.
4. A frequency source for increasing phase noise according to claim 3, characterized in that the fourth phase locked loop comprises a fourth phase detector having a reference input REFin connected to the output of the first band pass filter, a fourth loop filter having one end connected to the NU pin, ND pin of the fourth phase detector, and a fourth voltage controlled oscillator VCO4 having a control end connected to the other end of the fourth loop filter and an output end connected to the input of the fourth power divider;
the fourth loop filter comprises a resistor R16, a capacitor C17, a resistor R15, a capacitor C16, a resistor C14, a capacitor C15, a capacitor C19, a capacitor C18, a capacitor C17, a resistor C18, a capacitor C4, a resistor C4, a capacitor C4, a resistor C18, a capacitor C4, a capacitor C18, a capacitor C4 and a capacitor C19, wherein the resistor R16 is formed by connecting a normal phase input end with the normal phase input end of the fourth operational amplifier OP4 after being connected in series, the resistor R15 is connected with the ND pin of the fourth operational amplifier OP4, the capacitor C18 is connected with the ND pin of the fourth operational amplifier, the capacitor C14 is connected with the other end of the fourth operational amplifier OP4, the capacitor C19 is connected with the control end of the fourth voltage-controlled oscillator VCO4, and the other end of the capacitor C19 is grounded.
5. The phase noise enhancing frequency source of claim 4 wherein said down-mixing circuit comprises an input connected to an output of a sixth power dividerFrequency divider 2, local oscillator input LO and +.>The output end of the frequency divider 2 is connected with the first mixer, the radio frequency input end RF of the first mixer is connected with the switch selection filter circuit, and the input end of the first mixer is connected with the intermediate frequency output end IF of the first mixer; the local oscillator input LO is connected with the output end of the second band-pass filter, the radio frequency input RF is connected with one output end of the third power divider, and the low-pass filter is connected between the intermediate frequency output end IF of the second mixer and the reference input end REFin of the first phase discriminator.
6. The phase noise increasing frequency source according to claim 5, wherein the switch selection filter circuit comprises a first single-pole double-throw switch K1 having a fixed end connected to one output terminal of the fourth power divider, a second single-pole double-throw switch K2 having a fixed end connected to the RF input terminal RF of the first mixer and a free end directly connected to one free end of the first single-pole double-throw switch K1, and a second single-pole double-throw switch K2 connected in series between the other free end of the first single-pole double-throw switch K1 and the other free end of the second single-pole double-throw switch K22 frequency multiplier, third band-pass filter.
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