CN209120163U - A kind of energy conservation phaselocked loop frequency demultiplier - Google Patents
A kind of energy conservation phaselocked loop frequency demultiplier Download PDFInfo
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- CN209120163U CN209120163U CN201821680521.6U CN201821680521U CN209120163U CN 209120163 U CN209120163 U CN 209120163U CN 201821680521 U CN201821680521 U CN 201821680521U CN 209120163 U CN209120163 U CN 209120163U
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- phaselocked loop
- frequency
- chip
- input terminal
- energy conservation
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Abstract
The utility model relates to a kind of energy saving phaselocked loop frequency demultipliers, the phaselocked loop integrated chip being integrated including the two paths of signals input terminal, radio frequency amplifying circuit sum aggregate power splitter, frequency mixer, oscillator and the intermediate frequency amplifier that are sequentially connected electrically, the output end of DC-DC decompression chip and the output end of several signal ports is also respectively connected in the phaselocked loop integrated chip, and the input terminal of several signal ports is connect with the input terminal of DC-DC decompression chip respectively.Vertical polarization signal and horizontal polarization signals are converted to four road IF output signals to signal port by phaselocked loop integrated chip by the utility model, the voltage signal of signal port input is depressured chip by DC-DC and is depressured, and operating voltage is provided for phaselocked loop integrated chip, the energy consumption of product reduces, and than original product power saving 70% or so, noise coefficient is substantially reduced, flat gain, performance is more stable, and number of users also increases, and is allowed to meet the needs of client.
Description
Technical field
The utility model relates to the technical field of satellite communication, especially a kind of energy saving phaselocked loop frequency demultiplier.
Background technique
Existing frequency demultiplier product can generally make two users while use, and not interfere with each other, and still, there are users
Less, the high disadvantage of energy consumption.As modern electronic technology makes rapid progress, people constantly improve life requirement, and existing product is
It is not able to satisfy the demand of people, the frequency range of satellite-signal is more and more valuable, it is desirable that frequency range utilization rate is higher and higher, needs a kind of property
Energy is more preferable, cost is lower, is met the needs of users using the more products of number of users.
Utility model content
The purpose of the utility model is to provide a kind of energy saving phaselocked loop frequency demultiplier, solve existing frequency demultiplier there are users it is few,
The high technical problem of energy consumption.
The technical scheme adopted by the utility model to solve the technical problem is as follows:
A kind of energy conservation phaselocked loop frequency demultiplier, including be sequentially connected electrically two paths of signals input terminal, radio frequency amplifying circuit sum aggregate
The phaselocked loop integrated chip that power splitter, frequency mixer, oscillator and intermediate frequency amplifier are integrated, the phaselocked loop integrated chip are also divided
Be not connected with DC-DC decompression chip output end and several signal ports output end, several signal ports it is defeated
Enter end to connect with the input terminal of DC-DC decompression chip respectively.
It further, further include reference frequency crystal oscillator, the reference frequency crystal oscillator is connect with phaselocked loop integrated chip.
It further, further include diode, the diode has several, the input terminal of each diode and a signal port
It is correspondingly connected with, the output end of each diode is connect with DC-DC decompression chip.
It further, further include bandpass filter, the input terminal of the bandpass filter is connect with radio frequency amplifying circuit, described
The output end of bandpass filter is connect with phaselocked loop integrated chip.
Further, the radio frequency amplifying circuit includes first order radio frequency amplifying circuit and second level radio frequency amplifying circuit.
Further, the first order radio frequency amplifying circuit includes first order horizontal amplifier and first order vertical amplifier.
Further, the second level radio frequency amplifying circuit includes second level horizontal amplifier and second level vertical amplifier.
The beneficial effects of the utility model are: the utility model is by phaselocked loop integrated chip vertical polarization signal and water
Flat polarized signal is converted to four road IF output signals to signal port, and the voltage signal of signal port input is dropped by DC-DC
Pressure chip is depressured, and provides operating voltage for phaselocked loop integrated chip, and the energy consumption of product reduces, than original product power saving
70% or so, noise coefficient is substantially reduced, and flat gain, performance is more stable, and number of users also increases, and is allowed to meet client
Demand.
Detailed description of the invention
Specific embodiment of the present utility model is further described with reference to the accompanying drawing:
Fig. 1 is the schematic diagram of the utility model preferred embodiment.
Specific embodiment
In order to make those skilled in the art better understand the scheme of the utility model, practical to this below in conjunction with attached drawing
Technical solution in new embodiment is clearly and completely described, it is clear that described embodiment is only the utility model
The embodiment of a part, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
The model of the utility model protection all should belong in the every other embodiment obtained without creative efforts
It encloses.
Referring to Fig.1, a kind of energy saving phaselocked loop frequency demultiplier of the present embodiment, including the horizontal polarization signals H being sequentially connected electrically
Amplify with vertical polarization signal V two paths of signals input terminal, 1 sum aggregate power splitter of radio frequency amplifying circuit, frequency mixer, oscillator and intermediate frequency
The output of DC-DC decompression chip 6 is also respectively connected in the phaselocked loop integrated chip 3 that device is integrated, the phaselocked loop integrated chip 3
The output end at end and several signal ports, the input terminal of several signal ports are depressured chip 6 with the DC-DC respectively
Input terminal connection.For amplifying to two paths of signals, the phaselocked loop integrated chip 3 is used for the radio frequency amplifying circuit 1
Two paths of signals is converted into four road signals, four road signal includes two-way horizontal polarization signals and two-way vertical polarization signal,
Four signal ports are not interfere with each other mutually, can be given four users while be used, meet the needs of users.The DC-DC decompression
The voltage signal that chip 6 inputs signal port is depressured, and provides operating voltage for phaselocked loop integrated chip 3, makes product
Energy consumption substantially reduce, save power saving, and make each signal gain flat stable.
The energy conservation phaselocked loop frequency demultiplier further includes reference frequency crystal oscillator 5, and the reference frequency crystal oscillator 5 and phaselocked loop are integrated
Chip 3 connects, and the reference frequency crystal oscillator 5 makes frequency stabilization, and the reference frequency crystal oscillator 3 uses frequency for the patch of 25MHz
Crystal oscillator.
The energy conservation phaselocked loop frequency demultiplier further includes diode 4, and there are four the diodes 4, the input of each diode 4
End is correspondingly connected with a signal port, and the output end of each diode 4 is connect with DC-DC decompression chip 6, the diode 4
It is corresponded with signal port, the diode 4 is used as the control switch of signal port.
The phaselocked loop integrated chip 3 plays power splitter, frequency mixer, oscillation using the integrated chip of model RT346M
The effect of device and intermediate frequency amplifier.The DC-DC decompression chip 6 plays decompression using the integrated chip of model RT8259
Effect.The quantity of the signal port can be adjusted according to user demand, correspondingly the model to phaselocked loop integrated chip 3 or
Quantity is adjusted can be realized and gives multiple users while using.
The energy conservation phaselocked loop frequency demultiplier further includes bandpass filter 2, and the input terminal of the bandpass filter 2 is put with radio frequency
Big circuit 1 connects, and the output end of the bandpass filter 2 is connect with phaselocked loop integrated chip 3, and Ku input signal is filtered by band logical
Frequency is all fallen in Ku frequency range (950-2150M) range after wave device 2, and frequency demultiplier is made to accord with set-top box decoded frequency band.The band
The frequency values of bandpass filter 2 can be reset, so that product is generally applicable.
The radio frequency amplifying circuit 1 includes first order radio frequency amplifying circuit 11 and second level radio frequency amplifying circuit 12, described
First order radio frequency amplifying circuit 11 includes first order horizontal amplifier and first order vertical amplifier, the second level radio frequency amplification
Circuit 12 includes second level horizontal amplifier and second level vertical amplifier.The first order horizontal amplifier and the second level are horizontal
Amplifier is all made of the amplifier of model NE3512, and the first order vertical amplifier and second level vertical amplifier are all made of
The amplifier of model NE3503.
In conclusion above embodiments are only to illustrate the technical solution of the utility model, rather than its limitations；Although ginseng
The utility model is described in detail according to previous embodiment, those skilled in the art should understand that；It is still
It can modify the technical solutions described in the foregoing embodiments, or equally be replaced to being wherein no lack of technical characteristic
It changes, and these are modified or replaceed, the utility model embodiment technical solution that it does not separate the essence of the corresponding technical solution
Spirit and scope.
Claims (7)
1. a kind of energy conservation phaselocked loop frequency demultiplier, it is characterised in that: two paths of signals input terminal, radio frequency including being sequentially connected electrically amplify
The phaselocked loop integrated chip (3) that circuit (1) sum aggregate power splitter, frequency mixer, oscillator and intermediate frequency amplifier are integrated, the locking phase
The output end of DC-DC decompression chip (6) and the output end of several signal ports, institute is also respectively connected in ring integrated chip (3)
The input terminal for stating several signal ports is connect with the input terminal of DC-DC decompression chip (6) respectively.
2. energy conservation phaselocked loop frequency demultiplier according to claim 1, it is characterised in that: further include reference frequency crystal oscillator (5), institute
Reference frequency crystal oscillator (5) is stated to connect with phaselocked loop integrated chip (3).
3. energy conservation phaselocked loop frequency demultiplier according to claim 1 or 2, it is characterised in that: it further include diode (4), it is described
Diode (4) has several, and the input terminal of each diode (4) is correspondingly connected with a signal port, each diode (4) it is defeated
Outlet is connect with DC-DC decompression chip (6).
4. energy conservation phaselocked loop frequency demultiplier according to claim 1, it is characterised in that: it further include bandpass filter (2), it is described
The input terminal of bandpass filter (2) is connect with radio frequency amplifying circuit (1), the output end and phaselocked loop of the bandpass filter (2)
Integrated chip (3) connection.
5. energy conservation phaselocked loop frequency demultiplier according to claim 1, it is characterised in that: the radio frequency amplifying circuit (1) includes
First order radio frequency amplifying circuit (11) and second level radio frequency amplifying circuit (12).
6. energy conservation phaselocked loop frequency demultiplier according to claim 5, it is characterised in that: the first order radio frequency amplifying circuit
It (11) include first order horizontal amplifier and first order vertical amplifier.
7. energy conservation phaselocked loop frequency demultiplier according to claim 5, it is characterised in that: the second level radio frequency amplifying circuit
It (12) include second level horizontal amplifier and second level vertical amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821680521.6U CN209120163U (en) | 2018-10-17 | 2018-10-17 | A kind of energy conservation phaselocked loop frequency demultiplier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821680521.6U CN209120163U (en) | 2018-10-17 | 2018-10-17 | A kind of energy conservation phaselocked loop frequency demultiplier |
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| Publication Number | Publication Date |
|---|---|
| CN209120163U true CN209120163U (en) | 2019-07-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821680521.6U Active CN209120163U (en) | 2018-10-17 | 2018-10-17 | A kind of energy conservation phaselocked loop frequency demultiplier |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117081583A (en) * | 2023-10-17 | 2023-11-17 | 成都世源频控技术股份有限公司 | Frequency source for improving phase noise |
-
2018
- 2018-10-17 CN CN201821680521.6U patent/CN209120163U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117081583A (en) * | 2023-10-17 | 2023-11-17 | 成都世源频控技术股份有限公司 | Frequency source for improving phase noise |
| CN117081583B (en) * | 2023-10-17 | 2024-02-13 | 成都世源频控技术股份有限公司 | Frequency source for improving phase noise |
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