CN213186294U - Built-in UHF frequency reduction circuit and frequency reducer - Google Patents
Built-in UHF frequency reduction circuit and frequency reducer Download PDFInfo
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- CN213186294U CN213186294U CN202022176262.7U CN202022176262U CN213186294U CN 213186294 U CN213186294 U CN 213186294U CN 202022176262 U CN202022176262 U CN 202022176262U CN 213186294 U CN213186294 U CN 213186294U
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Abstract
The utility model discloses a built-in UHF frequency reduction circuit and frequency demultiplier, including satellite signal receiving circuit, ground wave signal receiving circuit and signal output interface, wherein, satellite signal receiving circuit includes one-level amplifier I, one-level amplifier II, second grade amplifier I, band-pass microstrip filter, phase locking ware and frequency selection circuit I, and ground wave signal receiving circuit includes one-level amplifier III, second grade amplifier II and frequency selection circuit II, and the signal output interface is connected with frequency selection circuit I's output and frequency selection circuit II's output respectively. The utility model discloses a satellite television signal and ground wave television signal can be received to the circuit, need not additionally to increase the UHF amplifier, facilitates the use, and ground antenna connects one-level amplifier III and second grade amplifier II, is favorable to improving the amplified strength of ground signal.
Description
Technical Field
The utility model relates to a frequency demultiplier technical field, in particular to built-in UHF frequency reduction circuit and frequency demultiplier.
Background
With the development of technology and the improvement of living standard, televisions have been popularized worldwide, and with the development of communication technology, the proportion of households that watch satellite televisions in households with televisions is higher, and a frequency demultiplier is one of necessary devices for watching satellite televisions. However, the conventional down converter has only a function of receiving a satellite signal. In fact, in addition to television programs and broadcast programs viewed by satellite signals, television programs and broadcast programs may be viewed by terrestrial wave signals. Terrestrial signals are abundant, and there are many countries and regions that transmit signals of television programs and radio programs in UHF (ultra high frequency) and VHF (very high frequency) bandwidths. When the conventional frequency demultiplier is used for receiving satellite television signals, if the conventional frequency demultiplier is required to receive terrestrial television signals and broadcast signals again, equipment such as an amplifier, a switching converter and the like of UHF or VHF is required to be additionally arranged, so that the use is inconvenient and the cost is high.
SUMMERY OF THE UTILITY MODEL
The utility model discloses aim at solving one of the technical problem that exists among the prior art at least. Therefore, the utility model provides a built-in UHF frequency reduction circuit and frequency demultiplier can receive satellite television signal and ground wave television signal.
On the first hand, the built-in UHF frequency reducing circuit according to the embodiment of the present invention comprises a first-stage amplifier I, wherein the input end is used for connecting a horizontal polarization antenna; the input end of the first-stage amplifier II is connected with the vertical polarization antenna; the input end of the second-stage amplifier I is respectively connected with the output end of the first-stage amplifier I and the output end of the first-stage amplifier II; the input end of the band-pass microstrip filter is connected with the output end of the secondary amplifier I; the input end of the phase locking device is connected with the output end of the band-pass microstrip filter; the input end of the frequency selection circuit I is connected with the output end of the phase locker; the input end of the first-stage amplifier III is connected with a ground antenna; the input end of the second-stage amplifier II is connected with the output end of the first-stage amplifier III; the input end of the frequency selecting circuit II is connected with the output end of the secondary amplifier II; and the signal output interface is respectively connected with the output end of the frequency selecting circuit I and the output end of the frequency selecting circuit II.
According to the utility model discloses built-in UHF frequency reduction circuit has following beneficial effect at least:
the utility model discloses a satellite television signal and ground wave television signal can be received to the circuit, need not additionally to increase the UHF amplifier, facilitates the use, and ground antenna connects one-level amplifier III and second grade amplifier II, is favorable to improving the amplified strength of ground signal.
According to some embodiments of the utility model, one-level amplifier I with one-level amplifier II equally divide and do not include the MOS pipe, the grid of MOS pipe is connected with first current-limiting resistor, and passes through first current-limiting resistor with the first power output end of phase-locked ware is connected, first current-limiting resistor still is connected with first filter capacitor, and passes through first filter capacitor ground connection, the source electrode ground connection of MOS pipe, the drain electrode of MOS pipe with the second power output end of phase-locked ware is connected, the MOS pipe is connected with second filter capacitor, and passes through second filter capacitor ground connection, the drain electrode of MOS pipe still with second-level amplifier I connects.
According to the utility model discloses a some embodiments, the grid of MOS pipe with first microstrip inductance has concatenated between the first current-limiting resistor, the drain electrode of MOS pipe with second microstrip inductance has concatenated between the second power supply output of phase-locked ware.
According to some embodiments of the utility model, second grade amplifier I's input is connected with the microstrip duplexer, and passes through the microstrip duplexer respectively with first grade list ware I with first grade amplifier II connects.
According to some embodiments of the present invention, a ceramic filter is connected in series between the phase locker and the frequency selective circuit I.
According to some embodiments of the utility model, first-order amplifier III with second-order amplifier II equally divides do not include the triode, the base of triode is connected with first coupling electric capacity to be connected with preceding stage circuit through first coupling electric capacity, the base of triode still is connected with second current-limiting resistance, and passes through second current-limiting resistance is connected with operating voltage, the projecting pole ground connection of triode, the collecting electrode of triode is connected with third microstrip inductance, and passes through third current-limiting resistance is connected to third microstrip inductance, third current-limiting resistance with operating voltage connects, the collecting electrode of triode still is connected with second coupling electric capacity, and passes through second coupling electric capacity and back stage circuit are connected.
According to some embodiments of the present invention, a potentiometer is connected between the first-stage amplifier III and the second-stage amplifier II.
According to some embodiments of the present invention, the frequency selecting circuit II includes an inductor L2 and a series connection of a capacitor C22, a capacitor C24, a capacitor C23, a capacitor C28 and a capacitor C27, the inductor L2 is connected in parallel to two ends of the capacitor C28, the capacitor C24 and two ends of the capacitor C27 are respectively connected in parallel to a fourth microstrip inductor L17 and a fifth microstrip inductor L18.
According to the utility model discloses a some embodiments, built-in UHF frequency reduction circuit still includes voltage stabilizing circuit, voltage stabilizing circuit's input is connected with magnetic core inductance L1, and passes through magnetic core inductance L1 with signal output interface connection, voltage stabilizing circuit's output respectively with phase-locked loop ware one-level amplifier III with secondary amplifier II connects.
In a second aspect, the internal UHF down converter according to the present invention includes the above-mentioned internal UHF down conversion circuit.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic block diagram of a built-in UHF down conversion circuit according to an embodiment of the present invention;
fig. 2 is a schematic circuit diagram of the internal UHF down conversion circuit according to the embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present invention, and should not be construed as limiting the present invention.
In the description of the present invention, a plurality of means are one or more, a plurality of means are two or more, and the terms greater than, less than, exceeding, etc. are understood as not including the number, and the terms greater than, less than, within, etc. are understood as including the number. If there is a description of the first, second, I, II, III for the purpose of distinguishing technical features only, it is not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present invention, unless there is an explicit limitation, the words such as setting, installation, connection, etc. should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above words in combination with the specific contents of the technical solution.
Referring to fig. 1, the present embodiment discloses a built-in UHF down-conversion circuit, which includes a satellite signal receiving circuit, a ground wave signal receiving circuit and a signal output interface 300, wherein the satellite signal receiving circuit includes a first-stage amplifier I110, a first-stage amplifier II 120, a second-stage amplifier I130, a band-pass microstrip filter 140, a phase-lock 150 and a frequency selecting circuit I160, an input end of the first-stage amplifier I110 is connected to a horizontally polarized antenna 111, an input end of the first-stage amplifier II 120 is connected to a vertically polarized antenna 112, an input end of the second-stage amplifier I130 is connected to an output end of the first-stage amplifier I110 and an output end of the first-stage amplifier II 120, an input end of the band-pass microstrip filter 140 is connected to an output end of the second-stage amplifier I130, an input end, the input end of the frequency selection circuit I160 is connected with the output end of the phase lock 150; the ground wave signal receiving circuit comprises a primary amplifier III 210, a secondary amplifier II220 and a frequency selecting circuit II 230, wherein the input end of the primary amplifier III 210 is connected with the ground antenna 211, the input end of the secondary amplifier II220 is connected with the output end of the primary amplifier III 210, and the input end of the frequency selecting circuit II 230 is connected with the output end of the secondary amplifier II 220; the signal output interface 300 is respectively connected with the output end of the frequency selecting circuit I160 and the output end of the frequency selecting circuit II 230.
The first-stage amplifier I110 and the first-stage amplifier II 120 respectively receive satellite television signals through the horizontal polarization antenna 111 and the vertical polarization antenna 112, and can switch between the horizontal polarization mode and the vertical polarization mode according to actual requirements, the first-stage amplifier III 210 receives ground wave television signals, such as UHF band signals, through the ground antenna 211, and can be replaced between the satellite television signals and the ground wave television signals according to actual application requirements, thereby greatly enriching television programs and broadcast programs, the frequency reducing circuit of the embodiment does not need to additionally increase a UHF amplifier, is convenient to use, and can avoid the problems of complicated installation, mismatching of equipment and accessories, and the like caused by different specifications, qualities and amplification factors of accessories of external UHF amplifiers on the market, and is beneficial to improving user experience, the ground antenna 211 of the embodiment is connected with the first-stage amplifier III 210 and the second-stage amplifier II220, the maximum amplification can be 30dB, the high-intensity amplification performance is realized, and the ground signal amplification intensity is favorably improved.
Referring to fig. 2, in some embodiments, each of the first-stage amplifier I110 and the first-stage amplifier II 120 includes a MOS transistor, such as a MOS transistor Q1 and a MOS transistor Q2, a gate of the MOS transistor is connected to a first current-limiting resistor, such as a resistor R2 and a resistor R1, and is connected to the first power supply output terminal of the phase-lock circuit 150 through the first current-limiting resistor, the first current-limiting resistor is further connected to a first filter capacitor, such as a capacitor C2 and a capacitor C1, and is grounded through the first filter capacitor, a source of the MOS transistor is grounded, a drain of the MOS transistor is connected to the second power supply output terminal of the phase-lock circuit 150, the MOS transistor is connected to a second filter capacitor, such as a capacitor C3 and a capacitor C6, and is grounded through the second filter capacitor, and a drain of the MOS transistor is further connected to the. In this embodiment, the gate and drain voltages of the MOS transistor are both level-controlled by the phase-locked loop 150, which is beneficial to adjusting the powers of the first-stage amplifier I110 and the first-stage amplifier II 120, thereby reducing the power consumption of the down-converter and the down-converter, and also reducing the signal crosstalk between the first-stage amplifier I110 and the first-stage amplifier II 120, thereby improving the isolation between horizontal polarization and vertical polarization.
Referring to fig. 2, in order to improve the anti-interference capability of the circuit, a first microstrip inductor, such as an inductor L11 and an inductor L12, is connected in series between the gate of the MOS transistor and the first current-limiting resistor, and a second microstrip inductor, such as an inductor L13 and an inductor L14, is connected in series between the drain of the MOS transistor and the second power supply output terminal of the phase locker 150, and the first microstrip inductor and the second microstrip inductor can reduce the influence of the interference signal on the MOS transistor, which is beneficial to improving the stability of the first-stage amplifier I110 and the first-stage amplifier II 120.
Referring to fig. 2, the input end of the second-stage amplifier I130 is connected to a microstrip duplexer 131, and is connected to the first-stage amplifier I and the first-stage amplifier II 120 through the microstrip duplexer 131, the satellite television signal is amplified by the first-stage amplifier I110 or the first-stage amplifier II 120 and then transmitted to the microstrip duplexer 131, and the microstrip duplexer 131 integrates the horizontally polarized signal and the vertically polarized signal, and outputs the integrated horizontally polarized signal to the second-stage amplifier I130 for secondary amplification. The microstrip duplexer 131 can be realized by wiring a circuit board, so that the cost of components and the wiring space can be saved, and the cost and the design difficulty can be reduced.
Referring to fig. 2, a ceramic filter 161 is connected in series between the phase lock 150 and the frequency selecting circuit I160. The radio frequency transmission end of the embodiment adopts the band-pass microstrip filter 140, and the intermediate frequency output end adopts the ceramic filter 161, so that interference signals of partial wave bands, such as 5G signals, can be filtered, and the anti-interference capability of the circuit can be improved.
Referring to fig. 2, in some embodiments, each of the first-stage amplifier III 210 and the second-stage amplifier II220 includes a transistor, such as a transistor Q5 and a transistor Q4, a base of the transistor is connected to a first coupling capacitor, such as a capacitor C25 and a capacitor C26, and is connected to the front-stage circuit through the first coupling capacitor, a base of the transistor is further connected to a second current-limiting resistor, such as a resistor R12 and a resistor R11, and is connected to the operating voltage through the second current-limiting resistor, the operating voltage is provided by the regulator IC2, an emitter of the transistor is grounded, a collector of the transistor is connected to a third microstrip inductor, such as an inductor L15 and an inductor L16, and is connected to a third current-limiting resistor, such as a resistor R9 and a resistor R10, the third current-limiting resistor is connected to the operating voltage, a collector of the transistor is further connected to a second coupling capacitor, such as a capacitor C, and is connected with the rear stage circuit through a second coupling capacitor. The first coupling capacitor and the second coupling capacitor can filter direct current interference signals in the circuit, and the third microstrip inductor can filter interference of input alternating current components on the collector electrode of the triode, so that the interference resistance and stability of the circuit are improved.
In the practical use process, because the external amplifier needs to select the external amplifier with different amplification ratios according to the factors such as user side distribution, cable signal loss and the like, for a user without professional knowledge, the difficulty of replacing the external amplifier is very high, in the embodiment, the potentiometer 221 is connected between the first-stage amplifier III 210 and the second-stage amplifier II220, the intensity of the output signal can be flexibly adjusted according to different signal environments, and the amplification saturation phenomenon can be avoided and the required amplification power can be ensured.
Referring to fig. 2, the frequency selecting circuit II 230 includes an inductor L2, and a capacitor C22, a capacitor C24, a capacitor C23, a capacitor C28, and a capacitor C27 connected in series, wherein the inductor L2 is connected in parallel to two ends of the capacitor C28, and two ends of the capacitor C24 and two ends of the capacitor C27 are respectively connected in parallel to a fourth microstrip inductor L17 and a fifth microstrip inductor L18. The parameters of the capacitor and the inductor are adjusted according to different application requirements, the frequency of the output signal of the frequency selecting circuit II 230 can be adjusted, and the flexibility of the use of the frequency reducing circuit is improved.
Referring to fig. 2, the internal UHF down-conversion circuit further includes a voltage stabilizing circuit 400, an input end of the voltage stabilizing circuit 400 is connected to a magnetic core inductor L1 and is connected to the signal output interface 300 through a magnetic core inductor L1, and an output end of the voltage stabilizing circuit 400 is connected to the phase-locked loop 150, the first-stage amplifier III 210, and the second-stage amplifier II220, respectively. The magnetic core inductor L1 can isolate the satellite television signal and the ground wave television signal, thereby avoiding signal crosstalk and being beneficial to improving the isolation of the signals, and the magnetic core inductor L1 can also reduce the influence of the satellite television signal and the ground wave television signal on the voltage stabilizing circuit 400, reduce interference signals and be beneficial to improving the stability of the working voltage.
The embodiment of the utility model provides a still disclose a built-in UHF frequency demultiplier, including foretell built-in UHF frequency demultiplier circuit, can receive satellite television signal and ground wave television signal, need not additionally to increase the UHF amplifier, facilitate the use, and ground antenna 211 connects one-level amplifier III 210 and second grade amplifier II220, is favorable to improving ground signal's amplification intensity.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention within the knowledge of those skilled in the art.
Claims (10)
1. A built-in UHF down conversion circuit, comprising:
a first-stage amplifier I (110), the input end of which is used for connecting a horizontal polarization antenna (111);
a first-stage amplifier II (120), the input end of which is used for connecting a vertical polarization antenna (112);
the input end of the secondary amplifier I (130) is respectively connected with the output end of the primary amplifier I (110) and the output end of the primary amplifier II (120);
a band-pass microstrip filter (140), the input end of which is connected with the output end of the second-stage amplifier I (130);
the input end of the phase lock device (150) is connected with the output end of the band-pass microstrip filter (140);
the input end of the frequency selection circuit I (160) is connected with the output end of the phase lock (150);
a primary amplifier III (210), the input end of which is used for connecting a ground antenna (211);
the input end of the second-stage amplifier II (220) is connected with the output end of the first-stage amplifier III (210);
the input end of the frequency selection circuit II (230) is connected with the output end of the secondary amplifier II (220);
and the signal output interface (300) is respectively connected with the output end of the frequency selecting circuit I (160) and the output end of the frequency selecting circuit II (230).
2. The internal UHF down conversion circuit of claim 1, wherein the first-stage amplifier I (110) and the first-stage amplifier II (120) each include a MOS transistor, a gate of the MOS transistor is connected to a first current-limiting resistor and connected to the first power supply output terminal of the phase locker (150) through the first current-limiting resistor, the first current-limiting resistor is further connected to a first filter capacitor and grounded through the first filter capacitor, a source of the MOS transistor is grounded, a drain of the MOS transistor is connected to the second power supply output terminal of the phase locker (150), the MOS transistor is connected to a second filter capacitor and grounded through the second filter capacitor, and a drain of the MOS transistor is further connected to the second-stage amplifier I (130).
3. The built-in UHF frequency reducing circuit according to claim 2, wherein a first microstrip inductor is connected in series between the gate of the MOS transistor and the first current limiting resistor, and a second microstrip inductor is connected in series between the drain of the MOS transistor and the second power supply output terminal of the phase locker (150).
4. The internal UHF frequency reducing circuit according to claim 1, wherein a microstrip duplexer (131) is connected to an input terminal of the secondary amplifier I (130), and the input terminal is connected to the primary amplifier I and the primary amplifier II (120) through the microstrip duplexer (131).
5. The built-in UHF down-conversion circuit of claim 1, wherein a ceramic filter (161) is connected in series between the phase locker (150) and the frequency selective circuit I (160).
6. The internal UHF down conversion circuit of claim 1, wherein the first-stage amplifier III (210) and the second-stage amplifier II (220) each comprise a triode, a base of the triode is connected to a first coupling capacitor and connected to a preceding stage circuit through the first coupling capacitor, a base of the triode is further connected to a second current-limiting resistor and connected to a working voltage through the second current-limiting resistor, an emitter of the triode is grounded, a collector of the triode is connected to a third microstrip inductor and connected to a third current-limiting resistor through the third microstrip inductor, the third current-limiting resistor is connected to the working voltage, and a collector of the triode is further connected to a second coupling capacitor and connected to a subsequent stage circuit through the second coupling capacitor.
7. The built-in UHF frequency down-conversion circuit according to claim 1 or 6, characterized in that a potentiometer (221) is connected between the primary amplifier III (210) and the secondary amplifier II (220).
8. The built-in UHF frequency reducing circuit of claim 1, wherein the frequency selecting circuit II (230) comprises an inductor L2 and a capacitor C22, a capacitor C24, a capacitor C23, a capacitor C28 and a capacitor C27 which are connected in series, the inductor L2 is connected in parallel to two ends of the capacitor C28, and two ends of the capacitor C24 and two ends of the capacitor C27 are respectively connected in parallel with a fourth microstrip inductor L17 and a fifth microstrip inductor L18.
9. The internal UHF frequency reducing circuit according to claim 1, further comprising a voltage stabilizing circuit (400), wherein the input end of the voltage stabilizing circuit (400) is connected to a magnetic core inductor L1 and is connected to the signal output interface (300) through the magnetic core inductor L1, and the output end of the voltage stabilizing circuit (400) is connected to the phase locker (150), the primary amplifier III (210) and the secondary amplifier II (220), respectively.
10. A built-in UHF down converter comprising the built-in UHF down conversion circuit of any one of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022176262.7U CN213186294U (en) | 2020-09-28 | 2020-09-28 | Built-in UHF frequency reduction circuit and frequency reducer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022176262.7U CN213186294U (en) | 2020-09-28 | 2020-09-28 | Built-in UHF frequency reduction circuit and frequency reducer |
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| CN213186294U true CN213186294U (en) | 2021-05-11 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112104827A (en) * | 2020-09-28 | 2020-12-18 | 珠海市普斯赛特科技有限公司 | Built-in UHF frequency reduction circuit and frequency reducer |
| CN115940830A (en) * | 2023-03-09 | 2023-04-07 | 三微电子科技(苏州)有限公司 | Amplifying circuit and amplifier comprising same |
-
2020
- 2020-09-28 CN CN202022176262.7U patent/CN213186294U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112104827A (en) * | 2020-09-28 | 2020-12-18 | 珠海市普斯赛特科技有限公司 | Built-in UHF frequency reduction circuit and frequency reducer |
| CN115940830A (en) * | 2023-03-09 | 2023-04-07 | 三微电子科技(苏州)有限公司 | Amplifying circuit and amplifier comprising same |
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