CN115940830A - Amplifying circuit and amplifier comprising same - Google Patents
Amplifying circuit and amplifier comprising same Download PDFInfo
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- CN115940830A CN115940830A CN202310219407.2A CN202310219407A CN115940830A CN 115940830 A CN115940830 A CN 115940830A CN 202310219407 A CN202310219407 A CN 202310219407A CN 115940830 A CN115940830 A CN 115940830A
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Abstract
The invention discloses an amplifying circuit and an amplifier comprising the same, wherein in the amplifying circuit, a first-stage amplifying circuit is vertically interconnected with a first peripheral circuit through a solder ball, a second-stage amplifying circuit is electrically connected with a second peripheral circuit, and the gain of the first-stage amplifying circuit is greater than that of the second-stage amplifying circuit; the radio frequency signal of the induction signal access unit at one side of the first peripheral circuit forms a first induction signal, the first induction signal is amplified by the primary amplification circuit to form a first amplification signal, and the first amplification signal is output from the other side of the first peripheral circuit; one side of the second peripheral circuit senses the first amplified signal to form a second sensing signal, the second sensing signal is amplified by the second-stage amplifying circuit to form a second amplified signal, and the second amplified signal is output from the other side of the second peripheral circuit; the signal output unit senses the second amplified signal and outputs the radio frequency signal amplified twice. Therefore, the advantages of low noise, low power consumption and miniaturization can be simultaneously considered.
Description
Technical Field
The invention relates to the technical field of communication, in particular to an amplifying circuit and an amplifier comprising the same.
Background
With the rapid development of wireless communication technology, the requirement for the noise performance of the rf amplifier is higher and higher. Because of the single process (the traditional rf amplifier chip can only be realized by using one silicon-based or compound process), the noise performance of the amplifier cannot exceed a certain range, and a specific noise cancellation technique is required at this time, while in the context of a single process, a plurality of relatively complex circuits are required to reduce noise from the perspective of circuit structure in order to meet the harsh requirements of some application scenarios for the noise performance of the rf amplifier chip. The current methods mainly for realizing low noise of the amplifier are feedback loop design and noise matching of passive devices. The low noise amplifier is realized on a single process, and the miniaturization, low power consumption and low noise cannot be considered at the same time.
Disclosure of Invention
The invention provides an amplifying circuit and an amplifier comprising the same, so that the performances of miniaturization, low power consumption and low noise of the amplifier are realized at the same time.
To achieve the above object, an embodiment of an aspect of the present invention provides an amplifying circuit, including: a first-stage amplifying circuit disposed on the first chip; the second-stage amplification circuit, the first peripheral circuit matched with the first-stage amplification circuit, the second peripheral circuit matched with the second-stage amplification circuit, the signal access unit and the signal output unit are sequentially arranged on the second chip;
the first-stage amplification circuit and the first peripheral circuit are vertically interconnected through a solder ball, the second-stage amplification circuit is electrically connected with the second peripheral circuit, and the gain of the first-stage amplification circuit is larger than that of the second-stage amplification circuit;
one side of the first peripheral circuit induces the radio frequency signal of the signal access unit to form a first induction signal, the first induction signal is amplified by the primary amplifying circuit to form a first amplified signal, and the first amplified signal is output from the other side of the first peripheral circuit; one side of the second peripheral circuit induces the first amplified signal to form a second induced signal, and the second induced signal is amplified by the second-stage amplifying circuit to form a second amplified signal which is output by the other side of the second peripheral circuit; the signal output unit senses the second amplified signal and outputs the radio frequency signal amplified twice.
Optionally, the first chip is a gallium arsenide active device, and the second chip is a silicon-based chip.
Optionally, the first-stage amplifying circuit is a differential pair tube type circuit.
Optionally, the first-stage amplification circuit includes a first transistor and a second transistor, a source of the first transistor and a source of the second transistor are electrically connected to form a first end, a gate of the first transistor is a second end, a drain of the first transistor is a third end, a gate of the second transistor is a fourth end, and a drain of the second transistor is a fifth end;
the first peripheral circuit includes five bonding terminals perpendicularly bonded to the first terminal, the second terminal, the third terminal, the fourth terminal, and the fifth terminal.
Optionally, the first peripheral circuit comprises: the inductor comprises a first inductor, a second inductor, a third inductor and a fourth inductor; one end of the first inductor is a second welding end welded with the second end, the other end of the first inductor is connected with one end of the second inductor and grounded, and the other end of the second inductor is a third welding end welded with the third end; one end of the third inductor is a fourth welding end welded with the fourth end, the other end of the third inductor and one end of the fourth inductor are connected to a power supply, and the other end of the fourth inductor is a fifth welding end welded with the fifth end;
further comprising: and one end of the bias resistor is a first welding end welded with the first end, and the other end of the bias resistor is grounded.
Optionally, the second-stage amplifying circuit is a differential circuit.
Optionally, the two-stage amplifying circuit comprises a third transistor and a fourth transistor, and a source of the third transistor and a source of the fourth transistor are connected to ground;
and the grid electrode and the drain electrode of the third transistor and the grid electrode and the drain electrode of the fourth transistor are also electrically connected with the second peripheral circuit.
Optionally, the second peripheral circuit comprises: a fifth inductor, a sixth inductor, a seventh inductor and an eighth inductor; one end of the fifth inductor is connected with the gate of the third transistor, the other end of the fifth inductor is connected with one end of the sixth inductor, and the other end of the sixth inductor is connected with the gate of the fourth transistor; one end of the seventh inductor is connected to the drain of the third transistor, the other end of the seventh inductor and one end of the eighth inductor are connected to a power supply, and the other end of the eighth inductor is connected to the drain of the fourth transistor.
Optionally, the signal access unit includes a ninth inductor, one end of the ninth inductor is used for accessing a radio frequency signal, and the other end of the ninth inductor is grounded, and the ninth inductor forms mutual inductance with the first inductor and the second inductor, respectively.
Optionally, the signal output unit includes a tenth inductor, one end of the tenth inductor is used for outputting the amplified radio frequency signal, and the other end of the tenth inductor is grounded, and the tenth inductor forms mutual inductance with the seventh inductor and the eighth inductor, respectively.
In order to achieve the above object, according to another embodiment of the present invention, an amplifier is further provided, which includes the amplifying circuit according to any embodiment of the present invention.
According to an amplification circuit and an amplifier including the same proposed by an embodiment of the present invention, the amplification circuit includes: the first-stage amplification circuit is arranged on the first chip, the second-stage amplification circuit is sequentially arranged on the second chip, the first peripheral circuit is matched with the first-stage amplification circuit, the second peripheral circuit is matched with the second-stage amplification circuit, the signal access unit and the signal output unit are arranged on the second chip; the first-stage amplification circuit and the first peripheral circuit are vertically interconnected through a solder ball, and the second-stage amplification circuit is electrically connected with the second peripheral circuit, wherein the gain of the first-stage amplification circuit is greater than that of the second-stage amplification circuit; a radio frequency signal of an induction signal access unit at one side of the first peripheral circuit forms a first induction signal, the first induction signal is amplified by the primary amplification circuit to form a first amplification signal, and the first amplification signal is output from the other side of the first peripheral circuit; one side of the second peripheral circuit senses the first amplified signal to form a second sensing signal, the second sensing signal is amplified by the second-stage amplifying circuit to form a second amplified signal, and the second amplified signal is output from the other side of the second peripheral circuit; the signal output unit senses the second amplified signal and outputs the radio frequency signal amplified twice. Therefore, the primary amplifying circuit arranged on the first chip and the first peripheral circuit on the second chip are connected through the welding of the welding balls by the three-dimensional stacking method, heterogeneous integration is achieved, the transmission loss of radio-frequency signals is lower, stability is better, and miniaturization of devices is facilitated. And the gain of the first-stage amplifying circuit is larger than that of the second-stage amplifying circuit, so that the noise influence of the noise of the second-stage amplifying circuit on the noise of the whole amplifying circuit can be inhibited, and the noise of the whole amplifying circuit is further reduced. Therefore, the amplifier comprising the amplifying circuit can simultaneously take advantages of low noise, low power consumption and miniaturization into consideration, is convenient for large-scale production, and further reduces production cost.
It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present invention, nor do they necessarily limit the scope of the invention. Other features of the present invention will become apparent from the following description.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of an amplifying circuit according to an embodiment of the present invention;
fig. 2 is a structural diagram of an amplifying circuit according to an embodiment of the present invention;
fig. 3 is a first chip structure diagram of an amplifying circuit according to an embodiment of the invention;
fig. 4 is a gain contrast curve of the amplifying circuit applied to a four-channel amplitude-phase multifunctional chip according to the embodiment of the present invention;
fig. 5 is a noise contrast curve of the amplifying circuit applied to a four-channel amplitude-phase multifunctional chip according to the embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in other sequences than those illustrated or described herein. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions.
At present, a low-noise amplifier is realized on a single process, and the miniaturization, low power consumption and low noise cannot be considered at the same time. Although the GaAs active device has good noise performance and higher gain in a millimeter wave frequency band, the GaAs active device has large area and high power consumption; although the Si-based chip has high integration level and low power consumption, the noise performance is poor compared with a GaAs device, and the gain is low in a millimeter wave frequency band. The noise cancellation technology theoretically realizes the elimination of noise by superposing two random noises with phases different by 180 degrees, but the realization of the 180-degree phase difference needs an additional active circuit, and the additional active circuit introduces new noise. Conventional methods for connecting two chips made of different materials together, such as wire bonding technology or tape automated bonding technology, can only operate on a single chip, and are difficult to mass-produce in a large scale, so that the cost of packaging by using the bonding technology is too high.
In order to solve the above problems, the present invention provides an amplifying circuit and an amplifier including the same, which can simultaneously achieve the advantages of miniaturization, low power consumption, and low noise.
Fig. 1 is a schematic diagram of an amplifier circuit according to an embodiment of the present invention. As shown in fig. 1 to 3, the amplifier circuit includes: a first-stage amplification circuit 101 provided on the first chip 100; a secondary amplification circuit 201, a first peripheral circuit 202 matched with the primary amplification circuit 101, a second peripheral circuit 203 matched with the secondary amplification circuit 201, a signal access unit 204 and a signal output unit 205 which are sequentially arranged on the second chip 200;
the first-stage amplification circuit 101 and the first peripheral circuit 202 are vertically interconnected through a solder ball 207, the second-stage amplification circuit 201 is electrically connected with the second peripheral circuit 203, and the gain of the first-stage amplification circuit 101 is larger than that of the second-stage amplification circuit 201;
a radio frequency signal of the sensing signal access unit 204 at one side of the first peripheral circuit 202 forms a first sensing signal, the first sensing signal is amplified by the first-stage amplifying circuit 101 to form a first amplified signal, and the first amplified signal is output from the other side of the first peripheral circuit 202; one side of the second peripheral circuit 203 senses the first amplified signal to form a second sensing signal, and the second sensing signal is amplified by the second-stage amplifying circuit 201 to form a second amplified signal and is output from the other side of the second peripheral circuit 203; the signal output unit 205 senses the second amplified signal and outputs the rf signal amplified twice.
It should be noted that the first-stage amplification circuit 101 on the first chip 100 is vertically soldered and interconnected with the terminals of the first peripheral circuit 202 on the second chip 200 through solder balls 207, wherein the solder balls 207 are drum-shaped, i.e. truncated spheres, and the solder balls 207 in such a shape have more optimized stress distribution and have smaller transmission loss of radio frequency signals, so that the gain of the whole amplification circuit is improved, and the gain of the second-stage amplification circuit 201 is smaller than that of the first-stage amplification circuit 101, thereby suppressing the noise generated by the second-stage amplification circuit 201 from deteriorating the noise performance of the whole amplification circuit. In addition, the solder balls 207 serve as electrical interconnection and stress buffering between the first chip 100 and the second chip 200, so that the reliability of the heterogeneous integrated amplifying circuit is improved. That is, the stacking of the first chip 100 and the second chip 200 miniaturizes the entire amplification circuit, and the vertical interconnection of the solder balls 207 allows the radio frequency signal received from the second chip 200 to directly enter the primary amplification circuit 101 of the first chip 100 with low loss, and the primary amplification circuit 101 has low noise and high gain with respect to the secondary amplification circuit, and finally, the entire amplification circuit has low power consumption, miniaturization, and low noise.
In one embodiment, the first chip 100 is a gallium arsenide active device and the second chip 200 is a silicon-based chip. The gallium arsenide active device has good noise performance, higher gain in a millimeter wave frequency band, large area and high power consumption; the silicon-based chip has high integration level and low power consumption, but has poor noise performance compared with a gallium arsenide device and lower gain in a millimeter wave frequency band, so that the gallium arsenide active device is connected with the silicon-based chip through the solder balls 207, the respective advantages of the gallium arsenide active device and the silicon-based chip are combined, the defects that the low-noise amplifier realized by the conventional single process cannot give consideration to noise, power consumption and miniaturization are overcome, large-scale production can be conveniently carried out, and the production cost is reduced.
Optionally, with continued reference to fig. 1-3, the primary amplification circuit 101 is a differential pair form circuit.
The first-stage amplifying circuit 101 comprises a first transistor Q1 and a second transistor Q2, wherein a source electrode of the first transistor Q1 and a source electrode of the second transistor Q2 are electrically connected to form a first end, a gate electrode of the first transistor Q1 is a second end, a drain electrode of the first transistor Q1 is a third end, a gate electrode of the second transistor Q2 is a fourth end, and a drain electrode of the second transistor Q2 is a fifth end;
the first peripheral circuit 202 includes five bonding terminals that are perpendicularly bonded to the first terminal, the second terminal, the third terminal, the fourth terminal, and the fifth terminal.
The first peripheral circuit 202 includes: a first inductor L1, a second inductor L2, a third inductor L3 and a fourth inductor L4; one end of the first inductor L1 is a second welding end welded with the second end, the other end of the first inductor L1 is connected with one end of the second inductor L2 and grounded, and the other end of the second inductor L2 is a third welding end welded with the third end; one end of the third inductor L3 is a fourth welding end welded with the fourth end, the other end of the third inductor L3 and one end of the fourth inductor L4 are connected to a power supply, and the other end of the fourth inductor L4 is a fifth welding end welded with the fifth end; the first peripheral circuit 202 further includes: and one end of the bias resistor R1 is a first welding end welded with the first end, and the other end of the bias resistor R1 is grounded.
It should be noted that the first-stage amplifying circuit 101 is a differential pair transistor type circuit, and can provide a higher gain and lower noise for the circuit. Both the first transistor Q1 and the second transistor Q2 may be pHEMT devices. In the first end, the second end, the third end, the fourth end and the fifth end of the first-stage amplifying circuit 101, the first end is the center, and the other four ends are distributed in a central symmetry manner. Therefore, the stress uniformity of the whole amplifying circuit is facilitated, and the structure is stable. The geometric dimensions of the five solder balls 207 between the first chip 100 and the second chip 200 are completely the same, the arrangement mode of the five solder balls 207 is just matched with the layout arrangement mode of the differential pair transistors of the gallium arsenide chip and the silicon-based chip, and the five solder balls 207 are respectively connected with 5 pads of the gallium arsenide chip and the silicon-based chip, so that the vertical interconnection of the solder balls 207 can realize a heterogeneous integration mode without increasing the difficulty of chip layout design.
The first peripheral circuit 202 is provided with a bias resistor R1, a self-biased differential pair-transistor gallium arsenide active device, a terminal of the self-biased differential pair-transistor gallium arsenide active device is vertically transited to a silicon-based chip through a 3D stacking process, and the first peripheral circuit 202 and the bias resistor R1 are arranged on the silicon-based chip. The bias resistor R1 is connected between the radio frequency ground and the direct current ground, so that the radio frequency signal is prevented from passing through, and because the bias resistor R1 is not contained in an equivalent signal circuit of the primary amplifying circuit 101, the thermal noise generated by the bias resistor R1 is not transmitted to the radio frequency output end of the amplifier, thereby effectively reducing the circuit noise. The situation that the common gallium arsenide amplifier circuit adopts a self-bias circuit structure in order to simplify a power-up scheme, a self-bias resistor is introduced to participate in matching of a radio frequency circuit, extra thermal noise is introduced into the self-bias resistor due to random thermal motion of current carriers, and the noise performance of the circuit is deteriorated to a certain extent is avoided.
With continued reference to fig. 1, the two-stage amplification circuit 201 is a differential circuit.
The two-stage amplifying circuit 201 comprises a third transistor Q3 and a fourth transistor Q4, wherein the source electrode of the third transistor Q3 and the source electrode of the fourth transistor Q4 are connected to the ground; the gate and drain of the third transistor Q3 and the gate and drain of the fourth transistor Q4 are also electrically connected to the second peripheral circuit 203.
The second peripheral circuit 203 includes: a fifth inductor L5, a sixth inductor L6, a seventh inductor L7, and an eighth inductor L8; one end of a fifth inductor L5 is connected to the gate of the third transistor Q3, the other end of the fifth inductor L is connected to one end of a sixth inductor L6, and the other end of the sixth inductor L6 is connected to the gate of the fourth transistor Q4; one end of the seventh inductor L7 is connected to the drain of the third transistor Q3, the other end and one end of the eighth inductor L8 are connected to the power supply, and the other end of the eighth inductor L8 is connected to the drain of the fourth transistor Q4.
The third transistor Q3 and the fourth transistor Q4 may be both insulated gate effect transistors, i.e., MOS transistors. Since a single-stage amplifier hardly meets the requirements of low noise and high gain, in order to further reduce the noise of the whole amplifier circuit, an MOS transistor is used as a device of the second-stage amplifier circuit 201 in this example, and is cascaded with the first-stage amplifier circuit 101, so as to increase the gain of the whole circuit and suppress the influence of the latter-stage circuit on the noise performance. Because the silicon-based process does not have a grounding back hole in the compound semiconductor process, the radio-frequency circuit based on the silicon-based process needs a bonding gold wire to be connected with an external ground, and the silicon-based MOS tube circuit (the secondary amplification circuit 201) adopts a differential form, so that an MOS tube source (source) end is in a small-signal alternating-current ground state, the influence of the bonding gold wire is effectively eliminated, and the thermal noise generated by the parasitic resistance of the bonding gold wire is prevented from being transmitted to an amplifier output end. The pHEMT tube based on the gallium arsenide process has high gain, and the MOS transistor based on the silicon process has high noise; therefore, the combined mode of placing the gallium arsenide device at the first stage and placing the silicon-based chip at the second stage can enable the high gain of the gallium arsenide device to effectively inhibit the noise generated by the silicon-based chip, thereby greatly reducing the output noise of the whole circuit of the low-noise amplifier.
Optionally, with continued reference to fig. 1, the signal access unit 204 includes a ninth inductor L9, one end of the ninth inductor L9 is used for accessing a radio frequency signal, and the other end is grounded, and the ninth inductor L9 forms mutual inductance with the first inductor L1 and the second inductor L2, respectively. The signal output unit 205 includes a tenth inductor L10, one end of the tenth inductor L10 is used for outputting the amplified radio frequency signal, and the other end is grounded, and the tenth inductor L10 forms mutual inductance with the seventh inductor L7 and the eighth inductor L8, respectively.
Therefore, as shown in fig. 1, a radio frequency signal enters an S end of the signal access unit 204, and is mutually inducted with the first inductor L1 and the second inductor L2 in the first peripheral circuit 202 through the ninth inductor L9 to transmit the radio frequency signal to the first-stage amplification circuit 101, after the first-stage amplification circuit 101 performs first-stage amplification on the inducted radio frequency signal, the third inductor L3 and the fourth inductor L4 of the first peripheral circuit 202 perform mutual induction with the fifth inductor L5 and the sixth inductor L6 of the second peripheral circuit 203 to transmit the first-stage amplified radio frequency signal to the second-stage amplification circuit 201, the second-stage amplification circuit 201 performs second-stage amplification on the inducted first-stage amplified radio frequency signal, and finally induces the second-stage amplified radio frequency signal output by the seventh inductor L7 and the eighth inductor L8 of the second peripheral circuit 203 through the tenth inductor L10 in the signal output unit 205, and the second-stage amplified radio frequency signal is output from the S end of the tenth inductor L10. The terminal G in fig. 1 is a ground terminal.
Therefore, in the amplifying circuit provided by the invention, the gallium arsenide active device and the silicon-based chip are stacked, and the chips made of two different materials are integrated together, so that heterogeneous integration is realized, the area of the chip is effectively reduced, the defect that the noise performance of the silicon-based amplifier is lower than that of the gallium arsenide amplifier is overcome, and higher integration level and better performance index can be realized at the same time. The gallium arsenide differential pair tube structure can allow the self-bias resistor to be connected between the radio frequency ground and the direct current ground, so that the required bias voltage can be provided, and the noise can be effectively reduced. The terminals of the gallium arsenide differential pair tube structure are distributed in a five-point type arrangement, so that the stacked chips are stressed uniformly and have stable structures. The reliability of the chip is ensured. The MOS differential pair transistor enables the source end of the MOS transistor to be in a small-signal alternating-current ground state, effectively eliminates the influence of a bonding gold wire, and avoids the transmission of noise generated by parasitic resistance of the bonding gold wire to the output end of the amplifier. The gallium arsenide active device is placed at the first stage of the whole circuit, the silicon-based chip is placed at the second stage of the whole circuit, and the high gain of the gallium arsenide active device is utilized to suppress noise.
In an application example, in an amplitude-phase multichannel chip, due to the integration of the invention, an external low-noise amplification chip is not required to be added separately, and a phased array antenna unit with small volume can be realized.
The four-channel amplitude-phase multifunctional chip is designed by adopting a 55nm RFCMOS process. A low noise self-biased 3D stacked differential amplification circuit is integrated on the chip. The following is a comparison of channel noise indicators with and without integrating the stacked low noise amplifier, as shown in fig. 4 and 5, and it can be seen that by using the amplifier circuit of the present invention, the noise indicators are significantly reduced (as shown in fig. 5, the horizontal axis is the rf frequency, and the vertical axis is the noise), and the gain indicators are significantly improved (as shown in fig. 4, the horizontal axis is the rf frequency, and the vertical axis is the gain), wherein the comparison scheme is a silicon-based amplifier circuit.
In another aspect, an embodiment of the present invention further provides an amplifier, including the amplifying circuit according to any embodiment of the present invention. The amplifier has the advantage of amplification circuit.
In summary, according to the amplifying circuit and the amplifier including the same provided by the embodiments of the present invention, the amplifying circuit includes: the first-stage amplification circuit is arranged on the first chip, the second-stage amplification circuit is sequentially arranged on the second chip, the first peripheral circuit is matched with the first-stage amplification circuit, the second peripheral circuit is matched with the second-stage amplification circuit, the signal access unit and the signal output unit; the first-stage amplification circuit and the first peripheral circuit are vertically interconnected through a solder ball, the second-stage amplification circuit is electrically connected with the second peripheral circuit, and the gain of the first-stage amplification circuit is larger than that of the second-stage amplification circuit; the radio frequency signal of the induction signal access unit at one side of the first peripheral circuit forms a first induction signal, the first induction signal is amplified by the primary amplification circuit to form a first amplification signal, and the first amplification signal is output from the other side of the first peripheral circuit; one side of the second peripheral circuit senses the first amplified signal to form a second sensing signal, the second sensing signal is amplified by the second-stage amplifying circuit to form a second amplified signal, and the second amplified signal is output from the other side of the second peripheral circuit; the signal output unit senses the second amplified signal and outputs the radio frequency signal amplified twice. Therefore, the primary amplifying circuit arranged on the first chip and the first peripheral circuit on the second chip are connected through the welding of the welding balls by the three-dimensional stacking method, heterogeneous integration is achieved, the transmission loss of radio-frequency signals is lower, stability is better, and miniaturization of devices is facilitated. And the gain of the first-stage amplifying circuit is larger than that of the second-stage amplifying circuit, so that the noise influence of the noise of the second-stage amplifying circuit on the noise of the whole amplifying circuit can be inhibited, and the noise of the whole amplifying circuit is further reduced. Therefore, the amplifier comprising the amplifying circuit can simultaneously take advantages of low noise, low power consumption and miniaturization into consideration, is convenient for large-scale production, and further reduces production cost.
The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made, depending on design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (11)
1. An amplification circuit, comprising: a first-stage amplifying circuit disposed on the first chip; the second-stage amplification circuit, the first peripheral circuit matched with the first-stage amplification circuit, the second peripheral circuit matched with the second-stage amplification circuit, the signal access unit and the signal output unit are sequentially arranged on the second chip;
the first-stage amplification circuit and the first peripheral circuit are vertically interconnected through a solder ball, the second-stage amplification circuit is electrically connected with the second peripheral circuit, and the gain of the first-stage amplification circuit is larger than that of the second-stage amplification circuit;
one side of the first peripheral circuit induces the radio frequency signal of the signal access unit to form a first induction signal, the first induction signal is amplified by the primary amplifying circuit to form a first amplified signal, and the first amplified signal is output from the other side of the first peripheral circuit; one side of the second peripheral circuit induces the first amplified signal to form a second induced signal, and the second induced signal is amplified by the second-stage amplifying circuit to form a second amplified signal which is output by the other side of the second peripheral circuit; the signal output unit senses the second amplified signal and outputs the radio frequency signal amplified twice.
2. The amplifier circuit of claim 1, wherein the first chip is a gallium arsenide active device and the second chip is a silicon-based chip.
3. The amplifier circuit according to claim 1 or 2, wherein the primary amplifier circuit is a differential pair transistor type circuit.
4. The amplifier circuit according to claim 3, wherein the one-stage amplifier circuit comprises a first transistor and a second transistor, a source of the first transistor and a source of the second transistor are electrically connected to form a first terminal, a gate of the first transistor is a second terminal, a drain of the first transistor is a third terminal, a gate of the second transistor is a fourth terminal, and a drain of the second transistor is a fifth terminal;
the first peripheral circuit includes five bonding terminals perpendicularly bonded to the first terminal, the second terminal, the third terminal, the fourth terminal, and the fifth terminal.
5. The amplification circuit of claim 4, wherein the first peripheral circuit comprises: the inductor comprises a first inductor, a second inductor, a third inductor and a fourth inductor; one end of the first inductor is a second welding end welded with the second end, the other end of the first inductor is connected with one end of the second inductor and grounded, and the other end of the second inductor is a third welding end welded with the third end; one end of the third inductor is a fourth welding end welded with the fourth end, the other end of the third inductor and one end of the fourth inductor are connected to a power supply, and the other end of the fourth inductor is a fifth welding end welded with the fifth end;
further comprising: and one end of the bias resistor is a first welding end welded with the first end, and the other end of the bias resistor is grounded.
6. The amplifying circuit according to claim 1 or 2, wherein the two-stage amplifying circuit is a differential circuit.
7. The amplifier circuit according to claim 6, wherein the two-stage amplifier circuit comprises a third transistor and a fourth transistor, and a source of the third transistor and a source of the fourth transistor are connected to ground;
and the grid electrode and the drain electrode of the third transistor and the grid electrode and the drain electrode of the fourth transistor are also electrically connected with the second peripheral circuit.
8. The amplification circuit of claim 7, wherein the second peripheral circuit comprises: a fifth inductor, a sixth inductor, a seventh inductor and an eighth inductor; one end of the fifth inductor is connected with the gate of the third transistor, the other end of the fifth inductor is connected with one end of the sixth inductor, and the other end of the sixth inductor is connected with the gate of the fourth transistor; one end of the seventh inductor is connected to the drain of the third transistor, the other end of the seventh inductor and one end of the eighth inductor are connected to a power supply, and the other end of the eighth inductor is connected to the drain of the fourth transistor.
9. The amplifying circuit according to claim 5, wherein the signal coupling unit includes a ninth inductor, one end of the ninth inductor is used for coupling in a radio frequency signal, and the other end of the ninth inductor is grounded, and the ninth inductor forms mutual inductance with the first inductor and the second inductor respectively.
10. The amplifier circuit according to claim 8, wherein the signal output unit comprises a tenth inductor, one end of the tenth inductor is used for outputting the amplified rf signal, and the other end of the tenth inductor is grounded, and the tenth inductor forms mutual inductance with the seventh inductor and the eighth inductor, respectively.
11. An amplifier comprising an amplifying circuit according to any one of claims 1 to 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310219407.2A CN115940830B (en) | 2023-03-09 | 2023-03-09 | Amplifying circuit and amplifier comprising same |
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| CN202310219407.2A CN115940830B (en) | 2023-03-09 | 2023-03-09 | Amplifying circuit and amplifier comprising same |
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| CN115940830B CN115940830B (en) | 2023-05-16 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008145604A1 (en) * | 2007-05-29 | 2008-12-04 | Telefonaktiebolaget Lm Ericsson (Publ) | Configurable, variable gain lna for multi-band rf receiver |
| CN206164477U (en) * | 2016-09-21 | 2017-05-10 | 无锡中科微电子工业技术研究院有限责任公司 | Current reuse type high frequency amplifier circuit |
| CN109245735A (en) * | 2018-10-18 | 2019-01-18 | 成都嘉纳海威科技有限责任公司 | A kind of high efficiency J class stacking power amplifier based on second harmonic injection technique |
| CN213186294U (en) * | 2020-09-28 | 2021-05-11 | 珠海市普斯赛特科技有限公司 | Built-in UHF frequency reduction circuit and frequency reducer |
| CN114649310A (en) * | 2020-12-17 | 2022-06-21 | 株式会社村田制作所 | Power amplifier and RF circuit module |
-
2023
- 2023-03-09 CN CN202310219407.2A patent/CN115940830B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008145604A1 (en) * | 2007-05-29 | 2008-12-04 | Telefonaktiebolaget Lm Ericsson (Publ) | Configurable, variable gain lna for multi-band rf receiver |
| CN206164477U (en) * | 2016-09-21 | 2017-05-10 | 无锡中科微电子工业技术研究院有限责任公司 | Current reuse type high frequency amplifier circuit |
| CN109245735A (en) * | 2018-10-18 | 2019-01-18 | 成都嘉纳海威科技有限责任公司 | A kind of high efficiency J class stacking power amplifier based on second harmonic injection technique |
| CN213186294U (en) * | 2020-09-28 | 2021-05-11 | 珠海市普斯赛特科技有限公司 | Built-in UHF frequency reduction circuit and frequency reducer |
| CN114649310A (en) * | 2020-12-17 | 2022-06-21 | 株式会社村田制作所 | Power amplifier and RF circuit module |
Also Published As
| Publication number | Publication date |
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| CN115940830B (en) | 2023-05-16 |
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