CN115940830B - Amplifying circuit and amplifier comprising same - Google Patents
Amplifying circuit and amplifier comprising same Download PDFInfo
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- CN115940830B CN115940830B CN202310219407.2A CN202310219407A CN115940830B CN 115940830 B CN115940830 B CN 115940830B CN 202310219407 A CN202310219407 A CN 202310219407A CN 115940830 B CN115940830 B CN 115940830B
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Abstract
The invention discloses an amplifying circuit and an amplifier comprising the same, wherein in the amplifying circuit, a first-stage amplifying circuit is vertically interconnected with a first peripheral circuit through a solder ball, a second-stage amplifying circuit is electrically connected with a second peripheral circuit, and the gain of the first-stage amplifying circuit is larger than that of the second-stage amplifying circuit; the method comprises the steps that a radio frequency signal of a sensing signal access unit at one side of a first peripheral circuit forms a first sensing signal, the first sensing signal is amplified by a primary amplifying circuit to form a first amplifying signal, and the first amplifying signal is output from the other side of the first peripheral circuit; sensing the first amplified signal on one side of the second peripheral circuit to form a second sensed signal, amplifying the second sensed signal by the second-stage amplifying circuit to form a second amplified signal, and outputting the second amplified signal on the other side of the second peripheral circuit; the signal output unit senses the second amplified signal and outputs a radio frequency signal amplified twice. Thus, the advantages of low noise, low power consumption and miniaturization can be simultaneously achieved.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to an amplifying circuit and an amplifier including the same.
Background
With the rapid development of wireless communication technology, the noise performance of the radio frequency amplifier is required to be higher and higher. Because the single process is limited (the traditional radio frequency amplifier chip can only be realized by adopting a silicon-based or compound process), the noise performance of the amplifier cannot exceed a certain range, a specific noise elimination technology is required at the moment, and in the background of the single process, a plurality of relatively complex circuits are required to be used for meeting the severe requirements of certain application scenes in order to ensure the noise performance of the radio frequency amplifier chip, so that the noise is reduced from the aspect of circuit structure. The current method for mainly realizing low noise of the amplifier is feedback loop design and noise matching of passive devices. The low noise amplifier is realized on a single process, and the miniaturization, low power consumption and low noise cannot be achieved simultaneously.
Disclosure of Invention
The invention provides an amplifying circuit and an amplifier comprising the same, which can simultaneously realize the performance of miniaturization, low power consumption and low noise of the amplifier.
To achieve the above object, an embodiment of an aspect of the present invention provides an amplifying circuit, including: a first-stage amplifying circuit provided on the first chip; the second-stage amplifying circuit, the first peripheral circuit matched with the first-stage amplifying circuit, the second peripheral circuit matched with the second-stage amplifying circuit, the signal access unit and the signal output unit are sequentially arranged on the second chip;
the first-stage amplifying circuit is vertically interconnected with the first peripheral circuit through a solder ball, and the second-stage amplifying circuit is electrically connected with the second peripheral circuit, wherein the gain of the first-stage amplifying circuit is larger than that of the second-stage amplifying circuit;
one side of the first peripheral circuit senses the radio frequency signal of the signal access unit to form a first sensing signal, the first sensing signal is amplified by the primary amplifying circuit to form a first amplified signal, and the first amplified signal is output by the other side of the first peripheral circuit; sensing the first amplified signal by one side of the second peripheral circuit to form a second sensed signal, wherein the second sensed signal is amplified by the second-stage amplifying circuit to form a second amplified signal, and the second amplified signal is output by the other side of the second peripheral circuit; the signal output unit senses the second amplified signal and outputs the radio frequency signal amplified twice.
Optionally, the first chip is a gallium arsenide active device, and the second chip is a silicon-based chip.
Optionally, the first-stage amplifying circuit is a differential pair-tube type circuit.
Optionally, the first-stage amplifying circuit includes a first transistor and a second transistor, where a source of the first transistor and a source of the second transistor are electrically connected to form a first end, a gate of the first transistor is a second end, a drain of the first transistor is a third end, a gate of the second transistor is a fourth end, and a drain of the second transistor is a fifth end;
the first peripheral circuit includes five soldering terminals soldered perpendicularly to the first, second, third, fourth and fifth terminals.
Optionally, the first peripheral circuit includes: a first inductor, a second inductor, a third inductor and a fourth inductor; one end of the first inductor is a second welding end welded with the second end, the other end of the first inductor is connected with one end of the second inductor and grounded, and the other end of the second inductor is a third welding end welded with the third end; one end of the third inductor is a fourth welding end welded with the fourth end, the other end of the third inductor and one end of the fourth inductor are connected to a power supply, and the other end of the fourth inductor is a fifth welding end welded with the fifth end;
further comprises: and one end of the bias resistor is a first welding end welded with the first end, and the other end of the bias resistor is grounded.
Optionally, the second-stage amplifying circuit is a differential circuit.
Optionally, the second-stage amplifying circuit includes a third transistor and a fourth transistor, and a source electrode of the third transistor is grounded to a source electrode of the fourth transistor;
and the grid electrode and the drain electrode of the third transistor are electrically connected with the second peripheral circuit.
Optionally, the second peripheral circuit includes: a fifth inductance, a sixth inductance, a seventh inductance, and an eighth inductance; one end of the fifth inductor is connected with the grid electrode of the third transistor, the other end of the fifth inductor is connected with a power supply, and the other end of the sixth inductor is connected with the grid electrode of the fourth transistor; one end of the seventh inductor is connected with the drain electrode of the third transistor, the other end of the seventh inductor is connected with one end of the eighth inductor to a power supply, and the other end of the eighth inductor is connected with the drain electrode of the fourth transistor.
Optionally, the signal access unit includes a ninth inductor, one end of the ninth inductor is used for accessing a radio frequency signal, the other end of the ninth inductor is grounded, and the ninth inductor forms mutual inductance with the first inductor and the second inductor respectively.
Optionally, the signal output unit includes a tenth inductor, one end of the tenth inductor is used for outputting the amplified radio frequency signal, the other end of the tenth inductor is grounded, and the tenth inductor forms mutual inductance with the seventh inductor and the eighth inductor respectively.
In order to achieve the above object, another embodiment of the present invention further provides an amplifier, which includes the amplifying circuit according to any one of the embodiments of the present invention.
According to an embodiment of the invention, an amplifying circuit and an amplifier comprising the same are provided, wherein the amplifying circuit comprises: the signal processing circuit comprises a first-stage amplifying circuit arranged on a first chip, a second-stage amplifying circuit arranged on a second chip in sequence, a first peripheral circuit matched with the first-stage amplifying circuit, a second peripheral circuit matched with the second-stage amplifying circuit, a signal access unit and a signal output unit; the first-stage amplifying circuit is vertically interconnected with the first peripheral circuit through a solder ball, and the second-stage amplifying circuit is electrically connected with the second peripheral circuit, wherein the gain of the first-stage amplifying circuit is larger than that of the second-stage amplifying circuit; the method comprises the steps that a radio frequency signal of a sensing signal access unit at one side of a first peripheral circuit forms a first sensing signal, the first sensing signal is amplified by a primary amplifying circuit to form a first amplifying signal, and the first amplifying signal is output from the other side of the first peripheral circuit; sensing the first amplified signal on one side of the second peripheral circuit to form a second sensed signal, amplifying the second sensed signal by the second-stage amplifying circuit to form a second amplified signal, and outputting the second amplified signal on the other side of the second peripheral circuit; the signal output unit senses the second amplified signal and outputs a radio frequency signal amplified twice. Therefore, through a three-dimensional stacking method, the first-stage amplifying circuit arranged on the first chip is connected with the first peripheral circuit arranged on the second chip through welding balls, heterogeneous integration is realized, the transmission loss of radio frequency signals is lower, the stability is better, and the miniaturization of devices is facilitated. And the gain of the primary amplifying circuit is larger than that of the secondary amplifying circuit, so that the influence of noise of the secondary amplifying circuit on the noise of the whole amplifying circuit can be restrained, and the noise of the whole amplifying circuit is further reduced. Therefore, the amplifier comprising the amplifying circuit can simultaneously realize the advantages of low noise, low power consumption and miniaturization, is convenient for large-scale production, and further reduces the production cost.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an amplifying circuit according to an embodiment of the present invention;
fig. 2 is a block diagram of an amplifying circuit according to an embodiment of the present invention;
FIG. 3 is a first chip configuration diagram of an amplifying circuit according to an embodiment of the present invention;
FIG. 4 is a gain contrast curve of an amplifying circuit according to an embodiment of the present invention applied to a four-channel amplitude-phase multifunctional chip;
fig. 5 is a noise contrast curve of the amplifying circuit applied to the four-channel amplitude-phase multifunctional chip according to the embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.
At present, the low noise amplifier is realized on a single process, and miniaturization, low power consumption and low noise cannot be achieved simultaneously. Although the GaAs active device has good noise performance and higher gain in the millimeter wave frequency band, the GaAs active device has large area and high power consumption; although the Si-based chip has high integration level and low power consumption, the Si-based chip has poorer noise performance than a GaAs device and lower gain in the millimeter wave frequency band. Noise cancellation techniques theoretically achieve noise cancellation by superimposing two random noises 180 degrees out of phase, but implementation of 180 degrees out of phase requires additional active circuitry that introduces new noise. Traditional methods for connecting two chips made of different materials together, such as wire bonding technology or carrier tape automatic bonding technology, can only be operated for a single chip, and large-scale batch production is difficult, so that the packaging cost is too high due to the bonding technology.
In order to solve the above problems, the present invention proposes an amplifying circuit capable of simultaneously achieving miniaturization, low power consumption, and low noise advantages, and an amplifier including the same.
Fig. 1 is a schematic diagram of an amplifying circuit according to an embodiment of the present invention. As shown in connection with fig. 1 to 3, the amplifying circuit includes: a first-stage amplification circuit 101 provided on the first chip 100; a second-stage amplification circuit 201, a first peripheral circuit 202 matched with the first-stage amplification circuit 101, a second peripheral circuit 203 matched with the second-stage amplification circuit 201, a signal access unit 204, and a signal output unit 205, which are sequentially provided on the second chip 200;
the first-stage amplification circuit 101 is vertically interconnected with the first peripheral circuit 202 through a solder ball 207, and the second-stage amplification circuit 201 is electrically connected with the second peripheral circuit 203, wherein the gain of the first-stage amplification circuit 101 is larger than that of the second-stage amplification circuit 201;
the radio frequency signal of the sensing signal access unit 204 at one side of the first peripheral circuit 202 forms a first sensing signal, the first sensing signal is amplified by the first-stage amplifying circuit 101 to form a first amplified signal, and the first amplified signal is output from the other side of the first peripheral circuit 202; sensing the first amplified signal by one side of the second peripheral circuit 203 to form a second sensed signal, amplifying the second sensed signal by the second stage amplifying circuit 201 to form a second amplified signal, and outputting the second amplified signal by the other side of the second peripheral circuit 203; the signal output unit 205 senses the second amplified signal and outputs a twice amplified radio frequency signal.
It should be noted that, the first stage amplifying circuit 101 on the first chip 100 is vertically soldered and interconnected with the terminal of the first peripheral circuit 202 on the second chip 200 through the solder ball 207, wherein the solder ball 207 is in a drum shape, i.e. a truncated sphere, and the solder ball 207 in this shape has more optimized stress distribution and has smaller radio frequency signal transmission loss, thus improving the gain of the whole amplifying circuit, and the gain of the second stage amplifying circuit 201 is smaller than that of the first stage amplifying circuit 101, so that the noise generated by the second stage amplifying circuit 201 is suppressed from deteriorating the noise performance of the whole amplifying circuit. In addition, the solder balls 207 play a role in electrical interconnection and stress buffering between the first chip 100 and the second chip 200, and improve the reliability of the isomerically integrated amplifying circuit. That is, the stacking of the first chip 100 and the second chip 200 miniaturizes the entire amplifying circuit, and the vertical interconnection of the solder balls 207 allows the radio frequency signal received from the second chip 200 to directly enter the primary amplifying circuit 101 of the first chip 100 with low loss, and the primary amplifying circuit 101 has low noise and large gain relative to the secondary amplifying circuit, ultimately resulting in low power consumption, miniaturization, and low noise of the entire amplifying circuit.
In one embodiment, the first chip 100 is a gallium arsenide active device and the second chip 200 is a silicon-based chip. The gallium arsenide active device has good noise performance, higher gain in millimeter wave frequency band, but large area and high power consumption; the silicon-based chip has high integration level and low power consumption, but has poorer noise performance compared with a gallium arsenide device and lower gain in a millimeter wave frequency band, thereby connecting the gallium arsenide active device with the silicon-based chip through the solder balls 207, combining the respective advantages of the gallium arsenide active device and the silicon-based chip, overcoming the defect that the existing low-noise amplifier realized by a single process cannot give consideration to noise, power consumption and miniaturization, and being convenient for mass production, thereby reducing the production cost.
Alternatively, with continued reference to fig. 1-3, the primary amplifying circuit 101 is a differential pair-tube type circuit.
The first-stage amplifying circuit 101 includes a first transistor Q1 and a second transistor Q2, where a source of the first transistor Q1 and a source of the second transistor Q2 are electrically connected to form a first end, a gate of the first transistor Q1 is a second end, a drain of the first transistor Q1 is a third end, a gate of the second transistor Q2 is a fourth end, and a drain of the second transistor Q2 is a fifth end;
the first peripheral circuit 202 includes five bonding terminals bonded perpendicularly to the first, second, third, fourth and fifth terminals.
The first peripheral circuit 202 includes: a first inductance L1, a second inductance L2, a third inductance L3, and a fourth inductance L4; one end of the first inductor L1 is a second welding end welded with the second end, the other end of the first inductor L1 is connected with one end of the second inductor L2 to be grounded, and the other end of the second inductor L2 is a third welding end welded with the third end; one end of the third inductor L3 is a fourth welding end welded with the fourth end, the other end of the third inductor L3 and one end of the fourth inductor L4 are connected to a power supply, and the other end of the fourth inductor L4 is a fifth welding end welded with the fifth end; the first peripheral circuit 202 further includes: and one end of the bias resistor R1 is a first welding end welded with the first end, and the other end of the bias resistor R1 is grounded.
It should be noted that, the first-stage amplifying circuit 101 is a differential pair-tube type circuit, which can provide a higher gain and lower noise for the circuit. Wherein, the first transistor Q1 and the second transistor Q2 may be pHEMT devices. Among the five terminals of the first end, the second end, the third end, the fourth end and the fifth end of the primary amplifying circuit 101, the first end is the center, and the remaining four ends are distributed symmetrically. Therefore, the stress of the whole amplifying circuit is more favorable to be uniform, and the structure is stable. The geometry of five solder balls 207 between the first chip 100 and the second chip 200 is completely the same, the arrangement mode of the five solder balls 207 is just matched with the arrangement mode of the differential pair transistor layout of the gallium arsenide chip and the silicon base chip, and the five solder balls 207 are respectively connected with 5 pads of the gallium arsenide chip and the silicon base chip, so that the vertical interconnection of the solder balls 207 can realize the heterogeneous integration mode without increasing the difficulty of chip layout design.
The first peripheral circuit 202 is provided with a bias resistor R1, and a gallium arsenide active device in the form of a self-bias differential pair transistor is vertically transited to a silicon-based chip through a 3D stacking process, and the first peripheral circuit 202 and the bias resistor R1 are arranged on the silicon-based chip. The bias resistor R1 is connected between the radio frequency ground and the direct current ground, so that the passing of radio frequency signals is avoided, and because the bias resistor R1 is not contained in an equivalent signal circuit of the primary amplifying circuit 101, thermal noise generated by the bias resistor R1 is not transmitted to the radio frequency output end of the amplifier, and circuit noise is effectively reduced. The self-bias resistor is introduced to participate in the matching of the radio frequency circuit, and the self-bias resistor can introduce additional thermal noise due to the random thermal motion of carriers, so that the noise performance of the circuit can be deteriorated to a certain extent.
With continued reference to fig. 1, the two-stage amplification circuit 201 is a differential circuit.
The second-stage amplifying circuit 201 includes a third transistor Q3 and a fourth transistor Q4, where a source of the third transistor Q3 is connected to a source of the fourth transistor Q4 and grounded; the gate and drain of the third transistor Q3 and the gate and drain of the fourth transistor Q4 are also electrically connected to the second peripheral circuit 203.
The second peripheral circuit 203 includes: a fifth inductance L5, a sixth inductance L6, a seventh inductance L7, and an eighth inductance L8; one end of the fifth inductor L5 is connected with the grid electrode of the third transistor Q3, the other end of the fifth inductor L5 is connected with a power supply, and the other end of the sixth inductor L6 is connected with the grid electrode of the fourth transistor Q4; one end of the seventh inductor L7 is connected to the drain of the third transistor Q3, the other end is connected to a power supply at one end of the eighth inductor L8, and the other end of the eighth inductor L8 is connected to the drain of the fourth transistor Q4.
The third transistor Q3 and the fourth transistor Q4 may be both insulated gate effect transistors, i.e., MOS transistors. Because the single-stage amplifier is difficult to meet the requirement of low noise and high gain, in order to further reduce the noise of the overall amplifier circuit, in this example, an MOS transistor is used as a device of the second-stage amplifying circuit 201, and is cascaded with the first-stage amplifying circuit 101, so that the gain of the overall circuit is improved, and the influence of the subsequent-stage circuit on the noise performance is suppressed. Because the silicon-based process has no grounding back hole in the compound semiconductor process, the radio frequency circuit based on the silicon-based process needs to connect the bond alloy wire with the external ground, and the silicon-based MOS tube circuit (the secondary amplifying circuit 201) adopts a differential mode, so that the MOS tube source (source) end is in a small signal alternating current ground state, the influence of the bond alloy wire is effectively eliminated, and the thermal noise generated by the parasitic resistance of the bond alloy wire is prevented from being transmitted to the output end of the amplifier. The pHEMT tube based on gallium arsenide technology has high gain, and the MOS transistor based on silicon technology has high noise; therefore, the combination mode that the gallium arsenide device is arranged at the first stage and the silicon base chip is arranged at the second stage can effectively restrain noise generated by the silicon base chip by high gain of the gallium arsenide device, so that output noise of the whole circuit of the low noise amplifier is greatly reduced.
Optionally, with continued reference to fig. 1, the signal access unit 204 includes a ninth inductor L9, where one end of the ninth inductor L9 is used to access the radio frequency signal, and the other end of the ninth inductor L9 is grounded, and the ninth inductor L9 forms mutual inductance with the first inductor L1 and the second inductor L2, respectively. The signal output unit 205 includes a tenth inductor L10, one end of the tenth inductor L10 is used for outputting the amplified radio frequency signal, the other end is grounded, and the tenth inductor L10 forms mutual inductance with the seventh inductor L7 and the eighth inductor L8, respectively.
Thus, as shown in fig. 1, the signal access unit 204 has an S-end for receiving the radio frequency signal, the radio frequency signal is transmitted to the first-stage amplifying circuit 101 through the mutual inductance between the ninth inductor L9 and the first inductor L1 and the second inductor L2 in the first peripheral circuit 202, the first-stage amplifying circuit 101 amplifies the induced radio frequency signal, the third inductor L3 and the fourth inductor L4 of the first peripheral circuit 202 and the fifth inductor L5 and the sixth inductor L6 of the second peripheral circuit 203 are mutually inducted, the radio frequency signal after the first-stage amplification is transmitted to the second-stage amplifying circuit 201, the second-stage amplifying circuit 201 amplifies the induced radio frequency signal after the first-stage amplification, and finally the second-stage amplified radio frequency signal output by the seventh inductor L7 and the eighth inductor L8 of the second peripheral circuit 203 is induced by the tenth inductor L10 in the signal output unit 205, and the S-end of the tenth inductor L10 is output. The G terminal in fig. 1 is a ground terminal.
Therefore, in the amplifying circuit provided by the invention, the gallium arsenide active device and the silicon-based chip are stacked, and the chips made of two different materials are integrated together, so that heterogeneous integration is realized, the area of the chip is effectively reduced, the defect that the noise performance of the silicon-based amplifier is higher than that of the gallium arsenide amplifier is overcome, and higher integration level and better performance index can be realized at the same time. The gallium arsenide differential pair tube structure can allow the self-bias resistor to be connected between the radio frequency ground and the direct current ground, so that the required bias voltage can be provided, and the noise can be effectively reduced. Terminals of the gallium arsenide differential pair tube structure are distributed in five-point arrangement, so that stacked chips are uniformly stressed and stable in structure. The reliability of the chip is ensured. The MOS differential pair tube enables the source end of the MOS tube to be in a small signal alternating current ground state, effectively eliminates the influence of the bond alloy wire, and avoids noise generated by parasitic resistance of the bond alloy wire from being transmitted to the output end of the amplifier. The gallium arsenide active device is placed at a first stage of the integrated circuit, the silicon-based chip is placed at a second stage of the integrated circuit, and the high gain of the gallium arsenide active device is utilized to suppress noise.
In one application example, in the amplitude-phase multichannel chip, due to the integration of the invention, a low-noise amplifier chip is not required to be externally added separately, and a small-volume phased array antenna unit can be realized.
Wherein, the four-channel amplitude-phase multifunctional chip is designed by adopting a 55nm RFCMOS process. A low noise self-biasing 3D stacked differential amplification circuit is integrated on top of the chip. The following is a comparison of channel noise indexes with and without integrating the stacked low noise amplifier, as shown in fig. 4 and 5, it can be seen that by using the amplifying circuit of the present invention, the noise index is significantly reduced (as shown in fig. 5, the horizontal axis is radio frequency, the vertical axis is noise), and the gain index is significantly improved (as shown in fig. 4, the horizontal axis is radio frequency, the vertical axis is gain), where the comparison scheme is a silicon-based amplifying circuit.
The embodiment of the invention also provides an amplifier, which comprises the amplifying circuit of any embodiment of the invention. The amplifier has advantageous performance of the amplifying circuit.
In summary, according to the amplifying circuit and the amplifier including the same provided by the embodiment of the invention, the amplifying circuit includes: the signal processing circuit comprises a first-stage amplifying circuit arranged on a first chip, a second-stage amplifying circuit arranged on a second chip in sequence, a first peripheral circuit matched with the first-stage amplifying circuit, a second peripheral circuit matched with the second-stage amplifying circuit, a signal access unit and a signal output unit; the first-stage amplifying circuit is vertically interconnected with the first peripheral circuit through a solder ball, and the second-stage amplifying circuit is electrically connected with the second peripheral circuit, wherein the gain of the first-stage amplifying circuit is larger than that of the second-stage amplifying circuit; the method comprises the steps that a radio frequency signal of a sensing signal access unit at one side of a first peripheral circuit forms a first sensing signal, the first sensing signal is amplified by a primary amplifying circuit to form a first amplifying signal, and the first amplifying signal is output from the other side of the first peripheral circuit; sensing the first amplified signal on one side of the second peripheral circuit to form a second sensed signal, amplifying the second sensed signal by the second-stage amplifying circuit to form a second amplified signal, and outputting the second amplified signal on the other side of the second peripheral circuit; the signal output unit senses the second amplified signal and outputs a radio frequency signal amplified twice. Therefore, through a three-dimensional stacking method, the first-stage amplifying circuit arranged on the first chip is connected with the first peripheral circuit arranged on the second chip through welding balls, heterogeneous integration is realized, the transmission loss of radio frequency signals is lower, the stability is better, and the miniaturization of devices is facilitated. And the gain of the primary amplifying circuit is larger than that of the secondary amplifying circuit, so that the influence of noise of the secondary amplifying circuit on the noise of the whole amplifying circuit can be restrained, and the noise of the whole amplifying circuit is further reduced. Therefore, the amplifier comprising the amplifying circuit can simultaneously realize the advantages of low noise, low power consumption and miniaturization, is convenient for large-scale production, and further reduces the production cost.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (11)
1. An amplifying circuit, comprising: a first-stage amplifying circuit provided on the first chip; the second-stage amplifying circuit, the first peripheral circuit matched with the first-stage amplifying circuit, the second peripheral circuit matched with the second-stage amplifying circuit, the signal access unit and the signal output unit are sequentially arranged on the second chip;
the first-stage amplifying circuit is vertically interconnected with the first peripheral circuit through a solder ball, and the second-stage amplifying circuit is electrically connected with the second peripheral circuit, wherein the gain of the first-stage amplifying circuit is larger than that of the second-stage amplifying circuit;
one side of the first peripheral circuit senses the radio frequency signal of the signal access unit to form a first sensing signal, the first sensing signal is amplified by the primary amplifying circuit to form a first amplified signal, and the first amplified signal is output by the other side of the first peripheral circuit; sensing the first amplified signal by one side of the second peripheral circuit to form a second sensed signal, wherein the second sensed signal is amplified by the second-stage amplifying circuit to form a second amplified signal, and the second amplified signal is output by the other side of the second peripheral circuit; the signal output unit senses the second amplified signal and outputs the radio frequency signal amplified twice.
2. The amplifying circuit of claim 1, wherein the first die is a gallium arsenide active device and the second die is a silicon-based die.
3. An amplifying circuit according to claim 1 or 2, wherein the primary amplifying circuit is a differential pair-tube type circuit.
4. The amplifying circuit according to claim 3, wherein the first-stage amplifying circuit comprises a first transistor and a second transistor, a source of the first transistor and a source of the second transistor are electrically connected to form a first end, a gate of the first transistor is a second end, a drain of the first transistor is a third end, a gate of the second transistor is a fourth end, and a drain of the second transistor is a fifth end;
the first peripheral circuit includes five soldering terminals soldered perpendicularly to the first, second, third, fourth and fifth terminals.
5. The amplifier circuit of claim 4, wherein the first peripheral circuit comprises: a first inductor, a second inductor, a third inductor and a fourth inductor; one end of the first inductor is a second welding end welded with the second end, the other end of the first inductor is connected with one end of the second inductor and grounded, and the other end of the second inductor is a third welding end welded with the third end; one end of the third inductor is a fourth welding end welded with the fourth end, the other end of the third inductor and one end of the fourth inductor are connected to a power supply, and the other end of the fourth inductor is a fifth welding end welded with the fifth end;
further comprises: and one end of the bias resistor is a first welding end welded with the first end, and the other end of the bias resistor is grounded.
6. An amplifying circuit according to claim 1 or 2, wherein the secondary amplifying circuit is a differential circuit.
7. The amplifier circuit of claim 6, wherein the second stage amplifier circuit comprises a third transistor and a fourth transistor, a source of the third transistor being connected to ground with a source of the fourth transistor;
and the grid electrode and the drain electrode of the third transistor are electrically connected with the second peripheral circuit.
8. The amplifier circuit of claim 7, wherein the second peripheral circuit comprises: a fifth inductance, a sixth inductance, a seventh inductance, and an eighth inductance; one end of the fifth inductor is connected with the grid electrode of the third transistor, the other end of the fifth inductor is connected with a power supply, and the other end of the sixth inductor is connected with the grid electrode of the fourth transistor; one end of the seventh inductor is connected with the drain electrode of the third transistor, the other end of the seventh inductor is connected with one end of the eighth inductor to a power supply, and the other end of the eighth inductor is connected with the drain electrode of the fourth transistor.
9. The amplifying circuit according to claim 5, wherein the signal access unit includes a ninth inductor, one end of the ninth inductor is used for accessing a radio frequency signal, the other end of the ninth inductor is grounded, and the ninth inductor forms mutual inductance with the first inductor and the second inductor respectively.
10. The amplifying circuit according to claim 8, wherein the signal output unit includes a tenth inductor, one end of the tenth inductor is used for outputting the amplified radio frequency signal, the other end of the tenth inductor is grounded, and the tenth inductor forms mutual inductance with the seventh inductor and the eighth inductor, respectively.
11. An amplifier comprising an amplifying circuit according to any of claims 1-10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310219407.2A CN115940830B (en) | 2023-03-09 | 2023-03-09 | Amplifying circuit and amplifier comprising same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202310219407.2A CN115940830B (en) | 2023-03-09 | 2023-03-09 | Amplifying circuit and amplifier comprising same |
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| CN115940830A CN115940830A (en) | 2023-04-07 |
| CN115940830B true CN115940830B (en) | 2023-05-16 |
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| US7486135B2 (en) * | 2007-05-29 | 2009-02-03 | Telefonaktiebolaget Lm Ericsson (Publ) | Configurable, variable gain LNA for multi-band RF receiver |
| CN206164477U (en) * | 2016-09-21 | 2017-05-10 | 无锡中科微电子工业技术研究院有限责任公司 | Current reuse type high frequency amplifier circuit |
| CN109245735B (en) * | 2018-10-18 | 2023-10-27 | 成都嘉纳海威科技有限责任公司 | High-efficiency J-type stacked power amplifier based on second harmonic injection technology |
| CN213186294U (en) * | 2020-09-28 | 2021-05-11 | 珠海市普斯赛特科技有限公司 | Built-in UHF frequency reduction circuit and frequency reducer |
| JP2022096501A (en) * | 2020-12-17 | 2022-06-29 | 株式会社村田製作所 | Power amplification device and rf circuit module |
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