CN207399176U - A kind of KU wave bands PLL single-chips extended pattern full range frequency demultiplier - Google Patents

Abstract

The utility model discloses a kind of KU wave bands PLL single-chips extended pattern full range frequency demultipliers, including PLL phase-locked loop chips IC3, metal-oxide-semiconductor Q1 and metal-oxide-semiconductor Q3, grid connection capacitance C3, capacitance C7 and the resistance R3 of the metal-oxide-semiconductor Q1, the grid connection resistance R6 of drain electrode, capacitance C6 and the resistance R4 of the other end connection metal-oxide-semiconductor Q2 of capacitance C3, metal-oxide-semiconductor Q2.The utility model uses the mode of oscillation of highly integrated phase-locked loop；This stable double vibrating system are made of phase discriminator, loop filtering, voltage controlled oscillator, frequency multiplication computing etc.；Solve traditional sucrose mode of oscillation frequency is unstable and high and low temperature environment in frequency variation greatly the phenomenon that；The process of manual debugging is eliminated in procedure for producing, save human cost and improves product yield.

Description

A kind of KU wave bands PLL single-chips extended pattern full range frequency demultiplier

Technical field

The utility model is related to a kind of frequency demultipliers, are specifically a kind of KU wave bands PLL single-chips extended pattern full range frequency demultiplier.

Background technology

With science and technology and the development of life, the transmission of communication is also increasingly popularized, and satellite television is watched in family.

Ratio is also higher and higher.Wherein, frequency demultiplier is to watch device essential to satellite television, but current C- ripples on the market In terms of the jamproof ability of its antinoise of the product of section frequency demultiplier and output function, it cannot increasingly meet client's Demand；

With the popularization of satellite television, it is only capable of watching full frequency band TV programme, for sole user end for a LNBF Through cannot increasingly meet customer need；Industrial technology is in continuous progress, the in recent years more and more fierce feelings of market competition Under condition, manufacture cost and design cost test is faced with for enterprise, more and more.

The design structure of conventional satellite frequency demultiplier is limited to, when user receives this 950MHz- using satellite television receiver During 2150MHz intermediate-frequency channel satellite television programmings, a satellite frequency demultiplier can only just be used for a user；(single port exports It is commonly called as:Single head exports), if it is desired to reach more satellite frequency demultipliers for multiple users share, often use one currently on the market The satellite frequency demultiplier of a bull output, such as:The modes such as dual output, four outputs, eight outputs are reached, (dual output, four outputs, eight Output etc. satellite frequency demultipliers price double in the satellite frequency demultiplier singly exported) it is of high cost, user port is limited.And because of coaxial electrical Cable is excessive, installs and connects up cumbersome mixed and disorderly.

Utility model content

The purpose of this utility model is to provide a kind of KU wave bands PLL single-chips extended pattern full range frequency demultiplier, in solution State the problem of being proposed in background technology.

To achieve the above object, the utility model provides following technical solution：

A kind of KU wave bands PLL single-chips extended pattern full range frequency demultiplier, including PLL phase-locked loop chips IC3, metal-oxide-semiconductor Q1 and MOS The leakage of grid connection capacitance C3, the capacitance C7 of pipe Q3, the metal-oxide-semiconductor Q1 and the other end connection metal-oxide-semiconductor Q2 of resistance R3, capacitance C3 Pole, capacitance C6 and resistance R4, other end connection capacitance C11 and PLL the lock phase of grid connection the resistance R6, resistance R6 of metal-oxide-semiconductor Q2 The foot 2 of ring core piece IC3, the foot 1 of the other end connection PLL phase-locked loop chips IC3 of resistance R4, the drain electrode connection capacitance of metal-oxide-semiconductor Q1 C2, capacitance C9 and resistance R7, the foot 32 of the other end connection PLL phase-locked loop chips IC3 of resistance R7, the other end connection of capacitance C2 The foot 34 of PLL phase-locked loop chips IC3 and the foot 35 of PLL phase-locked loop chips IC3, the foot 4 of PLL phase-locked loop chips IC3 connect motor The other end of the connection motor of foot 6 SMD1 of SMD1, PLL phase-locked loop chip IC3, the grid connection capacitance C18 of the metal-oxide-semiconductor Q3, Drain electrode, capacitance C20 and the resistance R11 of the other end connection metal-oxide-semiconductor Q4 of capacitance C22 and resistance R10, capacitance C18, metal-oxide-semiconductor Q4's Grid connects resistance R12, and the foot 8 of the other end connection capacitance C24 and PLL phase-locked loop chip IC3 of resistance R12, resistance R11's is another The foot 9 of one end connection PLL phase-locked loop chips IC3, drain electrode connection capacitance C16, capacitance C23 and the resistance R13 of metal-oxide-semiconductor Q3, resistance The foot 14 of the other end connection PLL phase-locked loop chips IC3 of R13, the foot of the other end connection PLL phase-locked loop chips IC3 of capacitance C16 The foot 12 of 11 and PLL phase-locked loop chips IC3, the foot 23 of PLL phase-locked loop chips IC3 connect cathode, the diode D2 of diode D1 Cathode, the cathode of diode D3 and the cathode of diode D4, diode D1 anode connection capacitance C4 and chip IC 1 pin 3, the pin 1 of chip IC 1 connects capacitance C5 and output port S1, the anode connection capacitance C10 of diode D2 and drawing for chip IC 2 Foot 3, the pin 1 of chip IC 2 connect capacitance C12 and output port S2, the anode connection capacitance C14 and chip IC 4 of diode D3 Pin 3, the pin 1 of chip IC 4 connects capacitance C15 and output port S3, the anode connection capacitance C19 and chip of diode D4 The pin 3 of IC5, the pin 1 of chip IC 5 connect capacitance C21 and output port S4.

Preferred embodiment as the utility model：The model TFF1044 of the PLL phase-locked loop chips IC3.

Preferred embodiment as the utility model：The chip IC 1, chip IC 2, the model of chip IC 4 and chip IC 5 are equal For 78L06.

Compared with prior art, the beneficial effects of the utility model are：1；This reality Patent project uses；Highly integrated lock phase is returned The mode of oscillation on road；This stable double vibrating system are made of phase discriminator, loop filtering, voltage controlled oscillator, frequency multiplication computing etc.；It solves The frequency of traditional sucrose mode of oscillation is unstable and high and low temperature environment in frequency variation greatly the phenomenon that；It is saved in procedure for producing The process of manual debugging has been gone, save human cost and has improved product yield.（Conventional architectures are needed with two dielectrics, cooperation Metal resonance cover.

2；A kind of KU- wave bands PLL single-chips extended pattern full range frequency demultiplier uses；（Figure one）High narrow frequency pectination type microstrip line Road alien frequencies bandpass filter, the single integrated lock phase chip of collocation;Double local oscillators of TFF1044 design outputs 9.75GHz/10.6GHz.It adopts It exported with integrated matrix form amplifying circuit, possess higher saturation tolerance, relatively low saturation distortion, equal with four channels of time-division The design of weighing apparatus output；Using independent electric power system and transmission, prevent to interfere with each other between signal and spread of voltage phenomenon.

3：Due to local oscillator using Single-Chip Integration phase locking unit, so that the interference between local oscillator is preferably minimized（Overcome The interference problem of difference frequency 1700MHz during traditional design, between local oscillator）.Simultaneously using rational wiring rule, by four signal ends Mouth is incorporated on the PCB of one piece of small area；Save space.

4：It designs and TFF1044 is locked in four road independent signal output modes using pull down resistor：V/L、H/L、V/H、 H/H is independently exported using multigroup signal, operating voltage range is big（10V—23V）It can work normally.For user terminal into professional etiquette The extension of pattern.

Description of the drawings

Fig. 1 is the operating diagram of the utility model 1；

Fig. 2 is the structure principle chart of the utility model.

Fig. 3 is the circuit diagram of the utility model.

Specific embodiment

The following is a combination of the drawings in the embodiments of the present utility model, and the technical scheme in the embodiment of the utility model is carried out It clearly and completely describes, it is clear that the described embodiments are only a part of the embodiments of the utility model rather than whole Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are without making creative work All other embodiments obtained shall fall within the protection scope of the present invention.

Please refer to Fig.1-3, in the utility model embodiment, a kind of KU wave bands PLL single-chips extended pattern full range frequency demultiplier, bag Include grid connection capacitance C3, capacitance C7 and the resistance of PLL phase-locked loop chips IC3, metal-oxide-semiconductor Q1 and metal-oxide-semiconductor Q3, the metal-oxide-semiconductor Q1 The grid connection resistance R6 of drain electrode, capacitance C6 and the resistance R4 of the other end connection metal-oxide-semiconductor Q2 of R3, capacitance C3, metal-oxide-semiconductor Q2, electricity Hinder the foot 2 of the other end connection capacitance C11 and PLL phase-locked loop chip IC3 of R6, the other end connection PLL phaselocked loop cores of resistance R4 The foot 1 of piece IC3, drain electrode connection capacitance C2, the capacitance C9 of metal-oxide-semiconductor Q1 and the other end connection PLL phaselocked loops of resistance R7, resistance R7 The foot 32 of chip IC 3, the foot 34 of other end connection PLL phase-locked loop chips IC3 of capacitance C2 and the foot of PLL phase-locked loop chips IC3 The foot 6 that the foot 4 of 35, PLL phase-locked loop chip IC3 connects motor SMD1, PLL phase-locked loop chip IC3 connects the another of motor SMD1 End, grid connection capacitance C18, the capacitance C22 of the metal-oxide-semiconductor Q3 and the other end connection metal-oxide-semiconductor Q4's of resistance R10, capacitance C18 Drain electrode, capacitance C20 and resistance R11, metal-oxide-semiconductor Q4 grid connection resistance R12, resistance R12 other end connection capacitance C24 and The foot 8 of PLL phase-locked loop chips IC3, the foot 9 of the other end connection PLL phase-locked loop chips IC3 of resistance R11, the drain electrode of metal-oxide-semiconductor Q3 Connect the foot 14 of the other end connection PLL phase-locked loop chips IC3 of capacitance C16, capacitance C23 and resistance R13, resistance R13, capacitance The foot 11 of other end connection PLL phase-locked loop chips IC3 of C16 and the foot 12 of PLL phase-locked loop chips IC3, PLL phase-locked loop chips The foot 23 of IC3 connects the cathode of the cathode of diode D1, the cathode of diode D2, the cathode of diode D3 and diode D4, and two The anode connection capacitance C4 of pole pipe D1 and the pin 3 of chip IC 1, the pin 1 of chip IC 1 connect capacitance C5 and output port S1, The anode connection capacitance C10 of diode D2 and the pin 3 of chip IC 2, the pin 1 of chip IC 2 connect capacitance C12 and output port The anode connection capacitance C14 of S2, diode D3 and the pin 3 of chip IC 4, the pin 1 of chip IC 4 connect capacitance C15 and output The anode connection capacitance C19 of port S3, diode D4 and the pin 3 of chip IC 5, the pin 1 of chip IC 5 connect capacitance C21 and Output port S4.

The model TFF1044 of PLL phase-locked loop chips IC3.Chip IC 1, chip IC 2, the type of chip IC 4 and chip IC 5 Number it is 78L06.

The operation principle of the utility model is：As shown in Fig. 2, satellite TV signal letter receives through LNB integrated bodies, is logical Waveguide is crossed by communications protocol frequency band as 10.7GHz --- 12.75GHz satellite TV signals completely import；Through metal structure Being filtered will（Frequency before 10.7GHz, after 12.75GHz）Inhibited and filtered out.Signal is through horizontal polarization and hangs down Straight polarization both of which is received；Amplify through level-one, two level amplification, micro-strip high-pass filtering, the integrated lock phase of the output of single-chip four Device, through narrow ripple alien frequencies suppression circuit:Export four patterns：V/L, H/L, V/H, H/H are expanded respectively by four port outputs for user terminal Exhibition uses.

Physical circuit is as shown in figure 3, satellite-signal receives through H/ horizontal polarizations probe, is input to first order MOS-FET （CKRF7513）- 0.3V--0.5V electricity needed for Q2 carries out low noise amplification, its VGS is provided after C11 is filtered, is depressured by R6 Pressure；VDS voltages are filtered through C6, dropping resistor R4 offer+2V voltages make it be operated in optimum state.Amplified signal has C3 It is coupled to Q1, carries out secondary amplification；It is made there are enough power driving signals to transmit.The coupled capacitance C2 of signal is exported to micro-strip height Pass filter filters out out of band signal；And it inputs to Single-Chip Integration phase locking unit（TFF1044）34th, 35 pins while and SMD1 （25MHz crystal oscillators）It is compared, frequency multiplication computing etc., obtains double local oscillators of 9.75GHz/10.6GHz；Be mixed through inside, The intermediate-freuqncy signal of 950MHz -2150MHZ is exported after amplification;Fixed V/L full ranges end signal is exported through the 28th foot positions of IC；It passes through again C1 coupling isolation outputs.Isolate output by the 26th feet of IC output V/H signals, through C13 capacitive couplings simultaneously.

Its VGS provides required -0.3V--0.5V voltages after C24 is filtered, is depressured by R12；VDS voltages are filtered through C20 Ripple, dropping resistor R11 offer+2V voltages make it be operated in optimum state.Amplified signal has C18 to be coupled to Q3, carry out Secondary amplification；It is made there are enough power driving signals to transmit.The coupled capacitance C2 of signal is exported will be with outer to micro-strip high-pass filtering Target signal filter；And it inputs to Single-Chip Integration phase locking unit（TFF1044）11st, 12 pins while and SMD1（25MHz crystal shakes Swing device）It is compared, frequency multiplication computing etc., obtains double local oscillators of 9.75GHz/10.6GHz；It is exported after inside mixing, amplification The intermediate-freuqncy signal of 950MHz -2150MHZ;Fixed H/L full ranges end signal is exported through the 23rd foot positions of IC；It couples and isolates through C1 again Output.Isolate output by the 18th feet of IC output H/H signals, through C8 capacitive couplings simultaneously.

Claims (3)

1. a kind of KU wave bands PLL single-chips extended pattern full range frequency demultiplier, including PLL phase-locked loop chips IC3, metal-oxide-semiconductor Q1 and metal-oxide-semiconductor Q3, which is characterized in that grid connection capacitance C3, the capacitance C7 of the metal-oxide-semiconductor Q1 and the other end connection of resistance R3, capacitance C3 The other end connection capacitance of grid connection the resistance R6, resistance R6 of drain electrode, capacitance C6 and the resistance R4 of metal-oxide-semiconductor Q2, metal-oxide-semiconductor Q2 The foot 2 of C11 and PLL phase-locked loop chips IC3, the foot 1 of the other end connection PLL phase-locked loop chips IC3 of resistance R4, metal-oxide-semiconductor Q1's The foot 32 of the other end connection PLL phase-locked loop chips IC3 of drain electrode connection capacitance C2, capacitance C9 and resistance R7, resistance R7, capacitance C2 The foot 34 of other end connection PLL phase-locked loop chips IC3 and the foot 35 of PLL phase-locked loop chips IC3, PLL phase-locked loop chips IC3's Foot 4 connects the other end of the connection motor of foot 6 SMD1 of motor SMD1, PLL phase-locked loop chip IC3, and the grid of the metal-oxide-semiconductor Q3 connects Capacitance C18, capacitance C22 and resistance R10 are met, the other end of capacitance C18 connects drain electrode, capacitance C20 and the resistance R11 of metal-oxide-semiconductor Q4, The foot 8 of the other end connection capacitance C24 and PLL phase-locked loop chip IC3 of grid connection the resistance R12, resistance R12 of metal-oxide-semiconductor Q4, electricity Hinder the foot 9 of the other end connection PLL phase-locked loop chips IC3 of R11, drain electrode connection capacitance C16, capacitance C23 and the resistance of metal-oxide-semiconductor Q3 The foot 14 of the other end connection PLL phase-locked loop chips IC3 of R13, resistance R13, the other end connection PLL phaselocked loop cores of capacitance C16 The foot 11 of piece IC3 and the foot 12 of PLL phase-locked loop chips IC3, the cathode of the connection diode of foot 23 D1 of PLL phase-locked loop chips IC3, The cathode of the cathode of diode D2, the cathode of diode D3 and diode D4, the anode connection capacitance C4 and chip of diode D1 The pin 3 of IC1, the pin 1 of chip IC 1 connect capacitance C5 and output port S1, the anode connection capacitance C10 and core of diode D2 The pin 3 of piece IC2, the pin 1 of chip IC 2 connect capacitance C12 and output port S2, the anode connection capacitance C14 of diode D3 With the pin 3 of chip IC 4, the pin 1 of chip IC 4 connects capacitance C15 and output port S3, the anode connection capacitance of diode D4 C19 and the pin of chip IC 53, the pin 1 of chip IC 5 connect capacitance C21 and output port S4.

2. KU wave bands PLL single-chips extended pattern full range frequency demultiplier according to claim 1, which is characterized in that the PLL locks The model TFF1044 of phase ring core piece IC3.

3. KU wave bands PLL single-chips extended pattern full range frequency demultiplier according to claim 1, which is characterized in that the chip IC1, chip IC 2, the model of chip IC 4 and chip IC 5 are 78L06.