CN216390915U - C-band dual-polarization single-local-oscillator single-output frequency demultiplier - Google Patents

Abstract

The utility model discloses a C-band dual-polarization single-local-oscillator single-output frequency demultiplier, wherein a signal output end of a vertical polarization antenna is connected with one signal input end of a combiner coupler through a vertical first-stage low-noise amplifier, a signal output end of a horizontal polarization antenna is connected with the other signal input end of the combiner coupler through a horizontal first-stage low-noise amplifier, a signal output end of the combiner coupler is connected with a signal input end of a 3.7GHz-4.2GHz band-pass filter through a second-stage low-noise amplifier, a signal output end of the band-pass filter is connected with a signal input end of a 950MHz-1450MHz band-pass filter through a phase-locked loop, and a signal output end of the 950MHz-1450MHz band-pass filter is connected with a corresponding signal input end of a video set top box. The frequency converter has the advantages of strong anti-interference capability, no interference of 5G adjacent frequency and the like.

Description

C-band dual-polarization single-local-oscillator single-output frequency demultiplier

Technical Field

The utility model relates to the technical field of television signal processing devices, in particular to a C-band double-local-oscillator dual-polarization single-output frequency demultiplier.

Background

The working principle of satellite antenna receiving satellite television is to collect weak satellite signals by using the satellite antenna and reflect the satellite signals to a low-noise frequency demultiplier arranged at the focus of a dish antenna. Then, a low noise block down converter amplifies the concentrated signal and reduces the rf frequency to an intermediate frequency of 950MHz to 1450MHz, which is then transmitted to an indoor receiver or digital set top box via a cable. The receiver selects the channel to be watched in the signal, and after the signal is amplified, demodulated and restored into image and sound signals, the image and sound signals are input into a television to play programs. The circuit of the early frequency demultiplier has weak interference resistance, such as 5G signals in the 5G era: 3.4GHz, 3.5GHz, 3.6GHz, 4.8GHZ all have the interference to previous product, and the viewer watches TV program and can all appear interfering mosaic, cause and use inconveniently, watch the effect poorly.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem of how to provide a C-band double-local-oscillator dual-polarization single-output frequency demultiplier which has strong anti-interference capability and is not interfered by 5G adjacent frequency.

In order to solve the technical problems, the technical scheme adopted by the utility model is as follows: the utility model provides a two local oscillator double polarization single output frequency demultipliers of C wave band which characterized in that: the signal output end of the vertical polarization antenna is connected with one signal input end of the combining coupler through a vertical first-stage low noise amplifier, the signal output end of the horizontal polarization antenna is connected with the other signal input end of the combining coupler through a horizontal first-stage low noise amplifier, the signal output end of the combining coupler is connected with the signal input end of a 3.7GHz-4.2GHz band-pass filter through a second-stage low noise amplifier, the signal output end of the band-pass filter is connected with the signal input end of a 950MHz-1450MHz band-pass filter through a phase-locked loop, and the signal output end of the 950MHz-1450MHz band-pass filter is connected with the corresponding signal input end of the video set top box.

The further technical scheme is as follows: the frequency demultiplier comprises field effect transistors Q1 and Q2, the grid of the Q1 is divided into three paths, the first path is connected with the signal output end of the vertical polarization antenna, the second path is grounded through a resistor R1, and the third path is grounded through a resistor R2 and a capacitor C1 in sequence; the source of the Q1 is grounded, the drain of the Q1 is divided into two paths, the first path is grounded through a capacitor C4, and the second path is connected with one input end of the combiner coupler through a capacitor C5;

the grid of the Q2 is divided into three paths, the first path is connected with the signal output end of the horizontal polarization antenna, the second path is grounded through a resistor R11, and the third path is grounded through a resistor R12 and a capacitor C14 in sequence; the source of the Q2 is grounded, the drain of the Q2 is divided into two paths, the first path is grounded through a capacitor C15, and the second path is connected with the other input end of the combiner coupler through a capacitor C6;

the output end of the combining coupler is divided into three paths, the first path is grounded through a resistor R5, the second path is grounded through a resistor R4 and a capacitor C8 in sequence, the third path is connected with the grid electrode of a field-effect tube Q3, and the source electrode of the Q3 is grounded; the drain of the Q3 is divided into three paths, the first path is grounded through a capacitor C9, the second path is connected with a pin 13 of an RDA3570 type chip, and the third path is connected with a pin 2 of the RDA3570 after sequentially passing through a capacitor C10 and a 3.7GHz-4.2GHz band-pass filter;

pins 1, 3, 7 and 9 of the RDA3570 are grounded; the 5 pin of the RDA3570 is connected with a node of the capacitor C14 and the resistor R12; the pin 6 of the RDA3570 is connected with a junction of a resistor R13 and a capacitor C16; the pin 8 of the RDA3570 is connected with the corresponding signal input end of the video set-top box through capacitors C17, C18, C20, C22 and C23 in sequence; the pin 10 of the RDA3570 is connected with the corresponding signal input end of the video set-top box after sequentially passing through a resistor R7, a resistor R9 and a diode D1; the pin 13 of the RDA3570 is connected with a junction point of a resistor R4 and a capacitor C8; the 11 pins of the RDA3570 are divided into two paths, the first path is grounded through a capacitor C11, and the second path is connected with the 3 pins of a 78H06 type power supply chip.

Adopt the produced beneficial effect of above-mentioned technical scheme to lie in: the frequency demultiplier adopts a multistage band-pass filter, has super-strong anti-interference capability, is economical and practical, and is not interfered by 5G adjacent frequency.

Drawings

The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

Fig. 1 is a schematic block diagram of a frequency converter according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a frequency converter according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.

As shown in fig. 1, the embodiment of the present invention discloses a C-band dual-polarized single-local-oscillator single-output frequency demultiplier, which is characterized in that: the signal output end of the vertical polarization antenna is connected with one signal input end of the combining coupler through a vertical first-stage low noise amplifier, the signal output end of the horizontal polarization antenna is connected with the other signal input end of the combining coupler through a horizontal first-stage low noise amplifier, the signal output end of the combining coupler is connected with the signal input end of a 3.7GHz-4.2GHz band-pass filter through a second-stage low noise amplifier, the signal output end of the band-pass filter is connected with the signal input end of a 950MHz-1450MHz band-pass filter through a phase-locked loop, and the signal output end of the 950MHz-1450MHz band-pass filter is connected with the corresponding signal input end of the video set top box.

Further, as shown in fig. 2, the frequency demultiplier includes field effect transistors Q1 and Q2, the gate of Q1 is divided into three paths, the first path is connected to the signal output terminal of the vertical polarization antenna, the second path is grounded via a resistor R1, and the third path is grounded via a resistor R2 and a capacitor C1 in sequence; the source of the Q1 is grounded, the drain of the Q1 is divided into two paths, the first path is grounded through a capacitor C4, and the second path is connected with one input end of the combiner coupler through a capacitor C5;

the grid of the Q2 is divided into three paths, the first path is connected with the signal output end of the horizontal polarization antenna, the second path is grounded through a resistor R11, and the third path is grounded through a resistor R12 and a capacitor C14 in sequence; the source of the Q2 is grounded, the drain of the Q2 is divided into two paths, the first path is grounded through a capacitor C15, and the second path is connected with the other input end of the combiner coupler through a capacitor C6;

the output end of the combining coupler is divided into three paths, the first path is grounded through a resistor R5, the second path is grounded through a resistor R4 and a capacitor C8 in sequence, the third path is connected with the grid electrode of a field-effect tube Q3, and the source electrode of the Q3 is grounded; the drain of the Q3 is divided into three paths, the first path is grounded through a capacitor C9, the second path is connected with a pin 13 of an RDA3570 type chip, and the third path is connected with a pin 2 of the RDA3570 after sequentially passing through a capacitor C10 and a 3.7GHz-4.2GHz band-pass filter;

pins 1, 3, 7 and 9 of the RDA3570 are grounded; the 5 pin of the RDA3570 is connected with a node of the capacitor C14 and the resistor R12; the pin 6 of the RDA3570 is connected with a junction of a resistor R13 and a capacitor C16; the pin 8 of the RDA3570 is connected with the corresponding signal input end of the video set-top box through capacitors C17, C18, C20, C22 and C23 in sequence; the pin 10 of the RDA3570 is connected with the corresponding signal input end of the video set-top box after sequentially passing through a resistor R7, a resistor R9 and a diode D1; the pin 13 of the RDA3570 is connected with a junction point of a resistor R4 and a capacitor C8; the 11 pins of the RDA3570 are divided into two paths, the first path is grounded through a capacitor C11, and the second path is connected with the 3 pins of a 78H06 type power supply chip.

The working principle is that a vertical signal and a horizontal signal are controlled by a set top box to a first-stage low noise amplifier, the signals are respectively transmitted to two input ends of a combiner coupler in turn, the signals are transmitted to a second-stage low noise amplifier after being combined, the amplified signals are strictly controlled to be 3.7GHz-4.2GHz in receiving frequency bandwidth through a multi-stage microstrip hairpin band-pass filter or a multi-stage hairpin band-pass filter and an LC band-pass filter, the amplified signals enter the LC band-pass filter (950 MHz-1450MHz) for output after being subjected to difference frequency by an oscillation and frequency mixing integrated IC (RDA 3570), and then the output signals are accessed to a C-band satellite television set top box through a high-frequency feeder line of at least 1.5 GHz.

Claims (2)

1. The utility model provides a C wave band double polarization single local oscillator single output frequency demultiplier which characterized in that: the signal output end of the vertical polarization antenna is connected with one signal input end of the combining coupler through a vertical first-stage low noise amplifier, the signal output end of the horizontal polarization antenna is connected with the other signal input end of the combining coupler through a horizontal first-stage low noise amplifier, the signal output end of the combining coupler is connected with the signal input end of a 3.7GHz-4.2GHz band-pass filter through a second-stage low noise amplifier, the signal output end of the band-pass filter is connected with the signal input end of a 950MHz-1450MHz band-pass filter through a phase-locked loop, and the signal output end of the 950MHz-1450MHz band-pass filter is connected with the corresponding signal input end of the video set top box.

2. The C-band dual-polarized single-local-oscillator single-output frequency demultiplier according to claim 1, wherein:

the antenna comprises field effect transistors Q1 and Q2, the grid of Q1 is divided into three paths, the first path is connected with the signal output end of the vertical polarization antenna, the second path is grounded through a resistor R1, and the third path is grounded through a resistor R2 and a capacitor C1 in sequence; the source of the Q1 is grounded, the drain of the Q1 is divided into two paths, the first path is grounded through a capacitor C4, and the second path is connected with one input end of the combiner coupler through a capacitor C5;

the grid of the Q2 is divided into three paths, the first path is connected with the signal output end of the horizontal polarization antenna, the second path is grounded through a resistor R11, and the third path is grounded through a resistor R12 and a capacitor C14 in sequence; the source of the Q2 is grounded, the drain of the Q2 is divided into two paths, the first path is grounded through a capacitor C15, and the second path is connected with the other input end of the combiner coupler through a capacitor C6;

the output end of the combining coupler is divided into three paths, the first path is grounded through a resistor R5, the second path is grounded through a resistor R4 and a capacitor C8 in sequence, the third path is connected with the grid electrode of a field-effect tube Q3, and the source electrode of the Q3 is grounded; the drain of the Q3 is divided into three paths, the first path is grounded through a capacitor C9, the second path is connected with a pin 13 of an RDA3570 type chip, and the third path is connected with a pin 2 of the RDA3570 after sequentially passing through a capacitor C10 and a 3.7GHz-4.2GHz band-pass filter;

pins 1, 3, 7 and 9 of the RDA3570 are grounded; the 5 pin of the RDA3570 is connected with a node of the capacitor C14 and the resistor R12; the pin 6 of the RDA3570 is connected with a junction of a resistor R13 and a capacitor C16; the pin 8 of the RDA3570 is connected with the corresponding signal input end of the video set-top box through capacitors C17, C18, C20, C22 and C23 in sequence; the pin 10 of the RDA3570 is connected with the corresponding signal input end of the video set-top box after sequentially passing through a resistor R7, a resistor R9 and a diode D1; the pin 13 of the RDA3570 is connected with a junction point of a resistor R4 and a capacitor C8; the 11 pins of the RDA3570 are divided into two paths, the first path is grounded through a capacitor C11, and the second path is connected with the 3 pins of a 78H06 type power supply chip.

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