CN203911873U - Dual polarization Twin PLL integrated circuit dual output frequency demultiplier - Google Patents
Dual polarization Twin PLL integrated circuit dual output frequency demultiplier Download PDFInfo
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- CN203911873U CN203911873U CN201420211958.0U CN201420211958U CN203911873U CN 203911873 U CN203911873 U CN 203911873U CN 201420211958 U CN201420211958 U CN 201420211958U CN 203911873 U CN203911873 U CN 203911873U
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Abstract
The utility model provides a dual polarization Twin PLL integrated circuit dual output frequency demultiplier, comprising a waveguide tube, a reflection rod, a polarized antenna, a first stage amplification module, a second stage amplification module and a filtering module which are successively communicated with the polarized antenna, and an integrated circuit, and characterized in that the first stage amplification module, the second stage amplification module and the filtering module form a filtering channel; the filtering channel is provided with a first filtering output and a second filtering output outputted to the integrated circuit; the integrated circuit is symmetrically provided with a first frequency reduction channel and a second frequency reduction channel; each frequency reduction channel respectively comprises a bias circuit, a Tone voltage detecting control circuit, a mixed circuit, and an intermediate frequency amplifier. The dual polarization Twin PLL integrated circuit dual output frequency demultiplier has the characteristics of practical and varied functions, stable output frequency, simple structure, etc.
Description
Technical field
The utility model belongs to short-wave communication tedhnology field, relates in particular to a kind of double polarization T win PLL integrated circuit (IC) design dual output frequency demultiplier that is applied to satellite communication field.
Background technology
In recent years, telstar receiver flourish, countries in the world are develop actively live telecast satellite (DVB-S) invariably, driven the industry development of wireless high-frequency communication system thereupon, also make domestic and international satellite digital television receiving system industry flourish, not only for China, earn a large amount of foreign exchanges every year, also increase domestic careers market.The wave bands such as dbs receiver frequency of utilization frequency band Ku, C, S, the downward signal of satellite of each wave band is first by antenna reception, again through the amplification of tuner and the first intermediate-freuqncy signal of down-conversion formation 950MHz-2150MHz, then through cable, be sent to the high-frequency tuner of receiver, high-frequency tuner is according to the frequency of required reception, by PLL (phase-locked loop) loop, control local oscillator frequency, input signal frequency conversion is become to the second intermediate-freuqncy signal of 479.5MHz, after processing finally by the signal by receiver, television set broadcasts signal of video signal and audio signal.
At present, the existing Ku wave band telstar low noise frequency reducing amplifier that contains a radiofrequency signal output or two radiofrequency signal outputs all uses traditional circuit design, be that circuit is by separate type module composition, as shown in Figure 1, include low noise amplifier, Ku wave band cavity oscillator, Ku wave band mixer and intermediate frequency amplifier, for example telstar on the market receives low noise amplifier Ku-Band, it adopts separate type module composition, it is cavity oscillator, intermediate frequency triode amplifier and voltage control integrated circuit, line construction is comparatively complicated, frequency of oscillation is easily drifted about, between the components and parts of separate type, easily disturb, cause output frequency unstable, television image is unintelligible, unstable, and line construction is complicated, technological process is comparatively complicated, production difficulty is large, production process fraction defective is higher, defective products is many, all causes very large waste, in addition at human and material resources with on the time, the screw that these amplifiers all will be adjusted on dielectric cavity oscillator could be realized frequency adjustment, uses, operates extremely inconvenient.
Utility model content
In order to solve the above-mentioned technical problem existing in prior art, the utility model provides that a kind of output frequency is stable and simple in structure, the double polarization T win PLL integrated circuit (IC) design dual output frequency demultiplier of multi-functional.
The technical scheme that the utility model solution prior art problem adopts is:
A kind of double polarization T win PLL integrated circuit dual output frequency demultiplier, comprise waveguide, reflection rod, poliarizing antenna and first order amplification module, second level amplification module, filtration module and the integrated circuit of poliarizing antenna described in conducting successively, described first order amplification module, second level amplification module and filtration module form filtering channel, and described filtering channel has the first filtering output and the second filtering output that exports described integrated circuit to; Described integrated circuit is arranged with the first frequency reducing passage and the second frequency reducing passage, and each frequency reducing passage comprises respectively bias circuit, Tone detecting voltage control circuit, mixed circuit and intermediate frequency amplifier.
The technical solution of the utility model is further described below:
Described mixed circuit and intermediate frequency amplifier are serially connected with between the input and output of frequency reducing passage successively, described Tone detecting voltage control circuit obtains the frequency reducing channel output end signal of telecommunication, through bias circuit, feeds back to first order amplification module or second level amplification module.
Further, described mixed circuit comprises frequency mixer, PLL phase-locked loop and oscillator.
As preferred version of the present utility model, described integrated circuit is provided with reference frequency input port, and described reference frequency input port is the complementary metal oxide semiconductors (CMOS) being integrated in integrated circuit, and described oscillator shares described reference frequency input port.
Further, between the input of described integrated circuit and filtration module output, be provided with polarization interchanger; Described polarization interchanger has a control end, realizes horizontal polarization and the perpendicular polarization of integrated circuit input end signal exchange by changing the incoming level of this control end.
Further, described first order amplification module comprises the first amplifier and the second amplifier; Described the second amplification module comprises the 3rd amplifier, the 4th amplifier, the 5th amplifier and the 6th amplifier; The input of described the first amplifier receives the perpendicular polarization output of poliarizing antenna, and the output of described the first amplifier connects respectively the input of the 3rd amplifier, the 5th amplifier; The input of described the second amplifier receives the horizontal polarization output of poliarizing antenna, and the output of described the second amplifier connects respectively the input of the 4th amplifier, the 6th amplifier; Described the 3rd amplifier is connected described filter with the output of the 4th amplifier, and after filtering, generates the first filtering output; Described the 5th amplifier is connected described filter with the output of the 6th amplifier, and after filtering, generates the second filtering output.
As preferred version of the present utility model, described the first amplifier, the second amplifier, the 3rd amplifier, the 4th amplifier, the 5th amplifier and the 6th amplifier are microwave field effect triode or SiGe triode.
As preferred version of the present utility model, described poliarizing antenna comprises horizontally-polarized antenna and vertical polarized antenna; The length of described horizontally-polarized antenna is the quarter-wave of certain frequency in Ku wave band, and its placement location is the quarter-wave of certain frequency in Ku wave band apart from the tube wall of waveguide; The length of described vertical polarized antenna is the quarter-wave of certain frequency in Ku wave band, and its placement location is the quarter-wave of certain frequency in Ku wave band apart from reflection rod.
As preferred version of the present utility model, described filtration module is band pass filter.
Compared with prior art, its superiority is embodied in the utility model:
1, adopt integrated integrated circuit to replace low noise amplifier, Ku wave band cavity oscillator, Ku wave band mixer and the intermediate frequency amplifier of traditional separation design, line construction is simplified greatly, and production difficulty and product fraction defective are also obviously reduced thereupon.
2, in circuit structure, added the design of new symmetrical architecture, allowed input wave band is more versatile and flexible with output kenel, output frequency stable.
3, on the circuit of dual output frequency demultiplier, done great innovation, adopt built-in polarization interchanger design, solution need to be revised the circuit structure problem of wave band cavity oscillator, wave band mixer, intermediate frequency amplifier etc. because of frequency demultiplier body kenel difference, saves time, laborsaving and be difficult for makeing mistakes.
4, when producing can for multiaspect more to customer demand, more can under dual output pattern, allow two users can select horizontal polarization low-frequency range, the output of horizontal polarization high band or the output of perpendicular polarization low-frequency range, the output of perpendicular polarization high band simultaneously simultaneously, use easy to operate.
Accompanying drawing explanation
Fig. 1 is traditional double output frequency demultiplier structural map.
Fig. 2 is composition framework schematic diagram of the present utility model.
Fig. 3 is that mixed circuit forms framework schematic diagram.
Fig. 4 is organigram of the present utility model.
Embodiment
As follows by reference to the accompanying drawings, the application's scheme is further described:
As shown in Figure 2, a kind of double polarization T win PLL integrated circuit dual output frequency demultiplier, comprise waveguide, reflection rod, poliarizing antenna and first order amplification module 1, second level amplification module 2, filtration module 3 and the integrated circuit 4 of poliarizing antenna described in conducting successively, described first order amplification module 1, second level amplification module 2 form filtering channel 10 with filtration module 3, and described filtering channel 10 has first filtering output the 101 and second filtering output 102 that exports described integrated circuit to; Described integrated circuit 4 is arranged with the first frequency reducing passage 41 and the second frequency reducing passage 42, and described the first frequency reducing passage 41 comprises bias circuit 41-1, Tone detecting voltage control circuit 41-2, mixed circuit 41-3 and intermediate frequency amplifier 41-4; Described the second frequency reducing passage 42 comprises bias circuit 42-1, Tone detecting voltage control circuit 42-2, mixed circuit 42-3 and intermediate frequency amplifier 42-4.
In the first frequency reducing passage 41, described mixed circuit 41-3 and intermediate frequency amplifier 41-4 are serially connected with between the input 411 and output 412 of the first frequency reducing passage 41 successively, described Tone detecting voltage control circuit 41-2 obtains frequency reducing channel output end 412 signals of telecommunication, through bias circuit 41-1, feeds back to first order amplification module 1 or second level amplification module 2.
In the second frequency reducing passage 42, described mixed circuit 42-3 and intermediate frequency amplifier 42-4 are serially connected with between the input 413 and output 414 of the second frequency reducing passage 42 successively, described Tone detecting voltage control circuit 42-2 obtains frequency reducing channel output end 414 signals of telecommunication, through bias circuit 42-1, feeds back to first order amplification module 1 or second level amplification module 2.
As shown in Figure 3, in described the first frequency reducing passage 41, described mixed circuit 41-3 comprises frequency mixer 41-3-1, PLL phase-locked loop 41-3-2 and oscillator 41-3-3; In described the second frequency reducing passage 42, its mixed circuit 42-3 forms identical with the mixed circuit of described the first frequency reducing passage 41.
As shown in Figure 4, described integrated circuit 4 is provided with reference frequency input port 413, and described reference frequency input port 413 is for to be integrated in the complementary metal oxide semiconductors (CMOS) in integrated circuit 4, and described oscillator 41-3-3 shares described reference frequency input port 413.
Between the input 411 of described integrated circuit 4 and filtration module 3 outputs, be provided with polarization interchanger 5; Described polarization interchanger 5 has a control end 51, realizes horizontal polarization and the perpendicular polarization of integrated circuit input end 411 signals exchange by changing the incoming level of this control end 51.
Described first order amplification module 1 comprises the first amplifier 11 and the second amplifier 12; Described the second amplification module 2 comprises the 3rd amplifier 21, the 4th amplifier 22, the 5th amplifier 23 and the 6th amplifier 24:
The input of described the first amplifier 11 receives the perpendicular polarization output of poliarizing antenna, and the output of described the first amplifier 11 connects respectively the input of the 3rd amplifier 21, the 5th amplifier 23;
The input of described the second amplifier 12 receives the horizontal polarization output of poliarizing antenna, and the output of described the second amplifier 12 connects respectively the input of the 4th amplifier 22, the 6th amplifier 24;
Described the 3rd amplifier 21 is connected described filtration module 3 with the output of the 4th amplifier 24, and after filtering, generates the first filtering output 301; Described the 5th amplifier is connected described filtration module 3 with the output of the 6th amplifier, and after filtering, generates the second filtering output 302.
Described the first amplifier 11, the second amplifier 12, the 3rd amplifier 21, the 4th amplifier 22, the 5th amplifier 23 and the 6th amplifier 24 are microwave field effect triode or SiGe triode.
Described poliarizing antenna comprises horizontally-polarized antenna and vertical polarized antenna;
The length of described horizontally-polarized antenna is the quarter-wave (2.3cm～2.5cm) of certain frequency in Ku wave band (11.7GHz～12.7GHz), i.e. 0.575cm～0.625cm; Its placement location is the quarter-wave (2.3cm～2.5cm) of certain frequency in Ku wave band (11.7GHz～12.7GHz) apart from the tube wall of waveguide (not showing in figure), be 0.575cm～0.625cm, to reach the effect that signal strength signal intensity is the strongest.
The length of described vertical polarized antenna is the quarter-wave (2.3cm～2.5cm) of certain frequency in Ku wave band (11.7GHz～12.7GHz), i.e. 0.575cm～0.625cm; And its placement location is the quarter-wave (2.3cm～2.5cm) for certain frequency (11.7GHz～12.7GHz) in Ku wave band apart from reflection rod (not showing in figure), be 0.575cm～0.625cm, to reach the effect that signal strength signal intensity is the strongest.
Described reflection rod is similarly 1/4th times of wavelength (2.3cm～2.5cm) of certain frequency in Ku wave band (11.7GHz～12.7GHz) apart from wave guide wall, 0.575cm～0.625cm is to reach the effect that signal strength signal intensity is the strongest.
Described filtration module 3 is band pass filter.
Above-mentioned preferred implementation should be considered as illustrating of the application's scheme implementation mode, and identical, the approximate or technology deduction made based on this of all and the application's scheme, replacement, improvement etc. all should be considered as the protection range of this patent.
Claims (9)
1. a double polarization T win PLL integrated circuit dual output frequency demultiplier, comprise waveguide, reflection rod, poliarizing antenna and first order amplification module, second level amplification module, filtration module and the integrated circuit of poliarizing antenna described in conducting successively, it is characterized in that: described first order amplification module, second level amplification module and filtration module form filtering channel, described filtering channel has the first filtering output and the second filtering output that exports described integrated circuit to; Described integrated circuit is arranged with the first frequency reducing passage and the second frequency reducing passage, and each frequency reducing passage comprises respectively bias circuit, Tone detecting voltage control circuit, mixed circuit and intermediate frequency amplifier.
2. double polarization T win PLL integrated circuit dual output frequency demultiplier according to claim 1, it is characterized in that: described mixed circuit and intermediate frequency amplifier are serially connected with between the input and output of frequency reducing passage successively, described Tone detecting voltage control circuit obtains the frequency reducing channel output end signal of telecommunication, through bias circuit, feeds back to first order amplification module or second level amplification module.
3. double polarization T win PLL integrated circuit dual output frequency demultiplier according to claim 2, is characterized in that: described mixed circuit comprises frequency mixer, PLL phase-locked loop and oscillator.
4. double polarization T win PLL integrated circuit dual output frequency demultiplier according to claim 3, it is characterized in that: described integrated circuit is provided with reference frequency input port, described reference frequency input port is the complementary metal oxide semiconductors (CMOS) being integrated in integrated circuit, and described oscillator shares described reference frequency input port.
5. double polarization T win PLL integrated circuit dual output frequency demultiplier according to claim 4, is characterized in that: between the input of described integrated circuit and filtration module output, be provided with polarization interchanger; Described polarization interchanger has a control end, realizes horizontal polarization and the perpendicular polarization of integrated circuit input end signal exchange by changing the incoming level of this control end.
6. double polarization T win PLL integrated circuit dual output frequency demultiplier according to claim 5, is characterized in that: described first order amplification module comprises the first amplifier and the second amplifier; Described the second amplification module comprises the 3rd amplifier, the 4th amplifier, the 5th amplifier and the 6th amplifier; The input of described the first amplifier receives the perpendicular polarization output of poliarizing antenna, and the output of described the first amplifier connects respectively the input of the 3rd amplifier, the 5th amplifier; The input of described the second amplifier receives the horizontal polarization output of poliarizing antenna, and the output of described the second amplifier connects respectively the input of the 4th amplifier, the 6th amplifier; Described the 3rd amplifier is connected described filtration module with the output of the 4th amplifier, and after filtering, generates the first filtering output; Described the 5th amplifier is connected described filtration module with the output of the 6th amplifier, and after filtering, generates the second filtering output.
7. double polarization T win PLL integrated circuit dual output frequency demultiplier according to claim 6, is characterized in that: described the first amplifier, the second amplifier, the 3rd amplifier, the 4th amplifier, the 5th amplifier and the 6th amplifier are microwave field effect triode or SiGe triode.
8. according to the double polarization T win PLL integrated circuit dual output frequency demultiplier described in claim 1-7 any one, it is characterized in that: described poliarizing antenna comprises horizontally-polarized antenna and vertical polarized antenna; The length of described horizontally-polarized antenna is the quarter-wave of certain frequency in Ku wave band, and its placement location is the quarter-wave of certain frequency in Ku wave band apart from the tube wall of waveguide; The length of described vertical polarized antenna is the quarter-wave of certain frequency in Ku wave band, and its placement location is the quarter-wave of certain frequency in Ku wave band apart from reflection rod.
9. according to the double polarization T win PLL integrated circuit dual output frequency demultiplier described in claim 1-7 any one, it is characterized in that: described filtration module is band pass filter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420211958.0U CN203911873U (en) | 2014-04-28 | 2014-04-28 | Dual polarization Twin PLL integrated circuit dual output frequency demultiplier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420211958.0U CN203911873U (en) | 2014-04-28 | 2014-04-28 | Dual polarization Twin PLL integrated circuit dual output frequency demultiplier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203911873U true CN203911873U (en) | 2014-10-29 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420211958.0U Expired - Fee Related CN203911873U (en) | 2014-04-28 | 2014-04-28 | Dual polarization Twin PLL integrated circuit dual output frequency demultiplier |
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| Country | Link |
|---|---|
| CN (1) | CN203911873U (en) |
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2014
- 2014-04-28 CN CN201420211958.0U patent/CN203911873U/en not_active Expired - Fee Related
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20141029 Termination date: 20170428 |
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| CF01 | Termination of patent right due to non-payment of annual fee |