JPH0541664A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To obtain the frequency synthesizer facilitating the selection of the tuning frequency in a digital tuning system and reducing the burden of a microcomputer or the like setting N value or the like of dividing. CONSTITUTION:Dividing data 105 is inputted to a dividing data storage circuit 1 through the prescribed data line. On the other hand, the storage address of the dividing data is outputted from an address designation circuit 6 through the prescribed control signal 104, to be inputted to the dividing data storage circuit 1. In the dividing data storage circuit 1, the dividing data corresponding to the storage address is read out, to be inputted to a programmable divider 2. In the programmable divider 2, the N value corresponding to the dividing data is set, and the frequency of the output signal 102 is set through the synchronization in the phase synchronization system, and the arbitrary channel selection is performed.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a frequency synthesizer.

[0002]

2. Description of the Related Art Generally, it is well known that a frequency synthesizer is used in a digital tuning system such as a radio and has the features that the tuning frequency is accurate and that automatic tuning is easy. By the way.

An example of a conventional frequency synthesizer of this type is shown in FIG. As shown in FIG. 2, in this conventional example,
It is composed of a programmable divider 2, a phase comparator 3, a low pass filter 4 and a voltage controlled oscillator 5.

In FIG. 2, an input signal 1 having a frequency f _r
01 is phase-compared with the signal 103 output from the programmable divider 2 in the phase comparator 3, and the phase error signal corresponding to the phase difference is input to the voltage controlled oscillator 5 via the low pass filter 4. Voltage controlled oscillator 5
Is an oscillator whose oscillation frequency is controlled by the voltage output from the low-pass filter 4. The oscillation output signal is output as the output signal 102 of the main frequency synthesizer having the frequency f _o and the programmable divider 2
Entered against. Programmable divider 2
Has a function of dividing the frequency of the input signal by N (a positive integer). Therefore, in the programmable divider 2, the frequency fo of the output signal 102 is _divided by N to obtain the frequency f _v. The signal 103 of (= f _o / N) is output and input to the phase comparator 3 described above. That is, FIG.
The frequency synthesizer shown in FIG. 2 forms a phase-locked system, and in the steady state, the frequency f _{v of the} signal 103 is
Has a frequency equal to the frequency f _r of the input signal 101. That is, f _v = f _r. Therefore, the frequency of the output signal 102 f _o becomes f _o = N · f _r.

In this way, channel selection in a receiver such as a radio is performed by the output signal 1 output from the voltage controlled oscillator 5.
A local oscillation frequency is generated through the frequency of 02,
This is done by changing the value of N (called N value).

[0006]

Since the conventional frequency synthesizer described above is provided with only one programmable divider, in the digital tuning system, the frequency currently received is changed to another frequency. In the case of tuning, for example, an N value is calculated from channel information in a microcomputer, and a programmable divider of a frequency synthesizer
RDS (RADIO DATA SYSTEM), which is practically used in Europe, requires processing such as transferring the N value using serial communication.
In the case of a system in which the frequency is automatically changed one after another as in the above, or in the case of a system in which there is a high possibility that the frequency tuned in the past is retuned, There is a drawback that the load on the computer becomes excessive.

[0007]

The frequency synthesizer of the present invention is formed by including a phase comparator, a low-pass filter, a voltage-controlled oscillator, and a phase-locked loop system including a programmable divider having a frequency dividing function. In a frequency synthesizer that outputs a signal of a predetermined frequency from a controlled oscillator, a plurality of frequency division data input from the outside is stored, the frequency division data is selected and output via a predetermined control signal, and the programmable It is configured by including a frequency division value setting means for setting a frequency division value in the divider.

The frequency division value setting means is stored in the frequency division data storage circuit via the frequency division data storage circuit for storing the plurality of frequency division data input from the outside and the control signal. An address designating circuit for designating an address to be selected among the plurality of divided data addresses may be provided.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in FIG. 1, in the present embodiment, a frequency division data storage circuit 1 capable of storing a plurality of frequency division data inputted from the outside, and a blograma which divides the frequency of an input signal by N Bull divider 2 and phase comparator 3
A low-pass filter 4, a voltage-controlled oscillator 5, and an addressing circuit 6.

In FIG. 1, the operation of the phase lock system including the phase comparator 3, the low-pass filter 4, the voltage controlled oscillator 5 and the programmable divider 2 is the same as that of the above-mentioned conventional example, but the present invention As a feature of the above, as a means for changing the frequency of the output signal 102 of the phase synchronization system, a frequency-divided data storage circuit 1 for newly storing frequency-divided data input from the outside, and the frequency-divided data storage circuit 1 And an address designating circuit 6 for designating an address of the frequency division data stored in.

First, the frequency division data 105 generated by a microcomputer or the like is input to the frequency division data storage circuit 1 via a predetermined data line. On the other hand, via the predetermined control signal 104, the storage address of the divided data designated in connection with the frequency selection is output from the address designating circuit 6 and input to the divided data storage circuit 1. In the divided data storage circuit 1, the divided data corresponding to the specified storage address is read out and input to the programmable divider 2. In the programmable divider 2, an N value corresponding to the divided data input from the divided data storage circuit 1 is set, and the N value is set to be different from that of the conventional example through the synchronous operation in the phase locked system. Similarly, the frequency of the output signal 102 is set and arbitrary channel selection is performed.

In this case, the divided data storage circuit 1
The operation of storing the divided data with respect to is performed continuously asynchronously with the timing of outputting the divided data from the divided data storage circuit 1 to the programmable divider 2. The frequency division data output to the programmable divider 2 is changed by controlling the designated address value of the address designating circuit 6 by a control signal 104 input from the outside, or by automatically incrementing or decrementing the value. Then, the frequency division data of the newly set address is output to the blog programmable divider 2.

When the above-mentioned frequency synthesizer is used to tune in a receiver such as a radio, frequency-divided data of frequency A to be tuned is generated and stored in the frequency-divided data storage circuit 1, and the address is stored. The storage address of the corresponding frequency-divided data is designated via the designation circuit 6. This allows
The frequency-divided data of the frequency A is output to the programmable divider 2, and the phase-locked system enters a steady state according to the frequency-divided data, resulting in the output signal 102.
The frequency of is output as the frequency A, and the desired tuning is performed. If there is a frequency to be further tuned in addition to that, if the corresponding frequency division data is generated in advance and stored in the frequency division data storage circuit 1, the tuning frequency can be changed. This can be performed only by changing the designated address value in the memory circuit 1, and it is not necessary to generate the divided data every time, and the tuning operation can be easily performed.

[0015]

As described above, according to the present invention, the frequency division data corresponding to the channel selection is stored in the frequency division data storage circuit in advance, and is transmitted via the address designation circuit by a predetermined external control signal. The frequency division data is read out by controlling the selection of the N value of the programmable divider so that the tuning frequency in the digital tuning system can be easily selected and the frequency division data is generated. This has the effect of reducing the burden on the user.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

[Explanation of symbols]

 1 Frequency division data storage circuit 2 Programmable divider 3 Phase comparator 4 Low pass filter 5 Voltage controlled oscillator 6 Addressing circuit

Claims (2)

[Claims] 1. A frequency formed by including a phase comparator, a low-pass filter, a voltage-controlled oscillator, and a phase-locking system including a programmable divider having a frequency dividing function, and outputting a signal of a predetermined frequency from the voltage-controlled oscillator. In the synthesizer, a plurality of frequency division data input from the outside is stored, the frequency division data is selected and output via a predetermined control signal,
A frequency synthesizer comprising frequency division value setting means for setting a frequency division value in the programmable divider. 2. The frequency division value setting means stores a frequency division data storage circuit for storing the plurality of frequency division data inputted from the outside, and the frequency division data storage circuit stores the frequency division data storage circuit via the control signal. The frequency synthesizer according to claim 1, further comprising: an addressing circuit that specifies an address to be selected from among a plurality of divided data addresses.