JPS6126732B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a channel selection device used in a television receiver or the like, and more particularly to a frequency synthesizer type channel selection device using a phase synchronization circuit. Recently, so-called frequency synthesizer type tuning devices, in which the oscillation frequency of a local oscillator is controlled by a phase-locked circuit (PLL circuit), have been used in television receivers, FM-AM radio receivers, and other receiving devices. It's coming. In other words, this method inserts a variable frequency divider circuit into the feedback loop of the phase-locked circuit, and performs channel selection by controlling the frequency division ratio according to the channel to be received.
By using a highly stable reference oscillator such as a crystal oscillator, the oscillation frequency of the voltage-controlled local oscillator synchronized therewith can be stabilized to the same level as that of the reference oscillator. Incidentally, in such a type of channel selection device, for the purpose of finely adjusting the frequency of the local oscillator, the variable frequency dividing circuit is one that can vary the value below the decimal point of the frequency division ratio. FIG. 1 shows an example of a channel selection device using this type of frequency synthesizer method. In FIG. 1, for example, a television signal received by an antenna 1 is sent to a mixer 3 via a high frequency amplification circuit 2.
After being converted to an intermediate frequency by the output of the voltage controlled local oscillator 5, the signal is taken out via the intermediate frequency amplifier 4. On the other hand, the phase locked circuit mainly includes a local oscillator 5, a variable frequency divider circuit 6, a highly stable reference oscillator 7 such as a crystal oscillator, a phase comparator 8, and a loop filter 9. That is, after the output of the local oscillator 5 is frequency-divided by the variable frequency divider circuit 6, the phase is compared in the phase comparator 8 with the output of the reference oscillator 7 pre-divided by a prescaler (pre-frequency divider), The output of the phase comparator 8 is fed back to the local oscillator 5 as a control voltage via a loop filter 9. The variable frequency dividing circuit 6 includes a prescaler 10a,
It is composed of a pulse sampling circuit 11, a prescaler 10b, a variable frequency divider 12, and a rate multiplier 13. That is, rate multiplier 1
3 is a variable frequency divider that generates Q output pulses (Q is an integer from O to P-1) in response to P input pulses (P is an arbitrary integer); in this example, the output of the prescaler 10c is It is used as input. The pulse extraction circuit 11 synchronizes with the output of the rate multiplier 13, for example, the output of the rate multiplier 13.
Prescaler 10a only when the output of
This circuit extracts one output pulse of the local oscillator 5 whose frequency has been divided by , and this extracted pulse train is input to the variable frequency divider 12 via the prescaler 10b.
Further, the output of the variable frequency divider 12 is transmitted to the phase comparator 8.
will be input at one end of the . When the phase locked circuit is configured in this way, the oscillation frequency oi of the local oscillator 5 is given by the following equation during phase locking. oi=n ₁ (n ₂ m ₁ + ₃ Q/P) ...(1) where ₃ = re/n ₃ , ₂ = ₃ /n ₄ =
re/n ₃ n ₄ = ₁ , so oi=n ₁ n ₂ (m+n ₄ /n ₂・Q/P) re/
n ₃ n ₄ ...(2) However, n ₁ to _{n 4} are each prescaler 10a to
10d is the frequency division ratio, m is the frequency division ratio of the variable frequency divider 12,
re represents the oscillation frequency of the reference oscillator 7. As a specific numerical example for a television receiver in equation (1), re = 1000MHz, n ₁・n ₂ = n ₃・n ₄ =
256, n ₂ = n ₄ = 4, P = 64, Q = 0, 1, 2...
Substituting 63 gives oi=(m+Q/64)MHz...(3). Therefore, as shown in FIG. 1, the tuning signal obtained by operating the tuning button 14 is converted into a predetermined code signal by the encoder 15 and set in the latch circuit 16. Circulator 12
For example, if the frequency division ratio m is m=150, 156,..., 162,...
..., 824, it is possible to select a channel. In addition, by operating the frequency fine tuner 18, the value of Q in the rate multiplier 13 can be adjusted through the latch circuit 19 by, for example, Q=
The oscillation frequency oi of the local oscillator 5 can be finely adjusted by changing it as 0, 1, 2, . . . , 63. According to the above example, as is clear from equation (3),
Frequency change step due to fine adjustment of oi is 1/64MHz =
The frequency is 15.625kHz, and an offset frequency (Δ=Q/64) can be created within a range Q times this. However, equation (3) only provides offset frequencies where 1>Δ0, and cannot obtain offset frequencies where Δ<0. That is, although oi can be finely adjusted in an increasing direction around the value determined by the frequency division ratio m of the variable frequency divider 12, it cannot be finely adjusted in a decreasing direction. In order to obtain an offset frequency where Δ<0, the frequency division ratio m of the variable frequency divider 12 is changed from m→
It may be set to m-1, but in that case, the following problem arises. That is, in order to change m→m-1, it is necessary to use the latch circuit 16 in FIG. 1 as a reversible counter and control its contents in accordance with the direction of fine adjustment of oi. Regarding the value of Q in the rate multiplier 13, the latch circuit 19 must also have the function of a reversible counter, and its counting direction must be controlled in accordance with the direction of fine adjustment of oi. This situation is shown in FIG. Figure 2 shows an example of the division ratio m
The spectrum of the oscillation frequency oi of the local oscillator 5 when the initial setting value of is m = 150, and m, Q
This shows the relationship between oi and the center value (150M
m=150 for fine tuning in the direction of increasing
As mentioned above, Q is Q=0, 1, 2,...
..., 63, but if you want to fine-tune oi in the direction of decreasing from the center value, m = 149, and Q must be changed as Q = 0, 63, 62..., 1. I understand. Furthermore, changing the frequency division ratio of the variable frequency divider 12 from m to m-1 means changing the channel number information stored in the latch circuit 16, which is displayed on the channel number display circuit 17 as it is. This is not desirable because the channel number changes every time the offset frequency is set to Δ<0. Therefore, in order to keep the channel number display constant regardless of the fine adjustment direction of oi, press the channel selection button 14.
A separate memory is required to store information on the channel number specified by the operation for display. In the above case, m→m by the latch circuit 16
If the timing of changing to -1 and the timing of setting the Q value by the latch circuit 19 do not match, the frequency of oi will instantaneously shift significantly, which will appear as noise in the output of the local oscillator 5. be. On the other hand, regarding the pulse sampling circuit 11 in FIG.
It cannot be configured simply by using one gate circuit, as in the case of extracting pulses of a constant frequency.
For this reason, it is necessary to adopt a configuration in which input pulses are extracted using the synchronization of input pulses that vary over a wide range as a reference timing, which complicates the circuit configuration. FIG. 3 shows a specific example of the configuration of the pulse sampling circuit 11, which is composed of three flip-flops and three gates, and it can be seen that it is quite complicated. As described above, since the device shown in FIG. 1 uses the pulse sampling circuit 11, not only the configuration of the variable frequency divider circuit 6 itself in the phase synchronization circuit becomes complicated, but also the fine adjustment of the oscillation frequency oi of the local oscillator 5 is increased and If an attempt is made to decrease the frequency in both directions, the peripheral circuitry for controlling the variable frequency divider circuit 6 will also become considerably complicated. For this reason, when converting a circuit into an IC, the chip area becomes larger, leading to lower yields and higher costs.At the same time, the increase in current due to the increase in circuit scale raises the chip temperature, which limits the ambient temperature of the IC and reduces consumption. There were various problems in practical use, such as increased power consumption. SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a frequency synthesizer type tuning device that can significantly simplify the circuit configuration while having a fine adjustment function for increasing and decreasing the oscillation frequency of a local oscillator. . The present invention will be explained in detail below with reference to illustrated embodiments. FIG. 4 shows a channel selection device according to an embodiment of the present invention. Parts corresponding to those in FIG. 1 are given the same reference numerals, and only the differences from FIG. 1 will be described. 4 differs from FIG. 1 in the configuration of the variable frequency divider circuit 6. In FIG. This variable frequency dividing circuit 6 includes a pulse sampling circuit 11 and a prescaler 10 in FIG.
This corresponds to the part b replaced with a first variable frequency divider 20, and this variable frequency divider 20 is a prescaler 1.
0a and the second variable frequency divider 12. The first variable frequency divider 20 is connected to the frequency fine tuner 18 every time the output pulse A of the rate multiplier 13, which is the third variable frequency divider, is generated.
The frequency division ratio k changes from the initial setting value k ₁ to k ₁ +1 or k ₁ -1 according to the fine adjustment signal B from. However, the above-mentioned fine adjustment signal B is determined in the fine adjustment direction of the oscillation frequency oi of the local oscillator 5, that is, whether oi is finely adjusted in the increasing direction or in the decreasing direction around the value determined by the frequency division ratio m of the variable frequency divider 12. Depending on the state, the state becomes logic “1” or “0” respectively.
It is a binary signal that changes to . Next, we will explain the details of each part. First, the rate multiplier 13 will be explained. Figure 5 shows the rate multiplier P=
8. FIG. 6 is a diagram showing an example of the configuration when Q=0 to 7, and is a time chart thereof. In FIG. 5, flip-flops 21a, 21b, 21c are
These flip-flops 21a, 21b, 21c are connected in series via an AND gate 22 to form a synchronous counter, and each of these flip-flops 21a, 21b, 21c receives an input pulse CP ₁
(output pulse of prescaler 10c), each output Q _a , Q _b , Q
_c becomes as shown in Figure 6. AND gate 23a, 2
3b and 23c are _{( CP 1 〓 a )} , (CP ₁ 〓Q _{a 〓 b ) ,} (CP ₁ 〓Q _a
〓Q _b 〓 _c )), and as shown in Fig. 6, the input pulse CP ₁ is 8
During the input, 4, 2, and 1 output pulses are output at different times. these
Each output of AND gates 23a, 23b, 23c is connected to a control signal from latch circuit 19 in FIG. 4 by AND gates 24a, 24b, 24c.
is selectively extracted according to C ₂ , C ₁ , C ₀ , and
It is synthesized in OR gate 25 to become CP ₂ , and this CP ₂
is extracted as the output pulse A of the rate multiplier 13. With this configuration, the control signals C ₂ , C ₁ , C ₀
By combining the values of , it is possible to generate 0 to 7 output pulses CP ₂ for 8 input pulses CP ₁ . For example, if C ₂ = logic “1”, C ₁ = logic “1”, and C ₀ = logic “0”, the output of the OR gate 25 is (CP ₁ 〓 _a )〓(CP ₁ 〓Q _a 〓 _b )
So, as shown in Fig. 6, 8 input pulses
Six output pulses CP ₂ will be generated for CP ₁ . Next, the first variable frequency divider 20 is controlled by its frequency division ratio k by the output pulse of the rate multiplier 13.
is configured such that k=k ₁ to k=k ₁ +1 or k ₁ -1, and FIG. 7 shows k ₁ = 4.
This is an example of a configuration in the case of . That is, in FIG. 7, 31a to 31c are D-type flip-flops, 32
is a buffer gate with an inverted output terminal, 33 is an AND gate with an inverted output terminal, and 34 to 37 are AND gates.
Gates 38 and 39 are OR gates, the logical formula of which is given by the following formula.

[Table] D ₂ = A￣Q ₁ + AQ ₁・Q￣ ₂ 〓
Here, as mentioned above, A indicates the output signal of the rate multiplier 13, and B indicates that the frequency division ratio k is switched from k ₁ (=4) to k ₁ -1 (=3) by A. The fine tuning signal from the frequency fine tuner 18 which determines whether to switch to k ₁ +1 (=5) or k 1 +1 (=5) is shown. Further, in FIG. 7, the inverted output ₁ of the flip-flop 31a is used as the output of the first variable frequency divider 20. In principle, the flip-flop 31a
The non-inverting output Q ₁ may be the output of the first variable frequency divider 20, but in this example, the non-inverting output Q ₁ is
Since it is also supplied to the AND gate 35, the inverted output ₁ is used in consideration of the balance between the drive capabilities of both the inverted and non-inverted outputs. The operation of this first variable frequency divider 20 will be explained with reference to the time chart of FIG. Now rate
Assuming that the output signal A of the multiplier 13 is A=logic "0", D ₁ = ₂ and D ₂ = Q ₁ from equation (5) regardless of the value of the fine adjustment signal B. The time chart at _this time is shown in FIG. The frequency division ratio k of the variable frequency divider 20 of 1 is k=k ₁ =4. Next, if A = logic "1" and B = logic "0", then D ₁ = ₂ and D ₂ = Q ₁・₂ from equation (4), so the time chart is as shown in Figure 8b. Become,
Since Q ₁ has one period when three pulses C, which are input to the first variable frequency divider 20, arrive, the frequency division ratio k is k=k ₁ -1=3. Furthermore, when A = logic "1" and B = logic "1", D ₁ = ₃ and D ₂ = Q _{1 2} , and the time chart becomes as shown in Figure 8c, and Q ₁ becomes Since five pulses C, which are input to the first variable frequency divider 20, arrive to form one period, the frequency division ratio k is k=k ₁ +
1=5. In addition, in FIG. 8a, even when looking at the non-inverting output _Q2 of the flip-flop 31b, the frequency division ratio is k.
However, in Figures 8b and 8c, only Q ₁ has the predetermined frequency division ratio K, so ₁ (or
It can be seen that Q ₁ ) needs to be the output of the first variable frequency divider 20. In this way, when the output signal A of the rate multiplier 18 becomes logic "1", the first variable frequency divider 20 changes its frequency division ratio k to k=k ₁ according to the fine adjustment signal B.
+1 or k ₁ -1. From the above, in Fig. 4, the oscillation frequency oi of the local oscillator 5 is determined by the equation (2) above during phase synchronization.
By replacing n ₂ (the frequency division ratio of the prescaler 10b) with the frequency division ratio k of the first variable frequency divider 20 corresponding to the prescaler 10b (in this case, k= _k1) , it is given by the following equation: oi= n ₁ k ₁ (m±n ₁ /k ₁・Q/P)re/n
₃ n ₄ ... (5) The ± sign in equation (5) represents the case where the fine adjustment signal B is logic "1" and "0", respectively. Therefore, as before, as a concrete numerical example, re=1000MHz,
n ₁ k ₁ = n ₃ n ₄ = 256, k ₁ = n ₄ = 4, P = 64, Q =
By substituting 0, 1, 2, ..., 63, oi=(m±Q/64)MHz ...(6), operate the channel selection button 14 and turn the encoder 1.
5. Through the latch circuit 16, m is set to m=150, 156,
. . . By changing the number like . . . 162, . . . , 824, it is possible to select a channel. An example of the configuration of a rate multiplier with P=64, Q=0, 1, 2, . . . 63 used in this case is shown in FIG. In FIG. 9, flip-flops 41a to 41
AND gates 42a to 42d constitute a synchronous counter, and flip-flop 21a in FIG.
˜21c and AND gate 22, respectively. Also, AND gates 43a to 43, 44
a to 44 and OR gate 45 are AND gates 23a to 23c and 24a to 2 in FIG. 5, respectively.
4c and OR gate 25. and,
In this case, 6-bit control signals C _{5 -C 0} are supplied from the latch circuit 19 shown in FIG _. The pulses are selectively taken out by the OR gate 45, and are taken out as an output pulse CP ₂ (A). In this case, 0 to 63 output pulses CP ₂ for 64 input pulses CP ₁ depending on the combination of control signals C ₅ to _{C 0}
will be generated. On the other hand, regarding fine adjustment of the oscillation frequency oi of the local oscillator 5, the frequency fine tuner 18 is operated to change the value of Q in the rate multiplier 13 through the latch circuit 19 as Q = 0, 1, 2, ..., 63. It is done by letting At that time, when finely adjusting oi in the increasing direction around the value determined by m, that is, if the offset frequency Δ of o is adjusted to 1>Δ0
When changing within the range of , oi=(m+Q/64) MHz. Conversely, when oi is finely adjusted in the decreasing direction, that is, when an offset frequency of Δ<0 is provided, oi=(m-Q/64). Therefore, even when Δ<0, there is no need to change the frequency division ratio m of the second variable frequency divider 12 from m to m-1, and the latch circuit 16 does not need to be a reversible counter. There is no need for a preliminary memory for storing the channel number designated by the channel selection button 14 for display, and the contents of the latch circuit 16 can be displayed as they are. Furthermore, regarding the latch circuit 19, regardless of the fine adjustment direction of oi, that is, regardless of whether an offset frequency of Δ>0 or Δ<0 is obtained, the value of Q in the rate multiplier 13 is set to Q=0.
There is no need to use a reversible counter because it is sufficient to always change in the same direction as →1→2→...→63. On the other hand, the first variable frequency divider 20 can be realized by adding some gate circuits for switching the frequency division ratio to the prescaler 10b in FIG. 1, as shown in detail in FIG. Therefore, the number of elements is reduced compared to the circuit consisting of the pulse sampling circuit 11 and the prescaler 10b in FIG.
Simplified. As described above with reference to one embodiment, according to the present invention, the circuit configuration of the phase synchronized circuit, particularly the variable frequency divider circuit 6, is simplified while having the same frequency fine adjustment function as the conventional device. At the same time, the peripheral circuitry associated therewith is also simplified. Therefore, since the circuit scale of the entire system of the tuning device is extremely simplified, it is possible to reduce the chip size, cost, and power consumption, especially when converting to an IC.Furthermore, the chip temperature is also reduced, so the surrounding environment is reduced. It has advantages such as ease of temperature control, and has great practical effects. Also, when making fine adjustments, only the contents of the latch circuit 19 of the latch circuits 16 and 19 are changed to adjust the rate.
Since it is only necessary to set the value of Q in the multiplier 13, there is no problem of noise in the output of the local oscillator 5. In the above embodiment, the initial setting value of the frequency division ratio k of the first variable frequency divider 20 was explained as k ₁ =4, but it goes without saying that k ₁ can be set to any value. Also, although n ₁ /k ₁ = 1, if n ₁ /k ₁ = N (N = 2, 3, 4, ...), the offset frequency Δ
Since the offset frequency is also multiplied by N, it is possible to change the offset frequency within the range of N>N·Q/P0. Furthermore, although the rate multiplier 13 was used as the third variable frequency divider in the above embodiment, a normal variable frequency divider that generates one output pulse for an integer number of input pulses may also be used. . However, the use of a rate multiplier is advantageous in that the offset frequency Δ can be changed more finely and at even pitches.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a synthesizer-based channel selection device, FIG. 2 is a diagram for explaining the operation of FIG. 1, and FIG. 3 is a diagram showing a specific example of the pulse sampling circuit in FIG. 1. FIG. 4 is a block diagram showing a channel selection device according to an embodiment of the present invention, FIG. 5 is a diagram showing a specific example of the rate multiplier in FIG. 4, FIG. 6 is a time chart showing its operation, and FIG. 7 is a diagram showing a specific example of the first variable frequency divider in FIG. 4, FIG. 8 is a time chart showing its operation, and FIG. 9 is a diagram showing yet another specific example of the rate multiplier. be. 5... Voltage controlled local oscillator, 6... Variable frequency divider circuit, 7... Reference oscillator, 8... Phase comparator, 9
...Loop filter, 10a to 10d...Prescaler, 12...Second variable frequency divider, 13...Rate multiplier (third variable frequency divider), 2
0...First variable frequency divider.

Claims (1)

[Claims] 1. The output of the voltage-controlled local oscillator is frequency-divided, and this frequency-divided output and the output of the reference oscillator or the output obtained by pre-dividing the frequency are input to a phase comparator, and the phase comparison result is inputted to a phase comparator. In a channel selection device that performs channel selection by applying phase synchronization to the local oscillator according to
A first variable frequency divider that divides the output of the local oscillator or the output obtained by pre-dividing the local oscillator by k (k is an arbitrary integer), and divides the output of the first variable frequency divider by m ( m is an arbitrary integer) and is provided to be input to the phase comparator, and whose frequency division ratio m is controlled according to the frequency to be received, and the output of the reference oscillator. or a third variable frequency divider which inputs the output obtained by pre-dividing the frequency and whose frequency division ratio is controlled by a frequency fine adjustment operation, and the frequency division ratio k of the first variable frequency divider. is changed from the initial setting value k ₁ to k ₁ according to the fine adjustment direction of the frequency fine adjustment operation every time the output pulse of the third variable frequency divider is generated.
A channel selection device characterized by changing the channel to +1 or k ₁ -1. 2 As the third variable frequency divider, for P input pulses (P is an arbitrary integer), Q pulses (Q=O~
The rate at which output pulses are generated (an integer of P-1) is
A channel selection device according to claim 1, which uses a multiplier.