JP3102149B2 - Clock synchronizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock synchronizer used in audio equipment, such as an AD converter or a DA converter, which requires a sampling clock.

[0002]

2. Description of the Related Art FIG. 7 shows a configuration of a converter using a conventional clock synchronizer. In FIG. 7, 10
Reference numeral 1 denotes an analog signal input terminal, which is connected to the AD converter 102. The output terminal of the AD converter 102 is connected to the digital signal output terminal 103. Reference numeral 104 denotes an input terminal of a clock supplied from the outside, which is connected to one input terminal of the phase comparator 105,
The output signal of No. 5 is a voltage V, which is input to a control voltage input terminal of the voltage controlled oscillator 106. Voltage controlled oscillator 1
The output terminal 06 is connected to the other input terminal of the phase comparator 105 and to the sampling clock input terminal of the AD converter 104.

Next, the operation will be described. 7, the frequency f _s of the clock having a frequency f _in to the clock input terminal 104 is input fed back from the phase comparator the next stage of the voltage controlled oscillator 106 in 105
Is performed frequency phase comparison between the signal having, in accordance with the difference between the two frequencies f _in and f _s, as shown in FIG. 8, it outputs a voltage V proportional to the frequency difference. Voltage controlled oscillator 10
6 outputs a signal having a frequency proportional to the voltage V. For example, the frequency f _s is the frequency f _in of the input clock
If higher, the output voltage V of the phase comparator 105 decreases, the frequency f _s of the output signal of the voltage controlled oscillator 106 is low. On the other hand, if the frequency f _s is lower than the frequency f _in,
The output voltage V of the phase comparator 105 increases, and the frequency f _s of the output signal of the voltage controlled oscillator 106 increases. By such an operation, the frequency f _s of the output signal of the voltage controlled oscillator 106 is focused and coincides with the frequency f _in , and A
The sampling clock of the D converter 102 can be operated in synchronization with a digital signal input from the outside.

As described above, even an AD converter using the above-described conventional clock synchronizer can operate the AD converter in synchronization with the frequency of an externally applied clock signal.

[0005]

However, in the above-described conventional device, when the range of change in the frequency of the clock supplied from the outside is relatively wide, the voltage controlled oscillator 10
When a highly stable oscillator using crystal, lithium tantalate, or the like cannot be used for 6 and the jitter of the external clock is large, the jitter affects the stability of the sampling clock input to the converter or the like. However, there is a problem that conversion accuracy is deteriorated.

The present invention is to solve such a conventional problem. When the frequency of the synchronous clock output is made to be high precision and high stability, when the synchronous clock is operated in synchronism with the external clock, the external clock is used. It is an object of the present invention to provide an excellent clock synchronizer in which the sampling clock becomes unstable due to the jitter and the conversion accuracy of a converter or the like does not deteriorate.

[0007]

According to the present invention, as a first means, a high stability voltage controlled oscillator having a high frequency stability for oscillating a reference clock is provided as first means.
A reference clock phase comparator as a first phase comparator, a normal voltage controlled oscillator, and an n-ary counter as a counter, and a high stability voltage controlled oscillator at one input terminal of the reference clock phase comparator And the output signal of the reference clock phase comparator is input to the control input terminal of a normal voltage controlled oscillator. The output signal of the voltage controlled oscillator is used as the output signal of the clock synchronizer, and The frequency is divided by n by the counter and input to the other input terminal of the reference clock phase comparator. Further, an external clock phase comparator as a second phase comparator and an up / down counter as a reversible counter for controlling a frequency division ratio n by an output voltage thereof are provided, and one input terminal of the external clock phase comparator is provided at one input terminal. Input the output signal of a normal voltage controlled oscillator, the external clock to be synchronized input from the external clock input terminal to the other input terminal, and output the output signal of the external clock phase comparator to the high stability voltage controlled oscillator. Control input terminal and the input terminal for controlling the increase / decrease of the count of the up / down counter. If the oscillation frequency of the normal voltage controlled oscillator is higher than the external clock input, the count of the n-ary counter is decreased. When the oscillation frequency of a high-stability voltage-controlled oscillator is finely adjusted and the oscillation frequency of a normal voltage-controlled oscillator is Increases the count of the n-ary counter, in which the oscillation frequency of high stability voltage-controlled oscillator and adapted to fine adjustment.

In order to achieve the above object, the present invention provides, as a second means, in addition to the first means, a frequency division ratio setting device and an input signal to an n-ary counter, the output signal of an up / down counter. From the output terminal of the external clock phase comparator, a frequency dividing switch for switching to the output signal of the frequency dividing ratio setting device, a constant voltage source, and a device connected to the control input terminal of the high stability voltage controlled oscillator. A power supply switch for switching to an output terminal of the voltage source. When an external clock input is not used, the setting value of the frequency division ratio setting device is connected to the n-ary counter by the frequency division ratio switch, and the constant voltage source Is input to the control input terminal of the high stability voltage controlled oscillator to generate a synchronous clock.

In order to achieve the above object, the present invention provides, as a third means, in addition to the first means, a decoder connected to an input terminal of an n-ary counter, and a numerical value or an output signal of the decoder. A display for displaying characters is provided, and a numerical value or a character corresponding to the count value given to the n-ary counter is displayed.

[0010]

According to the present invention, therefore, the first means synchronizes with the external clock first, and coarse adjustment is performed by the reference clock phase comparator, the ordinary voltage controlled oscillator and the n-ary counter. Synchronization is performed on the signal. Further, since the synchronization with the external clock is further fine-tuned by the external clock phase comparator and the high stability voltage controlled oscillator, the clock synchronizer outputs a synchronous clock with high stability and little jitter.

According to the second aspect of the present invention, when synchronization with an external clock is not required, the clock from the frequency division ratio setting device and the reference voltage from the constant voltage source are used by the changeover switch. So that the first
Similarly, the clock synchronizer outputs a synchronous clock having a wide frequency change width, high stability, and low jitter.

Further, according to the present invention, since the count given to the n-ary counter is proportional to the frequency of the synchronous clock output by the third means, the given frequency or a character corresponding thereto is displayed.

[0013]

FIG. 1 shows the structure of a first embodiment of the present invention, and FIG.
FIG. 3 shows the operation, and FIG. 3 shows one configuration of the application example.

[0014] In FIG. 1, 1 is a high stability voltage-controlled oscillator, the oscillation frequency is f _r. The high stability voltage controlled oscillator 1 has a frequency variable range of ± Δf. 2 is a reference clock phase comparator, 3 is a voltage controlled oscillator, 4 is a synchronous clock output terminal, 5 is an n-ary counter (counter), 6
Is an external clock phase comparator, 7 is an up / down counter (reversible counter), and 8 is an external clock input terminal. The output signal of the high stability voltage controlled oscillator 1 is input to one input terminal of the reference clock phase comparator 2. The output signal of the reference clock phase comparator 2 is input to the voltage controlled oscillator 3, and the output signal of the voltage controlled oscillator 3 is the output signal of the device through the synchronous clock output terminal 4. The output signal of the voltage controlled oscillator 3 is further input to one input terminal of an external clock phase comparator 6 and an input terminal of an n-ary counter 5 which is a counting means. The other input terminal of the external clock phase comparator 6 is connected to the external clock input terminal 8, the external clock frequency f _in is input. The output signal of the up / down counter 7 is also connected to the n-ary counter 5, and the output signal of the up / down counter 7 gives the count value n to divide the frequency by n. The frequency-divided output signal of the n-ary counter 5 is supplied to the reference clock phase comparator 2
Is input to the other input terminal. In this way, the blocks denoted by reference numerals 1 to 7 constitute a phase locked loop that synchronizes with an external clock, and this constitutes a clock synchronizer.

Next, the operation of the first embodiment will be described with reference to FIG.
This will be described with reference to FIG. 2, the horizontal axis represents the difference between the two frequencies f _r and f _c, the vertical axis indicates a high stability voltage-controlled oscillator 1 of the output voltage, respectively. In Figure 1, first, when high-stability voltage-controlled oscillator 1 outputs a clock having a frequency f _r, the frequency comparison between the clock having a frequency f _c which is the output signal of the n-ary counter 5 is performed, FIG. 2 As shown in FIG. 5, the difference between the frequencies of the two input signals ( _fr −
An output voltage corresponding to _fc ) is generated. The voltage controlled oscillator 3 outputs a clock having a frequency f _vco proportional to the output voltage of the reference clock phase comparator 2. n-ary counter 5 outputs a clock having a frequency f _c and n dividing the f _vco. By the action of the feedback loop of this configuration, the frequency f _vco of the output signal of the voltage controlled oscillator 3
Is f _r and f _c is set to be the same value. That is, for example, in the case of f _r> f _c, the reference clock phase comparator 2
, The oscillation frequency f _vco of the voltage controlled oscillator 3 increases. f _c is due to the proportional relationship f _{vc o,} the output frequency of the n-ary counter 5 is higher, f _r and f _c
Becomes smaller. If you f _r and f _c matches, f _c =
Since (1 / n) of · f _vco relationship holds, the output frequency f _vco of the voltage controlled oscillator 3 becomes n · f _r.

[0016] On the other hand, the external clock phase comparator 6, the frequency of the external clock input an external clock having an input frequency f _in the terminal 8 and the output signal of the voltage controlled oscillator 3 having a frequency n · f _r A comparison is made. In the up / down counter 7, the external clock phase comparator 6
_in <subtracting the count value n when the relationship of n · f _r is satisfied, also the external clock by the phase comparator 6 n · f _r> f _in
When the relationship of (1) is established, the count value n is increased. The value of n · f _r is focused to f _in this operation, (n-1)
· F _r ≦ f relationship _in ≦ n · f _r is so true. Further, in the high stability voltage controlled oscillator 1, the oscillation frequency _{fr is set} to ± Δ in proportion to the voltage output of the external clock phase comparator 6.
f is slightly increased or decreased. With such an operation, the oscillation frequency of the voltage controlled oscillator 3 becomes equal to the frequency of the external clock.

FIG. 3 shows, as an example of the application of the clock synchronizer according to the first embodiment, a configuration in which a synchronous clock output signal is used as a sampling clock of an AD converter. Reference numeral 9 denotes an AD converter. The synchronous clock output terminal 4 is connected to a sampling clock input terminal of the AD converter 9, and is synchronized by a clock synchronizer.

When a highly stable oscillator using a crystal oscillator, lithium tantalate, or the like is used as the high stability voltage controlled oscillator 1, the oscillation frequency of the voltage controlled oscillator 3 is changed to the oscillation frequency of the high stability voltage controlled oscillator 1. Because it is locked to
An output signal of the voltage controlled oscillator 3 having high frequency stability can be obtained.

As described above, according to the clock synchronizer of the first embodiment, the following effects can be obtained. (1) Synchronization with an external clock is first performed by the reference clock phase comparator 2, the voltage controlled oscillator 3, and the n-ary counter 5, so that synchronization with a clock input of a wide frequency range becomes possible. (2) Since the synchronization with the external clock is further fine-tuned by the external clock phase comparator 6 and the high stability voltage controlled oscillator 1, it is possible to obtain a clock output with little jitter by the high stability voltage controlled oscillator 1. it can. For example AD
When used for a converter, a DA converter, or the like, conversion can be performed in synchronization with a wide range of input signals. Also, since a clock with little jitter is provided as a sampling clock for these converters, the conversion accuracy can always be kept very high.

FIG. 4 shows the configuration of a second embodiment of the present invention. In FIG. 4, the blocks denoted by reference numerals 1 to 8 have the same names and the same functions as the blocks in the first embodiment shown in FIG. In FIG. 4, reference numeral 10 denotes a division ratio changeover switch, and reference numeral 11 denotes a division ratio setting device. The division ratio changeover switch 10 determines the division ratio of the n-ary counter 5 by the up / down counter 7 or the count value n given by the division ratio setter 11
Or to choose. Reference numeral 12 denotes a power switch, and reference numeral 13 denotes a constant voltage source. The power switch 12 selects whether the control voltage source applied to the high stability voltage controlled oscillator 1 is the output voltage of the external clock phase comparator 6 or the constant voltage source 13. The division ratio changeover switch 10 and the power supply changeover switch 12 are interlocked with each other, and are simultaneously switched. Further, the elements of these two switches may be switching means using a semiconductor element such as an analog switch.

Next, the operation of the second embodiment will be described. In some cases, the clock synchronizer does not use an external clock. In such a case, it is necessary to fix the frequency division ratio of the n-ary counter 5 instead of the external clock.
Therefore, the input signal of the n-ary counter 5 is converted into a count value n that determines the oscillation frequency of the voltage controlled oscillator 3 by switching the up / down counter 7 to the frequency division ratio setting device 11 by operating the frequency division ratio switch 10. Is to give. When the external clock is not used, the power supply switch 12 is operated to change the control voltage applied to the high stability voltage controlled oscillator 1 to the external clock in order to keep the oscillation frequency of the high stability voltage controlled oscillator 1 constant. The output voltage of the phase comparator 6 is switched to the output voltage of the constant voltage source 13.

Therefore, according to the clock synchronizer of the second embodiment, in addition to the effects of the first embodiment, even when the synchronization with the external clock is unnecessary, the division ratio changeover switch 10 and the power supply By operating the changeover switch 12, it is possible to obtain a sampling clock having a wide frequency change width and high stability. For example, when used in an AD converter or a DA converter, it can synchronize with a wide range of input signals. In addition, since a clock with less jitter is provided as a sampling clock for these converters, there is an effect that the conversion accuracy can always be kept very high.

FIG. 5 shows the configuration of a third embodiment of the present invention. In FIG. 5, the blocks denoted by reference numerals 1 to 8 have the same names and the same functions as the blocks in the first embodiment shown in FIG. In FIG. 5, 14 is a decoder, and 15 is a display. The decoder 14 extracts the count value of the up / down counter 7 and displays the count value on the display 15. The display 15 is an element having a plurality of segments, a dot matrix, a CRT, or the like, capable of displaying numbers and characters.

Next, the operation of the third embodiment will be described. When the variation width of the oscillation frequency of the high stability voltage controlled oscillator 1 is relatively small, the oscillation frequency of the voltage controlled oscillator 3 is proportional to the count value n of the n-ary counter 5. Performing the calculation of n · f _r in the decoder 14. Therefore, the display device 15 displays the oscillation frequency of the voltage controlled oscillator 3 which is the sampling frequency.

Therefore, according to the clock synchronizer of the third embodiment, in addition to the effect of the first embodiment, the count given to the n-ary counter 5 is proportional to the frequency of the sampling clock output. Therefore, the display of the sampling frequency given from the outside is performed by the decoder 14.
And the display unit 15 has the effect of being made possible.

FIG. 6 shows the configuration of the fourth embodiment of the present invention. In FIG. 6, each component indicated by each reference numeral has the same name and the same function as each component in the second and third embodiments shown in FIG. 4 and FIG. .

Next, the operation of the fourth embodiment will be described. In FIG. 6, when an external clock is not used,
In order to fix the frequency division ratio of the n-ary counter 5 in place of the external clock, the input signal of the n-ary counter 5 is operated by operating the frequency division ratio switch 10 to set the frequency division ratio from the up / down counter 7. Count n for determining the oscillation frequency of voltage controlled oscillator 3 by switching to
In addition, in order to make the oscillation frequency of the high stability voltage controlled oscillator 1 constant, the control voltage applied to the high stability voltage controlled oscillator 1 Even when the output voltage is switched from the output voltage to the output voltage of the constant voltage source 13, the display 15
4 indicates the frequency at the input terminal of the n-ary counter 5.

Therefore, according to the clock synchronizer of the fourth embodiment, in addition to the effect of the second embodiment, even when the synchronization with the external clock is unnecessary, the clock provided to the n-ary counter 5 can be obtained. Since the numerical value is proportional to the frequency of the sampling clock output, there is an effect that the display of the sampling frequency being set can be performed by the decoder 14 and the display 15.

In the third or fourth embodiment,
If a function of converting the numerical value of the result calculated by the decoder 14 into a code representing a character is added to the inside of the decoder 14 or another block, a character corresponding to the calculated frequency can be converted into, for example, when the frequency is 44.1 kHz. Is "CD"
In the case of 48 kHz, it is possible to display on the display 15 such as "DAT", and more places are provided for the user's convenience.

[0030]

The present invention has the following effects, as apparent from the first embodiment. (1) The synchronization with the external clock is first coarsely adjusted by the first phase comparator, the voltage controlled oscillator, and the counter. Synchronization with input is enabled. (2) Synchronization with an external clock is finely adjusted by the second phase comparator and the high-stability voltage-controlled oscillator. Therefore, a clock output with less jitter can be obtained by the high-stability voltage-controlled oscillator. . (3) When the clock synchronizer is used for, for example, an AD converter or a DA converter, conversion that synchronizes with a wide range of input signals can be performed. Also, since a clock with little jitter is provided as a sampling clock for these converters, the conversion accuracy can always be kept very high.

According to the present invention, as is apparent from the second embodiment, in addition to the effects of the first embodiment, even when synchronization with an external clock is not required, the first and second embodiments can be used. By operating the switching means, there is an effect that a sampling clock having a wide frequency change width and high stability can be obtained.

Further, according to the present invention, the third and fourth embodiments
As is clear from the embodiment of the present invention, since a decoder and a display are provided, even if an external clock is required or synchronization with the external clock is not required, the frequency corresponding to the sampling clock output or the frequency thereof This has the effect that characters can be displayed.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a clock synchronizer according to a first embodiment of the present invention.

FIG. 2 is an input / output characteristic diagram of a phase comparator in the clock synchronizer.

FIG. 3 is a schematic block diagram when the clock synchronizer is used for an AD converter.

FIG. 4 is a schematic block diagram of a clock synchronizer according to a second embodiment of the present invention.

FIG. 5 is a schematic block diagram of a clock synchronization device according to a third embodiment of the present invention.

FIG. 6 is a schematic block diagram of a clock synchronizer according to a fourth embodiment of the present invention.

FIG. 7 is a schematic block diagram of a conventional clock synchronizer.

FIG. 8 is an input / output characteristic diagram of a phase comparator in the clock synchronizer.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 high stability voltage controlled oscillator 2 reference clock phase comparator (first phase comparator) 3 voltage controlled oscillator 4 synchronous clock output terminal 5 n-ary counter (counter) 6 external clock phase comparator (second phase comparison) 7) Up / down counter (reversible counter) 8 External clock input terminal

Claims (4)

(57) [Claims] 1. A high stability voltage controlled oscillator for oscillating a reference clock, a first phase comparator to which an output signal of the high stability voltage controlled oscillator is input to one input terminal, and a first phase comparator A voltage-controlled oscillator in which the output voltage of the comparator is input to the control terminal, and an output signal of the voltage-controlled oscillator is input to one input terminal and the output voltage is input to the control terminal of the high-stability voltage-controlled oscillator. A second phase comparator, an external clock input terminal connected to the other input terminal of the second phase comparator for inputting an external clock, and an output signal of the voltage-controlled oscillator for inputting a frequency division. A counter for inputting the output signal to the other input terminal of the first phase comparator, and the high stability represented by the output voltage of the second phase comparator with respect to the counter. Output signal of voltage controlled oscillator A reversible counter that inputs a result of comparing a frequency with the frequency of the external clock to the counter to control a frequency division ratio in the counter, and outputs a synchronous clock connected to an output terminal of the voltage-controlled oscillator. And a synchronous clock output terminal. 2. A frequency division ratio setting device for setting a frequency division ratio in a counter, and a first switch for switching an input signal for controlling the frequency division ratio in the counter from a reversible counter to the frequency division ratio setter. Means, a constant voltage source for generating a voltage for controlling the oscillation frequency of the high stability voltage controlled oscillator, and a voltage for controlling the oscillation frequency of the high stability voltage controlled oscillator from the output voltage of the second phase comparator. Second to switch to constant voltage source output voltage
2. The clock synchronizer according to claim 1, further comprising: a switching unit. 3. A counter for inputting a signal for controlling a dividing ratio in a counter, and a display for displaying a numerical value corresponding to a count value given to the counter by an output signal of the decoder. 3. The clock synchronizer according to 1 or 2. 4. The clock synchronizer according to claim 3, wherein a character corresponding to a numerical value corresponding to the count value is displayed according to a predetermined rule.