JPH11150421A - Frequency synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To widen a band, while spuriousness due to a quantization error is suppressed to a low level by synthesizing a period signal from a phase-locked loop synthesizer with a period signal from a frequency up converter which receives the output signal of a direct digital synthesizer and up-converting it into a specified frequency. SOLUTION: A memory 6 receives a chirp data function from a chirp data function generating part 5 and outputs frequency rough setting data and frequency fine setting data to the PLL(phase-locked loop) synthesizer 2 and DDS 3(direct digital synthesizer). DDS3 and the frequency up-converter 4 output a signal which is up-converted into a desired frequency through frequency fine setting data. A mixer 7 synthesizes the period signals from the PLL synthesizer 2 and the frequency up converter, and a filter 8 removes an unwanted wave. Thus, a chirp signal which is arbitrarily set can be outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer using a phase-locked loop synthesizer and a direct digital synthesizer as high-speed and wide-band chirp waveform generating means for use in a radar transceiver.

[0002]

2. Description of the Related Art FIG. 7 shows a configuration of a conventional frequency synthesizer. In FIG.
Is a direct digital synthesizer (Direct
Digital Synthesizer: DD
S) and 4 are frequency upconverters. DDS3
Is composed of a phase accumulator 31, a memory 32, a digital-analog converter (hereinafter, DA converter) 33, and a filter 34.

Next, the operation will be described. The phase accumulator 31 in the DDS 3 accumulates and adds the frequency setting data based on the timing of the output signal of the reference clock from the reference clock oscillator 1 shown in the uppermost signal waveform diagram of FIG. The phase data shown in the signal waveform diagram is output. The phase accumulator 31
When the accumulated phase becomes 2π, the accumulated phase is reset to 0, and values of 0 to 2π are repeatedly output. The reference clock is configured so that one cycle of the output signal includes two or more clocks. As shown in FIG. 9, the memory 32 holds waveform data (amplitude data) for a phase as a lookup table using data as address data. As shown in FIG. 9, the phase data represents a phase corresponding to the amplitude data stored in the memory 32, but also represents an address of the memory 32,
Thus, the amplitude data is read. The amplitude data is D
The signal is converted to an analog value by the -A converter 33 and passed through a filter 34 for extracting only necessary frequency components from which unnecessary waves have been removed. The periodic signal that has passed through the filter 34 is input to the frequency up-converter 4, up-converted to a desired frequency, and output.

In such a configuration, the output frequency f _DDS of the DDS3 is _expressed as follows, where f _r is the reference signal frequency, A is the number of bits for which the frequency of the DDS3 can be set, and B is the decimal value of the actual frequency setting data. It is represented by 1. Thereby, the chirp signal as shown in FIG. 10 is output as the output frequency of the DDS3 by changing the frequency setting data at each update timing.

[0005]

(Equation 1)

[0006]

In the conventional frequency synthesizer as described above, a digital IC such as a DDS has a frequency limit, and a frequency band for suppressing a spurious caused by a quantization error in the DDS to a low level. Is limited, there is a drawback that the band cannot be widened. Further, when a method of expanding the band by multiplication using a phase locked loop synthesizer or the like is used, there is a disadvantage that the spurious level increases according to the multiplication order.

[0007] The present invention has been made to solve such a problem, and it is possible to widen a band while suppressing spuriousness caused by a quantization error to a low level.

[0008]

A frequency synthesizer according to a first aspect of the present invention includes a reference clock oscillator for generating a periodic signal having a specific frequency, and a first periodic signal having a designated frequency in response to frequency setting data. , A direct digital synthesizer that receives a frequency setting data to generate a second periodic signal having a designated frequency, and receives an output signal of the direct digital synthesizer to upconvert to a specific frequency A frequency upconverter, a chirp data function generating means for generating a chirp data function for generating a specified chirp waveform in response to chirp setting data, and controlling a phase locked loop synthesizer and a direct digital synthesizer in response to the chirp data function Laps to do A memory for outputting the number setting data,
The mixer is composed of a periodic signal from the phase locked loop synthesizer and a periodic signal from the frequency upconverter, and a filter for removing unnecessary waves from the mixer output.

A frequency synthesizer according to a second aspect of the present invention includes a reference clock oscillator for generating a periodic signal having a specific frequency, and a plurality of frequency synthesizers for generating a first periodic signal having a designated frequency in response to frequency setting data. Phase-locked loop synthesizers, a direct digital synthesizer that receives a frequency setting data and generates a second periodic signal having a specified frequency, and a frequency that receives an output signal of the direct digital synthesizer and up-converts to a specific frequency Upconverter, chirp data function generating means for generating a chirp data function for generating a specified chirp waveform in response to chirp setting data, and a plurality of phase locked loop synthesizers and direct digital synthesizers for receiving the chirp data function Control A memory for outputting a frequency setting data and a control signal for selecting one from a plurality of phase-locked loop synthesizers; and a switch for receiving a control signal from the memory and selecting one output from the plurality of phase-locked loop synthesizers. In addition, a mixer for synthesizing the periodic signal from the selected phase-locked loop synthesizer and the periodic signal from the frequency up-converter and a filter for removing unnecessary waves from the mixer output are used.

A frequency synthesizer according to a third aspect of the present invention includes a reference clock oscillator for generating a periodic signal having a specific frequency and a first clock generator for generating a first periodic signal having a specific frequency in response to frequency setting data. , A phase locked loop synthesizer that receives an output signal of the first direct digital synthesizer and frequency setting data and generates a second periodic signal having a specified frequency, A second direct digital synthesizer for generating a third periodic signal having a predetermined frequency, a frequency upconverter for receiving an output signal of the second direct digital synthesizer and upconverting the output signal to a specific frequency,
A chirp data function generating means for generating a chirp data function for generating a designated chirp waveform in response to the chirp setting data; a phase locked loop synthesizer and first and second direct digital synthesizers for receiving the chirp data function; A memory for outputting frequency setting data for control, a mixer for synthesizing a periodic signal from the phase locked loop synthesizer and a periodic signal from the frequency up-converter, and a filter for removing unnecessary waves from the mixer output are employed.

A frequency synthesizer according to a fourth aspect of the present invention provides a reference clock oscillator for generating a periodic signal having a specific frequency, and a first clock generator for generating a first periodic signal having a specific frequency in response to frequency setting data. Receiving the output signal of the first direct digital synthesizer and the frequency setting data to generate a second periodic signal having a designated frequency; and receiving the frequency setting data. Direct digital synthesizer for generating a third periodic signal having a specified frequency, a frequency upconverter for receiving an output signal of the second direct digital synthesizer and upconverting to a specific frequency, and chirp setting data Generates the specified chirp waveform A chirp data function generating means for generating a chirp data function for generating a plurality of phase locked loop synthesizers and frequency setting data for controlling the first and second direct digital synthesizers in response to the chirp data function. A memory for outputting a control signal for selecting one from the phase locked loop synthesizer;
A switch for selecting one output from a plurality of phase-locked loop synthesizers in response to a control signal from a memory, a mixer for synthesizing a periodic signal from the selected phase-locked loop synthesizer and a periodic signal from a frequency upconverter, The filter is configured to remove unnecessary waves from the mixer output.

Further, a frequency synthesizer according to a fifth aspect of the present invention includes a reference clock oscillator for generating a periodic signal having a specific frequency, and a first clock generator for generating a first periodic signal having a specific frequency in response to frequency setting data. , A phase locked loop synthesizer that receives an output signal of the first direct digital synthesizer and frequency setting data and generates a second periodic signal having a designated frequency, and receives a frequency setting data and receives a specific signal. A second direct digital synthesizer for generating a third periodic signal having a frequency, and a second direct digital synthesizer for generating a fourth periodic signal having a designated frequency in response to an output signal of the second direct digital synthesizer and frequency setting data. 3 direct digital synthesizers and 3 direct digital synthesizers A frequency upconverter for receiving an output signal of the synthesizer to upconvert to a specific frequency, a chirp data function generating means for receiving a chirp setting data and generating a chirp data function for generating a specified chirp waveform, and a chirp data Receiving the function, the phase locked loop synthesizer and the first, second, and third
Memory that outputs frequency setting data for controlling the direct digital synthesizer, a mixer that combines the periodic signal from the phase-locked loop synthesizer and the periodic signal from the frequency upconverter, and a filter that removes unnecessary waves from the mixer output Configuration.

A frequency synthesizer according to a sixth aspect of the present invention includes a reference clock oscillator for generating a periodic signal having a specific frequency and a first clock generator for generating a first periodic signal having a specific frequency in response to frequency setting data. Receiving the output signal of the first direct digital synthesizer and the frequency setting data to generate a second periodic signal having a designated frequency; and receiving the frequency setting data. To generate a third periodic signal having a specific frequency
A third direct digital synthesizer that receives an output signal of the second direct digital synthesizer and frequency setting data and generates a fourth periodic signal having a designated frequency;
A frequency up-converter for receiving an output signal of the third direct digital synthesizer to up-convert to a specific frequency, and generating a chirp data function for receiving a chirp setting data and generating a chirp data function for generating a specified chirp waveform Means, receiving a chirp data function, selecting a plurality of phase locked loop synthesizers, frequency setting data for controlling the first, second, and third direct digital synthesizers, and selecting one of the plurality of phase locked loop synthesizers A memory for outputting a control signal to be transmitted, a switch for selecting one output from a plurality of phase-locked loop synthesizers in response to a control signal from the memory, and a periodic signal from the selected phase-locked loop synthesizer and a frequency upconverter. Mixer that synthesizes periodic signals It was constructed by a filter for removing unnecessary waves from the output of the mixer.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a block diagram showing a first embodiment of the present invention. In FIG. 1, new parts 2,5 to 8,21 to 24 are different from the conventional example of FIG.
1, 3, and 4 are the same as the conventional example. The internal configuration of DDS3 is the same as the conventional one. 1 is a reference clock oscillator that generates a periodic signal having a specific frequency. 2 is a phase locked loop synthesizer (PhaseLock) that receives frequency setting data and generates a first periodic signal having a designated frequency.
ed Loop Synthesizer: PLL Synthesizer) 3 is a DDS that receives frequency setting data and generates a second periodic signal having a specified frequency, and 4 is a DDS 3
A frequency upconverter for receiving an output signal of the above and upconverting to a specific frequency, a chirp data function generator for receiving a chirp setting data and generating a chirp data function for generating a designated chirp waveform, 6
Is a memory that outputs frequency setting data for controlling the PLL synthesizer 2 and the DDS 3 in response to the chirp data function, 7 is a mixer that synthesizes a periodic signal from the PLL synthesizer 2 and a periodic signal from the frequency upconverter 4, and 8 is a mixer. This is a filter for removing unnecessary waves output from the mixer 7. The PLL synthesizer 2 includes a phase comparator 21,
Loop filter 22, voltage controlled oscillator (Voltage)
Control Oscillator: VC
O) 23 and a variable frequency divider 24.

Next, the operation will be described. The reference clock oscillator 1 generates a periodic signal having a specific frequency.
Output to the LL synthesizer 2, DDS3, chirp data function generator 5, and memory 6. The chirp data function generator 5 receives the chirp setting data such as the chirp repetition period, the chirp bandwidth, and the step frequency, generates the frequency update timing, and outputs the chirp bandwidth and the output frequency corresponding to the step frequency for each timing. Then, a chirp data function for specifying an address of the memory 6 storing frequency setting data of each synthesizer corresponding to the output frequency is generated. The memory 6 receives the chirp data function and outputs coarse frequency setting data for controlling the PLL synthesizer 2 and fine frequency setting data for controlling the DDS 3. The VCO inside the PLL synthesizer 2
23, a periodic signal is generated, the output signal is frequency-divided by a variable frequency divider 24 set to 1 / N times by frequency coarse setting data which can be arbitrarily set from the memory 6, and the phase comparator 21 The difference is obtained by comparing with the periodic signal from the oscillator 1, an error voltage corresponding to the difference is output by the loop filter 22, and is fed back to the VCO 23 as a control voltage, so that the periodic signal from the reference clock oscillator 1 is always N times larger. And at the same time is controlled to be in phase. At this time, the output frequency f _PLL of the PLL synthesizer 2, the frequency division number of the variable frequency divider 24 N, the reference signal frequency When f _r is expressed by "Equation 2". DDS3
And the frequency up-converter 4 have the same configuration as the conventional one. The output frequency of the DDS 3 is set based on the periodic signal from the reference clock oscillator 1 and the frequency fine setting data from the memory 6, and the up-converted signal to the desired frequency is set. Is output. The mixer 7 combines the periodic signal from the PLL synthesizer 2 and the periodic signal from the frequency up-converter 4, removes unnecessary waves from the mixer 7 with a filter 8, and outputs the resultant signal. At this time, the output frequency f _out of the frequency synthesizer is N, the frequency division number of the variable frequency divider 24 corresponding to the coarse frequency setting data, and f is the reference signal frequency.
_r , the number of bits for which the frequency of the DDS 3 can be set is A, the decimal value of the frequency fine setting data is B, and the set frequency of the frequency up-converter 4 is f _up .

[0016]

(Equation 2)

[0017]

(Equation 3)

With this configuration, the output frequency is roughly set in the PLL synthesizer 2 by the same step frequency as the reference frequency,
In S3, fine setting can be performed using a high-resolution step frequency. By performing this setting at each update timing, a chirp signal having an arbitrary setting as shown in FIG.
By generating a chirp signal without performing multiplication by the synthesizer 2, it is possible to widen a band while suppressing spuriousness due to a quantization error to a low level.

Embodiment 2 FIG. 2 is a block diagram showing a second embodiment of the present invention. In the figure, the new parts are 2, 5 to 9 compared with the conventional example of FIG. 7, and 1, 3, and 4 are the same as the conventional example. The internal configuration of the DDS 3 is the same as that of the related art, and the internal configuration of the plurality of PLL synthesizers 2 is the P
It is the same as LL synthesizer 2. 1 is a reference clock oscillator that generates a periodic signal having a specific frequency, 2 is a PLL synthesizer that receives frequency setting data and generates a first periodic signal having a specified frequency, and 3 is specified by receiving frequency setting data. DDS for generating a second periodic signal having the specified frequency, 4 is a frequency up-converter that receives the output signal of DDS 3 and up-converts to a specific frequency, and 5 receives chirp setting data and generates a specified chirp waveform. A chirp data function generator 6 for generating a chirp data function for performing the operation, a memory 6 receiving the chirp data function and outputting frequency setting data for controlling the plurality of PLL synthesizers 2 and the DDS 3, and a switch 7 for selecting Signal and frequency up-converter of one of the plurality of PLL synthesizers 2 A mixer for synthesizing the periodic signal from 4, a filter for removing unnecessary waves from the mixer 7, and a switch 9 for receiving a control signal from the memory 6 and selecting one from a plurality of PLL synthesizers 2. is there.

Next, the operation will be described. The components denoted by the same reference numerals as those in FIG. 1 of the first embodiment perform the same operations, receive the periodic signals from the reference clock oscillator 1, and set the respective frequency coarse setting data arbitrarily from the memory 6. Can be. The switch 9 selects one of the plurality of PLL synthesizers 2 according to a switching control signal from the memory 6 and outputs a periodic signal to the mixer 7.

By adopting such a configuration, the same effect as that of the first embodiment is obtained, and a chirp waveform is formed for each of the plurality of PLL synthesizers 2 except those selected by the switch 9. By providing the frequency setting data so that the next and the next settings are obtained, the convergence time of the PLL synthesizer 2 is shortened by converging the PLL synthesizer 2 in advance and using the same by switching with the switch 9. As a result, the frequency setting switching speed can be increased.

Embodiment 3 FIG. FIG. 3 is a block diagram showing a third embodiment of the present invention. In the drawing, the new parts are 2, 5 to 8, and 10, and 1, 3, and 4 are the same as the conventional example in FIG. . The internal configuration of the DDS3 and DDS10 is the same as the conventional one, and the internal configuration of the PLL synthesizer 2 is the same as the PLL synthesizer 2 of FIG. 1 is a reference clock oscillator for generating a periodic signal having a specific frequency,
2 is a PL that receives the output signal of the DDS 10 and the frequency setting data and generates a first periodic signal having a designated frequency.
The L synthesizer 3 receives the frequency setting data and generates a third periodic signal having a designated frequency.
Is a frequency upconverter that receives the output signal of the DDS3 and upconverts it to a specific frequency; 5 is a chirp data function generator that receives a chirp setting data and generates a chirp data function for generating a specified chirp waveform; Is a memory that receives the chirp data function and outputs frequency setting data for controlling the PLL synthesizer 2, DDS3, and DDS10; 7, a mixer that synthesizes a periodic signal from the PLL synthesizer 2 and a periodic signal from the frequency upconverter 4. Reference numeral 8 denotes a filter for removing unnecessary waves output from the mixer 7, and reference numeral 10 denotes a first periodic signal having a specific frequency upon receiving the frequency setting data, and
This is a DDS output to the L synthesizer 2.

Next, the operation will be described. The components denoted by the same reference numerals as those in FIG.
The DS 10 is similar to the DDS 3 and outputs a periodic signal to the PLL synthesizer 2 based on the periodic signal from the reference clock oscillator 1 and the frequency setting data from the memory 6.

[0024] Since by adopting such a configuration, exhibit the same effect as the first embodiment, also, the reference signal frequency f _r as shown in "Formula 2" can be set to a high resolution by DDS10, PLL synthesizer 2 Output frequency f
_{The PLL} can be slightly changed, and the number of frequency settings increases.

Embodiment 4 FIG. 4 is a block diagram showing a fourth embodiment of the present invention. In the drawing, new parts are 2, 5 to 10 compared to the conventional example of FIG. The internal configuration of the DDS3 and DDS10 is the same as the conventional one, and the internal configuration of the plurality of PLL synthesizers 2 is the same as the PLL synthesizer 2 of FIG. 1
Is a reference clock oscillator that generates a periodic signal having a specific frequency, 2 is a PLL synthesizer that receives the output signal of the DDS 10 and frequency setting data and generates a second periodic signal having a specified frequency, and 3 is frequency setting data. Generates a third periodic signal having a designated frequency
DS, 4 is a frequency upconverter that receives the output signal of DDS3 and upconverts to a specific frequency, and 5 is a chirp data function generator that receives a chirp setting data and generates a chirp data function for generating a specified chirp waveform. And 6, a memory for receiving the chirp data function and outputting frequency setting data for controlling the plurality of PLL synthesizers 2, DDS3, and DDS10, and 7, a plurality of PLL synthesizers 2 selected by the switch 9. A mixer for synthesizing one periodic signal and a periodic signal from the frequency up-converter 4, a filter 8 for removing unnecessary waves output from the mixer 7, 9 a control signal from the memory 6 and a plurality of PLL synthesizers 2 Switch to select one from 10 receives a frequency setting data and receives a specific frequency. A first periodic signal generated DDS to output a plurality of the PLL synthesizer 2 with.

Next, the operation will be described. The components denoted by the same reference numerals as those in FIG.
DS10 is the same as DDS3, and outputs a periodic signal to a plurality of PLL synthesizers 2 based on the periodic signal from reference clock oscillator 1 and the frequency setting data from memory 6.

[0027] By adopting such a configuration, exhibit the same effect as the second embodiment, also, "number 2" reference signal frequency f _r as shown in the order to be set at a high resolution by DDS10, a plurality of The output frequency f _PLL of each of the PLL synthesizers 2 can be slightly changed, and the number of frequency settings increases.

Embodiment 5 FIG. 5 is a block diagram showing a fifth embodiment of the present invention. In the drawing, new parts are 2, 5 to 8, 10, 11 from the conventional example of FIG.
Is the same as the conventional example. DDS3 and DDS10 and D
The internal configuration of the DS 11 is the same as that of the related art, and the internal configuration of the PLL synthesizer 2 is the same as the PLL synthesizer 2 of FIG. Reference numeral 1 denotes a reference clock oscillator that generates a periodic signal having a specific frequency. Reference numeral 2 denotes a PLL synthesizer that receives an output signal of the DDS 10 and frequency setting data and generates a second periodic signal having a specified frequency.
DDS that generates a fourth periodic signal having a designated frequency in response to the output signal and the frequency setting data.
A frequency upconverter for upconverting to a specific frequency in response to the output signal of 3, a chirp data function generator for receiving a chirp setting data and generating a chirp data function for generating a specified chirp waveform;
6 is a PLL synthesizer 2 receiving the chirp data function.
, A memory for outputting frequency setting data for controlling the DDS3, DDS10 and DDS11, a mixer 7 for synthesizing a periodic signal from the PLL synthesizer 2 and a periodic signal from the frequency upconverter 4, and 8 for an output from the mixer 7. A filter 10 for removing unnecessary waves receives a frequency setting data, generates a first periodic signal having a specific frequency, and outputs it to the PLL synthesizer 2. A DDS 11 receives the frequency setting data and has a specific frequency. 3 is a DDS that generates a periodic signal of No. 3 and outputs it to DDS3.

Next, the operation will be described. The components denoted by the same reference numerals as those in FIG.
DS11 is the same as DDS3, and outputs a periodic signal to DDS3 based on the periodic signal from reference clock oscillator 1 and the frequency setting data from memory 6.

[0030] By adopting such a configuration, effect similar to the third embodiment, also, since the "number 1" reference signal frequency f _r as shown in can be set to a high resolution by DDS11, the output of DDS3 The frequency f _DDS can be slightly changed, and the number of frequency settings increases.

Embodiment 6 FIG. FIG. 6 is a block diagram showing a sixth embodiment of the present invention. In the drawing, the new parts are 2, 5 to 11 compared to the conventional example of FIG. 7, and 1, 3, and 4 are the same as the conventional example. The internal configuration of the DDS3, DDS10 and DDS11 is the same as the conventional one, and the internal configuration of the plurality of PLL synthesizers 2 is the same as the PLL synthesizer 2 of FIG. Reference numeral 1 denotes a reference clock oscillator that generates a periodic signal having a specific frequency. Reference numeral 2 denotes a PLL synthesizer that receives an output signal of the DDS 10 and frequency setting data and generates a second periodic signal having a specified frequency.
DDS that generates a fourth periodic signal having a designated frequency in response to the output signal and the frequency setting data.
A frequency upconverter for upconverting to a specific frequency in response to the output signal of 3, a chirp data function generator for receiving a chirp setting data and generating a chirp data function for generating a specified chirp waveform;
Reference numeral 6 denotes a memory for outputting frequency setting data for controlling the plurality of PLL synthesizers 2, DDS3, DDS10, and DDS11 in response to the chirp data function, and reference numeral 7 denotes a plurality of PLL synthesizers 2 selected by the switch 9.
Among them, a mixer for synthesizing one periodic signal and a periodic signal from the frequency up-converter 4, a filter 8 for removing unnecessary waves from the mixer 7, and a plurality of PLLs 9 receiving a control signal from the memory 6 A switch 10 for selecting one of the synthesizers 2 receives a frequency setting data, generates a first periodic signal having a specific frequency, and generates a plurality of PLs.
The DDS 11 to be output to the L synthesizer 2 is a DDS which receives the frequency setting data, generates a third periodic signal having a specific frequency, and outputs it to the DDS 3.

The components having the same reference numerals as those in FIG. 4 of the fourth embodiment perform the same operations, and the DDS 11 is the same as the DDS 3, and is provided by the periodic signal from the reference clock oscillator 1 and the frequency setting data from the memory 6. A periodic signal is output to DDS3.

[0033] By adopting such a configuration, effect similar to the fourth embodiment, also, since the "number 1" reference signal frequency f _r as shown in can be set to a high resolution by DDS11, the output of DDS3 The frequency f _DDS can be slightly changed, and the number of frequency settings increases.

[0034]

According to the first aspect of the present invention, it is possible to widen a band while keeping spurious due to a quantization error at a low level.

According to the second aspect of the present invention, it is possible to widen the band while keeping the spurious due to the quantization error at a low level, and to increase the switching speed of the frequency setting.

According to the third aspect of the present invention, it is possible to widen the band while keeping the spurious due to the quantization error at a low level, and it is possible to increase the number of frequency settings.

According to the fourth aspect of the present invention, it is possible to widen the band while keeping the spurious due to the quantization error at a low level, to increase the switching speed of the frequency setting, and to further increase the frequency setting number. Can be increased.

Further, according to the fifth aspect, it is possible to widen the band while keeping spurious components due to quantization errors at a low level, and it is possible to increase the number of frequency settings.

According to the sixth aspect of the present invention, it is possible to widen the band while keeping spurious due to quantization errors at a low level, to increase the switching speed of frequency setting, and to further increase the number of frequency settings. Can be increased.

[Brief description of the drawings]

FIG. 1 is a diagram showing Embodiment 1 of a frequency synthesizer according to the present invention.

FIG. 2 is a diagram showing a second embodiment of the frequency synthesizer according to the present invention;

FIG. 3 is a diagram showing a third embodiment of the frequency synthesizer according to the present invention;

FIG. 4 is a diagram showing a fourth embodiment of the frequency synthesizer according to the present invention;

FIG. 5 is a diagram showing a fifth embodiment of the frequency synthesizer according to the present invention;

FIG. 6 is a diagram showing a sixth embodiment of the frequency synthesizer according to the present invention;

FIG. 7 is a diagram illustrating a conventional frequency synthesizer.

FIG. 8 is a diagram illustrating the operation of the DDS.

FIG. 9 is a diagram illustrating an example of a relationship between DDS phase data and amplitude data.

FIG. 10 is a schematic diagram showing a frequency change with respect to time in the related art.

FIG. 11 is a schematic diagram illustrating a frequency change with respect to time according to the first embodiment;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 reference clock oscillator, 2 PLL synthesizer (phase locked loop synthesizer), 3 DDS (direct digital synthesizer), 4 frequency upconverter, 5 chirp data function generator, 6 memory, 7
Mixer, 8 filters, 9 switches, 10 DDS
(Direct Digital Synthesizer), 11 DDS
(Direct digital synthesizer), 21 phase comparator, 22 loop filter, 23 VCO (voltage controlled oscillator), 24 variable frequency divider, 31 phase accumulator, 32 memory, 33 DA converter (digital-to-digital synthesizer)
Analog converter), 34 filters.

Claims (6)

[Claims] 1. A reference clock oscillator for generating a periodic signal having a specific frequency, a phase locked loop synthesizer for receiving a frequency setting data and generating a first periodic signal having a designated frequency, A direct digital synthesizer for receiving the output signal of the direct digital synthesizer to generate a second periodic signal having a specified frequency; a frequency upconverter for receiving an output signal of the direct digital synthesizer to upconvert to a specific frequency; A chirp data function generating means for generating a chirp data function for generating a chirp waveform, a memory receiving the chirp data function and outputting frequency setting data for controlling a phase locked loop synthesizer and a direct digital synthesizer, Synchronized loop synth A frequency synthesizer comprising a mixer for synthesizing a periodic signal from a sizer and a periodic signal from a frequency upconverter, and a filter for removing unnecessary waves from the output of the mixer. 2. A reference clock oscillator for generating a periodic signal having a specific frequency, a plurality of phase-locked loop synthesizers receiving a frequency setting data and generating a first periodic signal having a specified frequency, A direct digital synthesizer that receives a setting data and generates a second periodic signal having a designated frequency; a frequency upconverter that receives an output signal of the direct digital synthesizer to upconvert to a specific frequency; and receives chirp setting data. Data generating means for generating a chirp data function for generating a specified chirp waveform, frequency setting data for controlling a plurality of phase locked loop synthesizers and a direct digital synthesizer in response to the chirp data function Multiple phase locked loops A memory for outputting a control signal for selecting one from the synthesizer, a switch for receiving one of the control signals from the memory and selecting one of the plurality of phase-locked loop synthesizers, and a cycle from the selected phase-locked loop synthesizer A frequency synthesizer comprising a mixer for synthesizing a signal and a periodic signal from a frequency up-converter, and a filter for removing unnecessary waves from an output of the mixer. 3. A reference clock oscillator for generating a periodic signal having a specific frequency, a first direct digital synthesizer receiving a frequency setting data and generating a first periodic signal having a specific frequency, A phase locked loop synthesizer that receives a direct digital synthesizer output signal and frequency setting data to generate a second periodic signal having a specified frequency, and a third periodic signal that receives frequency setting data and has a specified frequency A second direct digital synthesizer for generating a signal, a frequency upconverter for receiving an output signal of the second direct digital synthesizer to upconvert to a specific frequency, and receiving a chirp setting data to generate a specified chirp waveform Chirp data function that generates the chirp data function of Generating means, a memory for receiving a chirp data function and outputting frequency setting data for controlling the phase locked loop synthesizer and the first and second direct digital synthesizers, a periodic signal from the phase locked loop synthesizer and a frequency upconverter A frequency synthesizer comprising a mixer for synthesizing a periodic signal from the mixer and a filter for removing unnecessary waves from the output of the mixer. 4. A reference clock oscillator for generating a periodic signal having a specific frequency, a first direct digital synthesizer for receiving a frequency setting data and generating a first periodic signal having a specific frequency, A plurality of phase-locked loop synthesizers for generating a second periodic signal having a designated frequency in response to an output signal of the direct digital synthesizer and frequency setting data, and a third having a designated frequency in response to the frequency setting data A second direct digital synthesizer for generating a periodic signal of
A frequency up-converter for receiving an output signal of the second direct digital synthesizer to up-convert to a specific frequency, and generating a chirp data function for receiving a chirp setting data and generating a chirp data function for generating a specified chirp waveform Means, frequency setting data for controlling the plurality of phase-locked loop synthesizers and the first and second direct digital synthesizers in response to the chirp data function, and a control signal for selecting one from the plurality of phase-locked loop synthesizers , A switch that receives a control signal from the memory and selects one output from a plurality of phase-locked loop synthesizers, a periodic signal from the selected phase-locked loop synthesizer, and a periodic signal from a frequency upconverter And a mixer that synthesizes Frequency synthesizer, characterized in that is constituted by a filter for removing unnecessary waves from the output of the mixer. 5. A reference clock oscillator for generating a periodic signal having a specific frequency, a first direct digital synthesizer for receiving a frequency setting data and generating a first periodic signal having a specific frequency, A phase locked loop synthesizer that receives a direct digital synthesizer output signal and frequency setting data and generates a second periodic signal having a designated frequency; and receives a frequency setting data and generates a third periodic signal having a specific frequency. The second that occurs
A third direct digital synthesizer that receives an output signal of the second direct digital synthesizer and frequency setting data and generates a fourth periodic signal having a designated frequency;
A frequency up-converter for receiving an output signal of the third direct digital synthesizer to up-convert to a specific frequency, and generating a chirp data function for receiving a chirp setting data and generating a chirp data function for generating a specified chirp waveform Means, a memory for receiving a chirp data function, and outputting frequency setting data for controlling the phase locked loop synthesizer and the first, second and third direct digital synthesizers; and a periodic signal and frequency from the phase locked loop synthesizer. A frequency synthesizer comprising: a mixer for synthesizing a periodic signal from an up-converter; and a filter for removing unnecessary waves from an output of the mixer. 6. A reference clock oscillator for generating a periodic signal having a specific frequency, a first direct digital synthesizer for receiving a frequency setting data and generating a first periodic signal having a specific frequency, A plurality of phase-locked loop synthesizers for receiving the output signal of the direct digital synthesizer and the frequency setting data to generate a second periodic signal having a designated frequency, and receiving a frequency setting data and receiving a third frequency having a specific frequency; A second direct digital synthesizer for generating a periodic signal;
A third direct digital synthesizer for generating a fourth periodic signal having a designated frequency in response to the output signal of the direct digital synthesizer and the frequency setting data, and receiving a specific signal in response to the output signal of the third direct digital synthesizer. A frequency upconverter for upconverting to a frequency, a chirp data function generating means for receiving a chirp setting data and generating a chirp data function for generating a specified chirp waveform, and a plurality of phase synchronization receiving the chirp data function A memory for outputting a loop synthesizer, frequency setting data for controlling the first, second, and third direct digital synthesizers and a control signal for selecting one from a plurality of phase-locked loop synthesizers; and a control signal from the memory Multiple phase synchronization A switch that selects one output from the loop synthesizer, a mixer that combines the periodic signal from the selected phase-locked loop synthesizer and the periodic signal from the frequency up-converter, and a filter that removes unnecessary waves from the output of the mixer Frequency synthesizer characterized by the following.