CN105334500A - S-band radar system frequency source - Google Patents

Abstract

The invention discloses an S-band radar system frequency source which comprises a DDS and interface control module and a frequency synthesizer module, wherein the DDS and interface control module comprises an FPGA core control module, an interface control circuit, a DDS circuit, a clock control circuit and an RS422 interface circuit; according to the interface control circuit, control of a TTL single-ended input/output signal is realized; pulse shape generation is realized by virtue of the DDS circuit; an reference clock is controlled by virtue of the clock control circuit; and data communication between the RS422 interface circuit and the external is realized. The frequency synthesizer module comprises a reference source circuit, an up-conversion link and a control circuit; the reference source circuit is used for generating a DDS clock signal; the up-conversion link is used for outputting an emission excitation signal; the control circuit receives an external power supply and outputs the power supply to each circuit by virtue of DC-DC conversion. The S-band radar system frequency source disclosed by the invention has extremely wide frequency range, good parasitic suppression performance, high output frequency spectrum purity and extremely high frequency resolution, can generate frequency modulation, amplitude modulation and other waveforms and is small in size, low in cost and low in power consumption, and the output frequency is easy to control.

Description

A kind of S-band radar system frequency source

Technical field

The invention belongs to radar system field, particularly a kind of frequency source of S-band radar system.

Background technology

The performance requirement of S-band radar system to the precision of frequency source, resolution, the purity of frequency spectrum, phase noise and frequency hopping switching time, volume etc. is higher.This just requires to select rational frequency synthesis mode, and existing main frequency synthesis mode has: direct modeling synthetic technology, Direct Digital and indirect frequency synthesis technique.

Direct modeling synthetic technology is the one technology comparatively widely of early application.The advantage of this technology has extremely low phase noise and minimum frequency switching time, but shortcoming realizes that equipment volume is large, power consumption is large and easily produces too much spurious components, and the purity of frequency spectrum is not high, is difficult to the non-linear effects suppressing hardware.

Direct Digital represents the direction of frequency synthesis technique, is the digitized key of Microwave Frequency Source.The advantage of this technology is that the fast frequency of Phase Continuation switches, and high frequency resolution, can produce the waveform such as frequency modulation, amplitude modulation and small size, low cost etc., but its limited frequency of operation, higher making an uproar mutually and the spuious usable range limiting it.

The frequency synthesizer that namely indirect frequency synthesis utilizes phase-locked loop pll to form is present stage a kind of widely used technology.The advantage of indirect frequency synthesis technique: have extremely wide frequency range, good Spurious suppression performance, output spectrum purity is very high, and output frequency is easy to control, and volume is little, cost is low.But it is longer that shortcoming is frequency switching time, and frequency resolution is limited.

Above frequency source synthesis mode all can not meet the request for utilization of S-band radar system completely.

Summary of the invention

The present invention seeks to the problem being not suitable for using in radar system for solving existing frequency synthesis technique, providing a kind of S-band radar system frequency source.

Technical scheme of the present invention is as follows:

A kind of S-band radar system frequency source, comprises DDS and interface control module, frequently combines module;

Described DDS and interface control module comprise fpga core control module, interface control circuit, DDS circuit, clock control circuit, RS422 interface circuit, for waveform generation and Interface Controller;

Described fpga core control module is connected with described interface control circuit, DDS circuit, clock control circuit, RS422 interface circuit respectively, UART for RS422 communication controls, the signals collecting of TTL single ended signal, the state of TTL Single-end output signal control, the control of input reference clock FPGA_CLK, and produce waveform by DDS controller control DDS chip, output linearity FM signal;

Described interface control circuit comprises TTL single ended input interface, TTL Single-end output interface, signal acquisition module, AGC/ frequency hopping controller, described TTL single ended input interface 16 road TTL single ended signal, send into fpga core control module by described signal acquisition module, complete the collection of TTL single ended signal; Fpga core control module makes described TTL Single-end output interface export 16 road TTL Single-end output signals by described AGC/ frequency hopping controller, completes the control of TTL Single-end output signal;

Described DDS circuit comprises DDS chip, DDS controller, and described DDS controller receives the control signal of fpga core control module, controls the generation that described DDS chip realizes waveform, exports the linear FM signal of the maximum 11MHz of 180MHz bandwidth;

Described clock control circuit comprises clock controller, and described clock controller receives the reference clock FPGA_CLK signal of 100MHz, sends into fpga core control module, completes the control of input reference clock FPGA_CLK;

Described RS422 interface circuit comprises RS422 interface, URAT controller, described RS422 interface comprises 2 road RS485-4W/RS422 signals, fpga core control module is connected to by described URAT controller, the UART completing RS422 communication controls, and realizes the data communication of DDS and interface control module and outside;

Described frequency is combined module and is comprised reference source circuit, up-conversion link, control circuit;

Described reference source circuit adopts Direct synthesis technique to produce the DDS clock signal of 1000MHz by frequency multiplier;

Described up-conversion link adopts superhet frequency mixing technique and indirect frequency synthesis technique, and the local oscillation signal of 3180MHz ± 80MHz that the 180MHz baseband signal that described DDS and interface control module are produced and PLL produce exports the transmitting pumping signal of 3000MHz ± 80MHz after mixing, filtering, modulation, amplification;

Described control circuit receives external power source and flow to each circuit after DC-DC conversion, is carried out the control of PLL frequency hopping and switch by interface transmission TTL signal simultaneously.

Advantageous Effects of the present invention is:

Invention introduces DDS, PLL, directly synthesize the frequency agility rate technology combined, traditional frequency source is made to have extremely wide frequency range, good Spurious suppression performance, higher output spectrum purity, high frequency resolution, the waveform such as frequency modulation, amplitude modulation and output frequency can be produced be easy to control, the advantages such as volume is little, cost is low, power consumption is little.

Simultaneity factor have employed modular technology, signal Autonomous test technology, improves system reliability and electromagnetic shielding capability, reduces system bulk, reduces maintenance difficulty.

Accompanying drawing explanation

Fig. 1 is DDS of the present invention and interface control module theory diagram.

Fig. 2 is that frequency of the present invention combines module principle block diagram.

Embodiment

Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described further.

S-band radar system frequency source of the present invention comprises DDS and interface control module, frequently combines module.

DDS and interface control module mainly complete Interface Controller and waveform generation function, and its theory diagram as shown in Figure 1.DDS and interface control module comprise fpga core control module, DDS controller, DDS chip, clock controller, URAT controller, signal acquisition module, AGC/ frequency hopping controller, RS422 interface, TTL single ended input interface, TTL Single-end output interface.

Wherein signal acquisition module, AGC/ frequency hopping controller, TTL single ended input interface, TTL Single-end output interface composition interface control circuit.Interface control circuit mainly realizes the control to TTL single ended signal and TTL Single-end output signal.

DDS controller, DDS chip (AD9910) form DDS circuit.DDS main circuit will realize the generation of pulse waveform.

Clock controller composition clock control circuit.Clock control circuit mainly realizes the control to input reference clock FPGA_CLK

URAT controller, RS422 interface composition RS422 interface circuit.RS422 interface circuit mainly realizes the data communication of DDS and interface control module and outside.

The UART that fpga core control module realizes RS422 communication controls, the signals collecting of TTL single ended signal, the state of TTL Single-end output signal control, the control of input reference clock FPGA_CLK, and the generation of waveform is realized by DDS controller control DDS chip, export the linear FM signal of the maximum 11MHz of 180MHz bandwidth.

DDS and interface control module meet high frequency resolution required by radar system, the waveform such as frequency modulation, amplitude modulation can be produced and output frequency be easy to control, the requirements such as volume is little, cost is low, power consumption is little, lightweight.

Frequently module principle block diagram is combined as shown in Figure 2.Frequently combine module and comprise reference source circuit, up-conversion link, control circuit three part.

Reference source circuit adopts Direct synthesis technique to produce the DDS clock signal of 1000MHz by frequency multiplier.

Up-conversion link adopts superhet frequency mixing technique and indirect frequency synthesis technique.The 180MHz baseband signal of DDS and interface control module, the local oscillation signal 3180MHz ± 80MHz produced with PLL exports the transmitting pumping signal Ft of 3000MHz ± 80MHz after mixing, filtering, modulation, amplification.

Control circuit receives external power source and flow to each circuit after DC-DC conversion, is carried out the control of PLL frequency hopping and switch by interface transmission TTL signal simultaneously.

Above-described is only the preferred embodiment of the present invention, the invention is not restricted to above embodiment.Be appreciated that the oher improvements and changes that those skilled in the art directly derive without departing from the spirit and concept in the present invention or associate, all should think and be included within protection scope of the present invention.

Claims (1)

1. a S-band radar system frequency source, is characterized in that: comprise DDS and interface control module, frequently combine module;

Described DDS and interface control module comprise fpga core control module, interface control circuit, DDS circuit, clock control circuit, RS422 interface circuit, for waveform generation and Interface Controller;

Described fpga core control module is connected with described interface control circuit, DDS circuit, clock control circuit, RS422 interface circuit respectively, UART for RS422 communication controls, the signals collecting of TTL single ended signal, the state of TTL Single-end output signal control, the control of input reference clock FPGA_CLK, and produce waveform by DDS controller control DDS chip, output linearity FM signal;

Described interface control circuit comprises TTL single ended input interface, TTL Single-end output interface, signal acquisition module, AGC/ frequency hopping controller, described TTL single ended input interface 16 road TTL single ended signal, send into fpga core control module by described signal acquisition module, complete the collection of TTL single ended signal; Fpga core control module makes described TTL Single-end output interface export 16 road TTL Single-end output signals by described AGC/ frequency hopping controller, completes the control of TTL Single-end output signal;

Described DDS circuit comprises DDS chip, DDS controller, and described DDS controller receives the control signal of fpga core control module, controls the generation that described DDS chip realizes waveform, exports the linear FM signal of the maximum 11MHz of 180MHz bandwidth;

Described clock control circuit comprises clock controller, and described clock controller receives the reference clock FPGA_CLK signal of 100MHz, sends into fpga core control module, completes the control of input reference clock FPGA_CLK;

Described RS422 interface circuit comprises RS422 interface, URAT controller, described RS422 interface comprises 2 road RS485-4W/RS422 signals, fpga core control module is connected to by described URAT controller, the UART completing RS422 communication controls, and realizes the data communication of DDS and interface control module and outside;

Described frequency is combined module and is comprised reference source circuit, up-conversion link, control circuit;

Described reference source circuit adopts Direct synthesis technique to produce the DDS clock signal of 1000MHz by frequency multiplier;

Described up-conversion link adopts superhet frequency mixing technique and indirect frequency synthesis technique, and the local oscillation signal of 3180MHz ± 80MHz that the 180MHz baseband signal that described DDS and interface control module are produced and PLL produce exports the transmitting pumping signal of 3000MHz ± 80MHz after mixing, filtering, modulation, amplification;

Described control circuit receives external power source and flow to each circuit after DC-DC conversion, is carried out the control of PLL frequency hopping and switch by interface transmission TTL signal simultaneously.