CN204967791U

CN204967791U - UHF doppler radar system high stable clock network

Info

Publication number: CN204967791U
Application number: CN201520810925.2U
Authority: CN
Inventors: 文必洋; 侯义东; 王才军; 田应伟; 谭剑
Original assignee: Wuhan University WHU
Current assignee: Wuhan University WHU
Priority date: 2015-10-19
Filing date: 2015-10-19
Publication date: 2016-01-13
Anticipated expiration: 2025-10-19

Abstract

The utility model provides a UHF doppler radar system high stable clock network, including high stable temperature compensation crystal oscillator, digital phase -locked loop DSPLL module, low shake clock fan out modular, ordinary crystal oscillator, FPGA, the temperature compensation crystal oscillator produces low shake 10MHz clock source as DSPLL's reference clock, and the DSPLL doubling of frequency produces two way clocks of 983.04MHz and 81.92Mhz, and the 983.04Mhz clock is directly as the reference clock in data signal source, obtain behind the 81.92Mhz clock process clock fan out modular 9 the tunnel together the frequency in -phase clock regard as 8 way analog -to -digital conversion module and FPGA clock respectively, utilize the inside PLL of FPGA to generate 10MHz clock output conduct USB module reference clock simultaneously, inside PLL's reference clock derives from ordinary 50Mhz crystal oscillator. The utility model discloses a reference clock is whole to be derived from with a high stability temperature compensation crystal oscillator, utilizes digital phase -locked loop to produce the required frequency of each module, has improved the phase stability of system greatly, and whole clock system simple and clear easily realizes.

Description

A kind of UHF Doppler radar system high stable clock network

Technical field

The utility model belongs to Radar Technology field, particularly relates to a kind of UHF Doppler radar system high stable clock network.

Background technology

Doppler radar is that a kind of Doppler effect that utilizes is to the radar of the position and speed of related movement that detect moving target; Radar emission linear frequency sweep continuous wave, reflection echo is understood after running into target, receiver utilizes local oscillation signal to go frequency sweep to echo, carry out twice Fourier transform again and extract phase information, this message reflection velocity information of target, therefore require very high to the phase stability of system, if the phase place of system own is in skew, then can wrong being reflected in the velocity information of target.

Unified high-quality clock source is not adopted during traditional receiver clock network design, but derived digital signal reference clock and digital local oscillator reference clock adopt two independently clock sources, these two modules input independently clock source like this, both phase difference uncontrollable, thus cause the phase stability of system very poor.

Summary of the invention

For background technology Problems existing, the utility model provides a kind of UHF Doppler radar system high stable clock network.The reference clock of whole system is all derived from same high stability temperature compensating crystal oscillator by the utility model, utilize digital phase-locked loop to produce frequency needed for modules, even if there is phase difference between modules reference clock like this, but difference is fixing and can uses software compensation, substantially improves the phase stability of system like this.Whole clock network is simple and clear, is easy to realize.

The technical solution of the utility model is as follows:

A kind of UHF Doppler radar system high stable clock network, comprises high stable temperature compensating crystal oscillator, digital phase-locked loop DSPLL module, low-jitter clock fan-out modular, common crystals, FPGA and USB module; High stable temperature compensating crystal oscillator, digital phase-locked loop DSPLL module, low-jitter clock fan-out modular connect successively, and common crystals is connected with FPGA; FPGA and digital phase-locked loop DSPLL model calling; USB module is connected with FPGA;

High stable temperature compensating crystal oscillator produces the reference clock of low jitter 10MHz clock source as digital phase-locked loop DSPLL module, digital phase-locked loop DSPLL module frequency multiplication produces 983.04MHz and 81.92Mhz two-way clock, 983.04MHz clock directly exports, 81.92Mhz clock obtains 9 tunnels with frequency in-phase clock after low-jitter clock fan-out modular, wherein 8 tunnels directly export, and an other road is as FPGA system clock; Common 50Mhz crystal oscillator is as another clock source of FPGA, and utilize the inner PLL of FPGA to generate 10MHz clock simultaneously and export as USB module reference clock, the reference clock of inner PLL derives from common 50Mhz crystal oscillator.

Described temperature compensating crystal oscillator frequency stability should be less than 10ppm, and phase noise is low as far as possible.

Described digital phase-locked loop DSPLL module uses the digital phase-locked loop chip that a model of SILICONLABS company is SI5324.

Described low-jitter clock fan-out modular uses a model of TI company to be cdclvd1216 chip.

Described FPGA selects ALTERA company CYCLONEV series, and generates NIOSII flush bonding processor therein for initialization DSPLL module.

Compared with prior art, the utility model has the following advantages and beneficial effect:

1, the utility model circuit structure is simple, system is clear, and clock frequency stability is high, phase noise is low, system phase stability is high;

2, the digital phase-locked loop in the utility model is configured by FPGA, thus can change parameter flexibly to export the clock of various frequency for being operated in the radar of different-waveband, portable high.

Accompanying drawing explanation

Fig. 1 is structural representation of the present utility model.

Fig. 2 is the circuit diagram of digital phase-locked loop.

Fig. 3 is Doppler's spectrogram that the utility model is applied in field test in UHF Doppler radar and obtains.

Fig. 4 is the DR figure that the utility model is applied in that field test in UHF Doppler radar obtains.

Embodiment

Describe in detail below in conjunction with drawings and Examples:

The utility model comprises high stable temperature compensating crystal oscillator, digital phase-locked loop DSPLL module, low-jitter clock fan-out modular, common crystals, FPGA as shown in Figure 1; Wherein temperature compensating crystal oscillator produces the reference clock of low jitter 10MHz clock source as DSPLL, DSPLL frequency multiplication produces 983.04MHz and 81.92Mhz two-way clock, 983.04Mhz clock is directly as the reference clock of derived digital signal, and 81.92Mhz clock obtains 9 tunnels with frequency in-phase clock respectively as 8 road analog-to-digital conversion modules and FPGA system clock after oversampling clock fan-out modular; In addition, common 50Mhz crystal oscillator is as another clock source of FPGA, and utilize the inner PLL of FPGA to generate 10MHz clock simultaneously and export as USB module reference clock, the reference clock of inner PLL derives from common 50Mhz crystal oscillator.

FPGA selects the CYCLONEV series of ALTERA company, and in FPGA, generate NIOSII flush bonding processor, NIOSII can configure initiation parameter to digital phase-locked loop; Owing to not having clock to export before digital phase-locked loop no initializtion, therefore need to be used alone the reference clock of a common crystals as NIOSII.Host computer can be communicated with NIOSII by USB module, thus can change phase-locked-loop configuration parameter flexibly.

Digital phase-locked loop selects the SI5324 of SILICONLABS company, and its core circuit figure as shown in Figure 2; Clock fan-out chip selects the cdclvd1216 of TI company, and clock signal cabling all uses LVPECL difference scheme, for single-ended clock, then transmits after using transformer to be converted to difference; Difference cabling on PCB adopts microstrip line, and characteristic impedance is designed to 100 ohm, in order to prevent reflection, to differential lines termination 100 Ohmic resistance.

USB module was be the data transmission scheme between radar system and host computer originally, here simultaneously also can as the path of host computer configurable clock generator network, and USB main control chip selects CY7C68013.

After system electrification, first automatically FPGA program is loaded, load NIOSII successfully and can normally export required clock according to default parameters by SPI interface configuration digital phase-locked loop, if want to change clock frequency, then change the parameter of NIOSII storage by host computer.

Fig. 3 and Fig. 4 is the datagram that the utility model is applied in field test in UHF Doppler radar and obtains, go out to have very high peak value at Prague frequency as can clearly see from the figure, signal to noise ratio can reach about 40dB, the phase stability of this illustrative system is fine, the wave in river can be reflected well, the information such as stream.

Claims

1. a UHF Doppler radar system high stable clock network, is characterized in that:

Comprise high stable temperature compensating crystal oscillator, digital phase-locked loop DSPLL module, low-jitter clock fan-out modular, common crystals, FPGA and USB module; High stable temperature compensating crystal oscillator, digital phase-locked loop DSPLL module, low-jitter clock fan-out modular connect successively, and common crystals is connected with FPGA; FPGA and digital phase-locked loop DSPLL model calling; USB module is connected with FPGA;

2. a kind of UHF Doppler radar system high stable clock network according to claim 1, is characterized in that: the frequency stability of described high stable temperature compensating crystal oscillator is less than 10ppm, and phase noise is lower than 100dB.

3. a kind of UHF Doppler radar system high stable clock network according to claim 1, is characterized in that: described digital phase-locked loop DSPLL module uses the digital phase-locked loop chip that the model of SILICONLABS company is SI5324.

4. a kind of UHF Doppler radar system high stable clock network according to claim 1, is characterized in that: described low-jitter clock fan-out modular uses the model of TI company to be cdclvd1216 chip.

5. a kind of UHF Doppler radar system high stable clock network according to claim 1, it is characterized in that: described FPGA selects ALTERA company CYCLONEV series, and generate NIOSII flush bonding processor therein for initialize digital phase-locked loop DSPLL module.

6. a kind of UHF Doppler radar system high stable clock network according to claim 1, is characterized in that: described reference clock PCB cabling all adopts high-quality LVPEL difference scheme, and cabling characteristic impedance is designed to 100 ohm, and isometric cabling.