CN203014777U

CN203014777U - Simplified frequency agility frequency synthesizer based on DDS non-linear characteristics

Info

Publication number: CN203014777U
Application number: CN 201220733611
Authority: CN
Inventors: 杨光; 孙敏; 宋烨曦
Original assignee: Sichuan Jiuzhou Electric Group Co Ltd
Current assignee: Sichuan Jiuzhou Electric Group Co Ltd
Priority date: 2012-12-28
Filing date: 2012-12-28
Publication date: 2013-06-19
Anticipated expiration: 2022-12-28

Abstract

The utility model discloses a simplified frequency agility frequency synthesizer based on DDS non-linear characteristics relating to the direct digital frequency synthesis technology field. The object of the utility model is to provide a frequency agility frequency synthesizer having a small size and low costs. The utility model is characterized in that a clock circuit, a DDS chip, a frequency control circuit, and a frequency selection circuit are provided; an output end of the clock circuit is connected with a clock signal input end of the DDS chip; an output end of the frequency control circuit is connected with a frequency control end of the DDS chip; and a frequency output end of the DDS chip is connected with an input end of the frequency selection circuit.

Description

A kind of agility scheme synthesizer of simplifying based on the DDS nonlinear characteristic

Technical field

The utility model relates to a kind of Direct Digital frequency synthesis technique field, is specifically related to a kind of agility scheme synthesizer of simplifying based on the DDS nonlinear characteristic.

Background technology

The Direct Digital frequency synthesis is exactly the said DDS(Direct Digital of people Synthesis).Has frequency switching time speed based on the agility scheme synthesizer of DDS fast, frequency resolution is high, and the frequency conversion phase place is continuous, can directly export the characteristics such as modulation signal, be widely used in now the fields such as radar system, communication system, tool has a broad prospect of the use.Yet, compare the frequency hopping synthesizer of realizing with phase-locked loop, existing agility scheme synthesizer realize the circuit more complicated, the module volume is also larger.

The utility model content

Goal of the invention of the present utility model is: for the problem of above-mentioned existence, provide the agility scheme synthesizer that a kind of volume is little, cost is low.

The technical solution adopted in the utility model is such: comprise clock circuit, DDS chip, frequency control circuit and frequency selection circuit; The output of described clock circuit is connected with the clock signal input terminal of DDS chip; The output of frequency control circuit is connected with the frequency control terminal of DDS chip; The frequency output terminal of DDS chip is connected with the input of frequency selection circuit.

Preferably, also comprise amplifying circuit and second level bandwidth-limited circuit; The output of described frequency selection circuit is connected with the input of amplifying circuit, and the output of amplifying circuit is connected with the input of second level bandwidth-limited circuit.

Preferably, described frequency selection circuit is first order bandwidth-limited circuit.

Preferably, the clock signal of described clock circuit output 1GHz.

Preferably, described frequency control circuit is used for controlling the Frequency Hopping Signal that the DDS chip produces 50 ~ 200MHz.

Preferably, the passband frequency range of first order bandwidth-limited circuit and second level bandwidth-limited circuit is 1050 ~ 1200MHz.

Preferably, described clock circuit comprises 20MHz crystal oscillator, phase-locked loop, loop filter, voltage controlled oscillator and power splitter; Described phase-locked loop, loop filter, voltage controlled oscillator and power splitter are linked in sequence; Wherein, described 20MHz crystal oscillator is connected with the reference clock signal input of phase-locked loop; An output of described power splitter is as the output of clock circuit, and another output is connected with the signal input part of phase-locked loop.

Preferably, described frequency control circuit is CPLD.

In sum, owing to having adopted technique scheme, the beneficial effects of the utility model are:

1, save mixting circuit part in traditional agility scheme synthesizer, simplified modular circuit.

2, when simplifying circuit, do not affect the realization of the index such as spuious inhibition.

Description of drawings

Fig. 1 is the utility model the first embodiment schematic block circuit diagram.

Fig. 2 is the utility model the second embodiment schematic block circuit diagram.

Fig. 3 is the utility model the 3rd embodiment schematic block circuit diagram.

Embodiment

Below in conjunction with accompanying drawing, the utility model is described in detail.

In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explaining the utility model, and be not used in restriction the utility model.

As shown in Figure 1, the first embodiment of the disclosed agility scheme synthesizer of the utility model is such: comprise clock circuit, DDS chip, frequency control circuit and frequency selection circuit.The output of described clock circuit is connected with the clock signal input terminal of DDS chip; The output of frequency control circuit is connected with the frequency control terminal of DDS chip; The frequency output terminal of DDS chip is connected with the input of frequency selection circuit.Concrete, described frequency selection circuit is used for the target signal filter of signal except echo signal with the output of DDS chip, and it can be first order bandwidth-limited circuit.

As Fig. 2, in the second embodiment of the present utility model, also comprise amplifying circuit and second level bandwidth-limited circuit; The output of described frequency selection circuit is connected with the input of amplifying circuit, and the output of amplifying circuit is connected with the input of second level bandwidth-limited circuit.In the present embodiment, amplifying circuit is preferably the two-stage amplifying circuit.The passband frequency range of the second level bandwidth-limited circuit of setting up in the present embodiment is identical with first order bandwidth-limited circuit, and purpose is as far as possible that other target signal filters except echo signal are clean.

As Fig. 3, on the basis of the utility model the second embodiment, clock circuit wherein comprises 20MHz crystal oscillator, phase-locked loop, loop filter, voltage controlled oscillator and power splitter; Described phase-locked loop, loop filter, voltage controlled oscillator and power splitter are linked in sequence; Wherein, described 20MHz crystal oscillator is connected with the reference clock signal input of phase-locked loop; An output of described power splitter is as the output of clock circuit, and another output is connected with the signal input part of phase-locked loop.

In another embodiment of the utility model, described frequency control circuit can be CPLD.

The operation principle of the disclosed frequency synthesizer of the utility model is: the clock circuit clocking, generally elect clock signal frequency as signal that frequency is 1GHz, and frequency control circuit, namely CPLD, control the Frequency Hopping Signal that the DDS chip produces the certain frequency scope.Because being actually, the output frequency of DDS chip produced by its inner DAC, and due to the non-linear effects of DAC self, the DDS chip is when the signal of this particular frequency range of output, also can be accompanied by other signals that this particular frequency range signal of output and clock signal mixing produce, just exist us to expect to obtain L-band and above signal in described other signals.Pass through frequency selection circuit, just can select the signal of the frequency range that we need, be echo signal, then echo signal just can be exported by amplifying circuit and second level band pass filter and be satisfied the echo signal that specific engineering objective (comprising that output signal power index, spuious inhibition index, harmonic wave suppress index etc.) requires.

In order to satisfy the requirement of spuious inhibition, we produce the Frequency Hopping Signal of 200MHz left and right, for example 50 ~ 200MHz by general control DDS chip.

The below is the labor the beneficial effects of the utility model against existing technologies:

Because the output frequency of DDS is relevant with its clock signal, generally be no more than 40% of clock signal frequency.Another embodiment of the present utility model uses the AD9910 chip as the DDS chip, and its clock signal is up to 1GHz.That is to say, the output frequency of this DDS is up to 400MHz.

In order to realize L-band and above output, traditional practice is to add a mixting circuit at the DDS output.Such as exporting for the frequency that realizes 1050MHz ~ 1200MHz, traditional way is, DDS output 50MHz ~ 200MHz is as the input of mixting circuit, adopt another phase-locked loop circuit to produce the 1GHz signal as the local oscillator of frequency mixer, getting at last up-conversion exports as mixting circuit, signal after up-conversion passes through filtering, amplification again, realizes that at last frequency range is the signal output of 1050MHz ~ 1200MHz.As seen, traditional agility scheme synthesizer comprises the generation circuit of mixting circuit and local oscillation signal, and circuit structure is comparatively complicated.

And the utility model utilizes the nonlinear characteristic of DDS chip internal DAC cleverly, save mixting circuit in traditional agility scheme synthesizer and the generation circuit of local oscillation signal, simplified greatly modular circuit, dwindled the module volume, alleviate module weight, reduced the module cost.

Consider and to cause that when simplifying circuit the circuit noise restraint reduces, the utility model is further controlled the Frequency Hopping Signal that the DDS chip produces suitable frequency band range, 50 ~ 200MHz for example, and the parameter of appropriate design filter circuit and amplifying circuit, realize spuious being better than-this index request of 60dBc in band.

The above is only preferred embodiment of the present utility model; not in order to limit the utility model; all any modifications of doing within spirit of the present utility model and principle, be equal to and replace and improvement etc., within all should being included in protection range of the present utility model.

Claims

1. an agility scheme synthesizer of simplifying based on the DDS nonlinear characteristic, is characterized in that, comprises clock circuit, DDS chip, frequency control circuit and frequency selection circuit;

The output of described clock circuit is connected with the clock signal input terminal of DDS chip; The output of frequency control circuit is connected with the frequency control terminal of DDS chip; The frequency output terminal of DDS chip is connected with the input of frequency selection circuit.

2. agility scheme synthesizer according to claim 1, is characterized in that, also comprises amplifying circuit and second level bandwidth-limited circuit; The output of described frequency selection circuit is connected with the input of amplifying circuit, and the output of amplifying circuit is connected with the input of second level bandwidth-limited circuit.

3. agility scheme synthesizer according to claim 1 and 2, is characterized in that, described frequency selection circuit is first order bandwidth-limited circuit.

4. agility scheme synthesizer according to claim 3, is characterized in that, the clock signal of described clock circuit output 1GHz.

5. agility scheme synthesizer according to claim 4, is characterized in that, described frequency control circuit is used for controlling the Frequency Hopping Signal that the DDS chip produces 50 ~ 200MHz.

6. agility scheme synthesizer according to claim 5, is characterized in that, the passband frequency range of first order bandwidth-limited circuit and second level bandwidth-limited circuit is 1050 ~ 1200MHz.

7. agility scheme synthesizer according to claim 1 or 5, is characterized in that, described clock circuit comprises 20MHz crystal oscillator, phase-locked loop, loop filter, voltage controlled oscillator and power splitter; Described phase-locked loop, loop filter, voltage controlled oscillator and power splitter are linked in sequence; Wherein, described 20MHz crystal oscillator is connected with the reference clock signal input of phase-locked loop; An output of described power splitter is as the output of clock circuit, and another output is connected with the signal input part of phase-locked loop.

8. agility scheme synthesizer according to claim 7, is characterized in that, described frequency control circuit is CPLD.