CN205212817U - Broadband frequency agility frequency synthesizer - Google Patents
Broadband frequency agility frequency synthesizer Download PDFInfo
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- CN205212817U CN205212817U CN201521086298.9U CN201521086298U CN205212817U CN 205212817 U CN205212817 U CN 205212817U CN 201521086298 U CN201521086298 U CN 201521086298U CN 205212817 U CN205212817 U CN 205212817U
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Abstract
The utility model discloses a broadband frequency agility frequency synthesizer, it relates to the frequency synthesizer of this vibration source in the communications field. It comprises parts such as frequency multiplier, wave filter, frequency hopping phase -locked loop circuit, amplifier, switch, FPGA. It carries out frequency control through serial interface, and is inside by frequency hopping phase -locked loop circuit, switch and wave filter realization frequency synthesis purpose. The utility model has the advantages of export step -by -step little, quick frequency hopping, phase noise low, stray low, the harmonic is low, frequency range is wide, integrate the degree height, low power dissipation, simple structure, stable performance are reliable, can normally work than under the adverse circumstances, the specially adapted is as this vibration source of anti -interference satellite communication equipment.
Description
Technical field
The utility model relates to a kind of broadband agility scheme synthesizer in wireless communication field, is specially adapted to the local vibration source as anti-interference satellite communication equipment.
Background technology
In order to increase anti-interference of communication system and Anti TBIgG ability, usually adopting frequency hopping communications mode, especially Anti-Jamming Satellite Communications Systems, requiring that local vibration source possesses the feature of fast frequency-hopped, little stepping and miniaturization, low-power consumption; Simultaneously along with the raising of satellite communication frequency range, available bandwidth is also increased to the 1600MHz of Ka frequency range by the 500MHz of Ku frequency range at increase communication bandwidth, require that local vibration source also should possess the feature of Broadband emission.The local vibration source of current satellite communication equipment all can not meet the requirement of fast frequency-hopped, little stepping and miniaturization, low-power consumption simultaneously.
Utility model content
The purpose of this utility model be to avoid the weak point in above-mentioned background technology and provide a kind of can as the Frequency Hopping Synthesizer of the anti-interference satellite communication equipment local vibration source of frequency hopping, the utility model normally can work at comparatively rugged environment-40 DEG C ~+85 DEG C, also have export that stepping is little, fast frequency-hopped, phase noise is low, spuious low, harmonic wave is low, wide frequency range, integration degree are high, low in energy consumption, structure is simple, the feature such as stable and reliable for performance.
The purpose of this utility model is achieved in that a kind of broadband agility scheme synthesizer, comprises frequency multiplier 1, power splitter 2, FPGA5, the first switch 6, second switch 7, first filter 8, second filter 9, the 3rd switch 10 and amplifier 11; It is characterized in that, also comprise the first frequency hopping phase-locked loop circuit 3 and the second frequency hopping phase-locked loop circuit 4; The first described frequency hopping phase-locked loop circuit 3 and the second frequency hopping phase-locked loop circuit 4 are integrated with phase-locked loop and VCO; Wherein the input port of frequency multiplier 1 is connected with outside, and output port is connected with the input port of power splitter 2; The output port of power splitter 2 is connected with the input port of the first frequency hopping phase-locked loop circuit 3 with the second frequency hopping phase-locked loop circuit 4 respectively; The output port of FPGA5 is connected with the input port of the first frequency hopping phase-locked loop circuit 3 with the second frequency hopping phase-locked loop circuit 4 respectively; First frequency hopping phase-locked loop circuit 3 is all connected with the first switch 6 with the output port of the second frequency hopping phase-locked loop circuit 4; The output port of the first switch 6 is connected with the input port of second switch 7; The output port of second switch 7 is connected with the input port of the first filter 8 with the second filter 9 respectively; First filter 8 is all connected with switch 10 with the output port of the second filter 9; The output port of switch 10 is connected with the input port of amplifier 11; Amplifier 11 is connected with outside.
Wherein, the first frequency hopping phase-locked loop circuit 3 and the second frequency hopping phase-locked loop circuit 4 are made up of regulator block 12, phase-locked chip 13, amplifier 14, control circuit 15 and reference signal 16, resistor R1, R2 and capacitor C1, C2 and C3; The output port of regulator block 12 is connected with the input port of phase-locked chip 13; The output port of phase-locked chip 13 is connected with the input port of amplifier 14; The output port of reference signal 16 is connected with the input port of phase-locked chip 13; The output port of control circuit 15 is connected with the input port of regulator block 12 with phase-locked chip 13 respectively; Capacitor C1, C2 and C3 are in parallel, and one end is connected with phase-locked chip 13, other end ground connection; Resistor R1 is connected between C1 and C2, and resistor R2 is connected between C1 and C3.
Wherein, the first frequency hopping phase-locked loop circuit 3 and the second frequency hopping phase-locked loop circuit 4 carry out pingpang handoff by the first switch 6; First filter 8 and the second filter 9 carry out region filtering by second switch 7 and the 3rd switch 10.
Wherein, first frequency hopping phase-locked loop circuit 3 and the inner integrated VCO of the second frequency hopping phase-locked loop circuit 4 can carry out frequency preset fast, by the control signal of FPGA5, the output of VCO accurately can be preset at a narrow bandwidth range rapidly, and then optimize the locking time of frequently combining, reduce the residence time of frequency.
The utility model has the following advantages compared with background technology:
1. the utility model adopts the fractional frequency division pattern of phase-locked loop circuit to realize little stepping output characteristic; Fast frequency-hopped and the Broadband emission of frequency synthesizer is realized by pingpang handoff and region filtering.
2. the utility model integration degree is high, low in energy consumption, and debugging work load is little, normally can work at comparatively rugged environment temperature-40 DEG C ~+85 DEG C.
3. the utility model compact conformation, volume is little, and cost is low, has application value.
Accompanying drawing explanation
Fig. 1 is functional-block diagram of the present utility model.
Fig. 2 is the electrical schematic diagram of the utility model frequency hopping phase-locked loop circuit.
Embodiment
See figures.1.and.2, the utility model is made up of frequency multiplier 1, power splitter 2, FPGA5, the first switch 6, second switch 7, first filter 8, second filter 9, the 3rd switch 10, amplifier 11, first frequency hopping phase-locked loop circuit 3 and the second frequency hopping phase-locked loop circuit 4; First frequency hopping phase-locked loop circuit 3 and the second frequency hopping phase-locked loop circuit 4 are integrated with phase-locked loop and VCO.Fig. 1 is the electric functional-block diagram of the utility model embodiment, and embodiment presses Fig. 1 connection line.Wherein the input port of frequency multiplier 1 is connected with external 10MHz reference data source signal, and output port is connected with the input port of power splitter 2, and frequency multiplier 1 exports the fifth harmonic signal of reference frequency; The output port of power splitter 2 is connected with the input port of the first frequency hopping phase-locked loop circuit 3 with the second frequency hopping phase-locked loop circuit 4 respectively, and the frequency-doubled signal that frequency multiplier 1 exports is divided into two by power splitter 2, and embodiment adopts commercially available special SD-2 to make; Frequency-doubled signal is as the clock signal of the first frequency hopping phase-locked loop circuit 3 and the second frequency hopping phase-locked loop circuit 4, and embodiment adopts commercially available special frequency multiplier RMK-5-51+ to make; FPGA5 is used for controlling frequency hopping phase-locked loop circuit and switching circuit, and the output port of FPGA5 is connected with the input port of the first frequency hopping phase-locked loop circuit 3 with the second frequency hopping phase-locked loop circuit 4 respectively; Embodiment adopts commercially available special EP3C10F256I7N to make; First frequency hopping phase-locked loop circuit 3 is all connected with the first switch 6 with the output port of the second frequency hopping phase-locked loop circuit 4; The output port of the first switch 6 is connected with the input port of second switch 7; The output port of second switch 7 is connected with the input port of the first filter 8 with the second filter 9 respectively; First filter 8 is all connected with switch 10 with the output port of the second filter 9; The output port of switch 10 is connected with the input port of amplifier 11; Amplifier 11 is connected with outside.First switching circuit 6, second switch circuit 7, the 3rd switching circuit 10 are used for pingpang handoff phase-locked loop circuit and region filtering, and embodiment adopts commercially available special HMC232LP4 to make; First filter circuit 8, second filter circuit 9 is used for carrying out region filtering to local oscillation signal, and embodiment adopts 7MP2700U1000-KB, 7MP3700U1000-KB of No.13 Inst., Chinese Electronic Science & Technology Group Co to make; Amplifier 11 pairs of local oscillation signals amplify, and embodiment adopts commercially available special SBB-3089Z to make.
The utility model first frequency hopping phase-locked loop circuit 3 and the second frequency hopping phase-locked loop circuit 4 are made up of regulator block 12, phase-locked chip 13, amplifier 14, control circuit 15, reference signal 16, resistor R1, R2 capacitor C1, C2 and C3.Fig. 2 is the electrical schematic diagram of the utility model first frequency hopping phase-locked loop circuit 3 and the second frequency hopping phase-locked loop circuit 4, and embodiment presses Fig. 2 connection line.The output port of regulator block 12 is connected with the input port of phase-locked chip 13; The output port of phase-locked chip 13 is connected with the input port of amplifier 14; The output port of reference signal 16 is connected with the input port of phase-locked chip 13; The output port of control circuit 15 is connected with the input port of regulator block 12 with phase-locked chip 13 respectively; Capacitor C1, C2 and C3 are in parallel, and one end is connected with phase-locked chip 13, other end ground connection; Resistor R1 is connected between C1 and C2, and resistor R2 is connected between C1 and C3.Its effect of phase-locked chip 13 exports broadband lockin signal, and embodiment adopts commercially available special phase-locked loop chip HMC833LP6GE to make; Regulator block 12 is used for realizing voltage transformation, is+3.3V and+5V the+6V of outside voltage transformation, and as the operating voltage of phase-locked loop chip HMC833LP6GE, embodiment adopts commercially available special pressurizer HMC1060LP3E to make; Its effect of amplifier 14 is amplified local oscillation signal, and have buffer action, and to reduce the load balance factor of phase-locked chip HMC833LP6GE, embodiment adopts commercially available special pressurizer SBB-3089Z to make; Resistor R1, R2 capacitor C1, C2 and C3 form fast frequency-hopped loop filter, realize fast frequency-hopped for phase-locked loop chip HMC833LP6GE, and embodiment adopts commercially available 0603 general resistor and capacitor fabrication.
The concise and to the point operation principle of the utility model is as follows: adopt serial line interface to control, 1st input port of frequency multiplier 1 connects the external reference a reference source of input port A, by the effect of the first frequency hopping phase-locked loop circuit 3 and the second frequency hopping phase-locked loop circuit 4, output radiofrequency signal is made to obtain the frequency stability identical with reference data source; Local oscillation signal, by the effect of the first switching circuit 6, second switch circuit 7, the 3rd switching circuit 10 and the first filter circuit 8, second filter circuit 9, obtains fast frequency-hopped and Broadband emission.First switch on power, frequency multiplier 1 exports 5 times of the reference frequency clock signals as the first frequency hopping phase-locked loop circuit 3 and the second frequency hopping phase-locked loop circuit 4.FPGA5 circuit by input port B and PERCOM peripheral communication, and carries out data configuration to the first frequency hopping phase-locked loop circuit 3, second frequency hopping phase-locked loop circuit 4 first switching circuit 6, second switch circuit 7, the 3rd switching circuit 10, first filter circuit 8, second filter circuit 9.Local oscillation signal, by after switch filtering, inputs to output port C by amplifying circuit 11.
Mounting structure of the present utility model is as follows: it is in 4 layers of printed board of 95 millimeters × 105 millimeters that circuit components Double-face adhesive whole in Fig. 1 and Fig. 2 is contained in a block length × wide, printed board is arranged in shielding box body, then by the sealing of upper cover plate implementation structure.Input port A and output port C adopts two SMA-F cable blocks to connect, and input port B is connected by the double socket of 15 cores, assembly cost utility model.
Claims (4)
1. a broadband agility scheme synthesizer, comprises frequency multiplier (1), power splitter (2), FPGA (5), the first switch (6), second switch (7), the first filter (8), the second filter (9), the 3rd switch (10) and amplifier (11); It is characterized in that, also comprise the first frequency hopping phase-locked loop circuit (3) and the second frequency hopping phase-locked loop circuit (4); The first described frequency hopping phase-locked loop circuit (3) and the second frequency hopping phase-locked loop circuit (4) are integrated with phase-locked loop and VCO; Wherein the input port of frequency multiplier (1) is connected with outside, and the output port of frequency multiplier (1) is connected with the input port of power splitter (2); The output port of power splitter (2) is connected with the input port of the first frequency hopping phase-locked loop circuit (3) with the second frequency hopping phase-locked loop circuit (4) respectively; The output port of FPGA (5) is connected with the input port of the first frequency hopping phase-locked loop circuit (3) with the second frequency hopping phase-locked loop circuit (4) respectively; First frequency hopping phase-locked loop circuit (3) is all connected with the first switch (6) with the output port of the second frequency hopping phase-locked loop circuit (4); The output port of the first switch (6) is connected with the input port of second switch (7); The output port of second switch (7) is connected with the input port of the first filter (8) with the second filter (9) respectively; First filter (8) is all connected with switch (10) with the output port of the second filter (9); The output port of switch (10) is connected with the input port of amplifier (11); Amplifier (11) is connected with outside.
2. broadband according to claim 1 agility scheme synthesizer, is characterized in that: the first frequency hopping phase-locked loop circuit (3) and the second frequency hopping phase-locked loop circuit (4) are made up of regulator block (12), phase-locked chip (13), amplifier (14), control circuit (15), reference signal (16), resistor R1, R2 and capacitor C1, C2 and C3; The output port of regulator block (12) is connected with the input port of phase-locked chip (13); The output port of phase-locked chip (13) is connected with the input port of amplifier (14); The output port of reference signal (16) is connected with the input port of phase-locked chip (13); The output port of control circuit (15) is connected with the input port of regulator block (12) with phase-locked chip (13) respectively; Capacitor C1, C2 and C3 are in parallel, and one end is connected with phase-locked chip (13), other end ground connection; Resistor R1 is connected between C1 and C2, and resistor R2 is connected between C1 and C3.
3. broadband according to claim 1 agility scheme synthesizer, is characterized in that: the first frequency hopping phase-locked loop circuit (3) and the second frequency hopping phase-locked loop circuit (4) carry out pingpang handoff by the first switch (6); First filter (8) and the second filter (9) carry out region filtering by second switch (7) and the 3rd switch (10).
4. broadband according to claim 1 agility scheme synthesizer, it is characterized in that: the first frequency hopping phase-locked loop circuit (3) and the inner integrated VCO of the second frequency hopping phase-locked loop circuit (4) can carry out frequency preset fast, by the control signal of FPGA (5), the output of VCO accurately can be preset at a narrow bandwidth range rapidly.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521086298.9U CN205212817U (en) | 2015-12-24 | 2015-12-24 | Broadband frequency agility frequency synthesizer |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201521086298.9U CN205212817U (en) | 2015-12-24 | 2015-12-24 | Broadband frequency agility frequency synthesizer |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110995251A (en) * | 2019-12-04 | 2020-04-10 | 山东浪潮人工智能研究院有限公司 | Frequency hopping source for reducing frequency changing time and using method thereof |
| CN111130462A (en) * | 2020-01-20 | 2020-05-08 | 中国电子科技集团公司第五十四研究所 | Q/V frequency band ultra-wideband up-converter |
| CN115166382A (en) * | 2022-07-06 | 2022-10-11 | 成都中创锐科信息技术有限公司 | Multi-radiation source coherent signal simulation device and method |
-
2015
- 2015-12-24 CN CN201521086298.9U patent/CN205212817U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110995251A (en) * | 2019-12-04 | 2020-04-10 | 山东浪潮人工智能研究院有限公司 | Frequency hopping source for reducing frequency changing time and using method thereof |
| CN110995251B (en) * | 2019-12-04 | 2023-12-08 | 山东浪潮科学研究院有限公司 | Frequency hopping source capable of reducing frequency changing time and application method thereof |
| CN111130462A (en) * | 2020-01-20 | 2020-05-08 | 中国电子科技集团公司第五十四研究所 | Q/V frequency band ultra-wideband up-converter |
| CN111130462B (en) * | 2020-01-20 | 2022-12-09 | 中国电子科技集团公司第五十四研究所 | Q/V frequency band ultra-wideband up-converter |
| CN115166382A (en) * | 2022-07-06 | 2022-10-11 | 成都中创锐科信息技术有限公司 | Multi-radiation source coherent signal simulation device and method |
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| CF01 | Termination of patent right due to non-payment of annual fee |