JP2008172512A - Frequency synthesizer, phase lock loop, and clock generation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a frequency synthesizer capable of realizing frequency division of high precision while suppressing circuit increase, without using a PLL of a conventional configuration, and to provide a clock generation method. <P>SOLUTION: The frequency synthesizer comprises phase selection synthesizers 502 and 503 for generating a clock of a plurality of frequencies based on a N phase clock from a reference clock generator 501. At a clock selecting means 504 in the phase selection synthesizers 502 and 503, a clock of (N/M)f is generated by inputting the N phase clock and a phase number (j: integral number from 0 to (N-1)) and selecting a clock corresponding to the phase number. At a phase number generation means 505, the clock of (N/M)f, a division denominator M, and a division numerator N are inputted, and a value (M-N) synchronized with the clock of (N/M)f and computed from the division denominator M and the division numerator N is totaled. Then, a remainder from division of the totaled value ACC by N is adopted as the phase number (j). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a frequency synthesizer and a phase-locked loop that generate a clock having an arbitrary frequency, and a clock generation method.

  A conventional frequency synthesizer combines a frequency divider, phase comparator, filter (LPF, loop filter), and voltage controlled oscillator (VCO) to synchronize the phase of the divided clock of the voltage controlled oscillator and the divided clock of the reference clock. A desired frequency is generated by performing feedback control (phase lock loop: PLL) (see, for example, Patent Document 1, Patent Document 2, and Patent Document 3).

  However, in the conventional method, when it is desired to generate a plurality of frequencies at the same time, it is necessary to configure PLLs for the types of frequencies. For example, when it is desired to generate two types of frequencies, as shown in FIG. 28, a first reference clock generator 10001 includes a frequency divider 10002, 10006, a phase comparator 10003, LPF 10004, and a VCO 10005. It is necessary to generate a frequency individually by the PLL of the second PLL and the second PLL composed of the frequency dividers 10007 and 10011, the phase comparator 10008, the LPF 10009, and the VCO 10010. In particular, in the case of a PLL, since a capacitive component is required to realize the filter, the occupied area on the LSI is increased, leading to an increase in cost.

  On the other hand, there is a method of synthesizing a desired frequency without using a PLL (see, for example, Patent Document 4 and Patent Document 5). In this method, multi-phase clocks with different phases are input as reference clocks, and edges are extracted from clocks with different phases, or pulses corresponding to each clock phase are generated by edge extraction by a differentiator. Is synthesized by a synthesis circuit such as wired OR to synthesize a desired frequency.

  As another method not using the PLL, the selector selects a multi-phase clock, selects two clock phases in one cycle, and determines the rising edge and falling edge of a desired clock according to each clock phase. Some are synthesized (see, for example, Patent Document 6).

Japanese Patent No. 2827968 Japanese Patent No. 3319677 Japanese Patent No. 2817676 Japanese Patent Application No. 3-241417 Japanese Patent Application No. 5-119641 JP 2002-305440 A

  However, the conventional method of synthesizing a desired frequency without using the PLL described above requires a plurality of edge extraction circuits, differentiators, selectors, etc. for generating pulses for a period corresponding to the desired frequency. Become. For example, if the number of phases of the reference clock is P and the desired period is N times the reference clock, then P × N edge extraction circuits or differentiators are required. In the case of Patent Document 6, the same number of flip-flops and selectors as the number of clock phases are required. For this reason, in particular, when it is desired to realize the frequency dividing operation with high accuracy, P and N increase, so that the influence of the increase in the edge extraction circuit, or the circuit of the differentiator and selector increases.

  As described above, in the conventional frequency synthesizer, when a plurality of frequencies are generated at the same time, the number of PLLs, edge extraction circuits, differentiators, flip-flops, selectors, and the like corresponding to the desired frequencies are required. Increased size and cost.

  The present invention has been made in view of the above circumstances, and provides a frequency synthesizer and a clock generation method capable of realizing a high-precision frequency-dividing operation while suppressing an increase in circuit without using a phase-locked loop having a conventional configuration. The purpose is to provide.

  Further, the present invention aims to improve the characteristics of the clock generator and reduce the power consumption by applying a configuration that realizes a high-precision frequency division operation while suppressing an increase in circuit to a frequency divider for a phase-locked loop. It is an object of the present invention to provide a frequency synthesizer and a phase-locked loop that can be used, and a clock generation method.

The frequency synthesizer of the present invention is a frequency synthesizer that generates an N / M frequency-divided clock (N and M are integers) from an N-phase clock, and has a predetermined phase number from a frequency-dividing denominator M and a frequency-dividing numerator N. A phase number generating means for generating, and a clock selecting means for selecting a clock phase corresponding to the phase number output by the phase number generating means from the N phase clock and outputting the N / M divided clock. It is to be prepared.
With the above configuration, multiphase clocks having different phases as inputs are input as reference clocks, and the multiphase clock having the same rising edge timing as the rising edge timing in the divided clock waveform is appropriately selected and output. Realize circumferential operation. Since N / M frequency division can be realized at this time, by controlling the frequency division denominator M and the frequency division numerator N, for example, 5/6 * f ₀ , 5/7 * f _{0 and the} like are realized in addition to the frequency f _0. In addition, since the frequency such as 5/6 (83%) and 5/7 (71%) can be selected with respect to the reference frequency, the resolution of the generated output frequency is greatly improved. In addition, since it is possible to obtain a desired frequency without configuring a conventional PLL, a filter or the like is not necessary, and the area occupied when configured on an LSI is reduced, leading to cost reduction. Therefore, it is possible to realize a high-precision frequency dividing operation while suppressing an increase in circuit without using a phase lock loop having a conventional configuration.

Further, the present invention is the above-described frequency synthesizer, wherein the phase number generation means accumulates a value of (MN) for each cycle of the N / M frequency-divided clock, and the accumulated value is represented by N The remainder obtained by dividing by is used as the phase number.
The above configuration eliminates the need for edge extraction circuits or differentiators that only generate pulses for the period corresponding to the desired frequency, and the number of selectors is greatly reduced. Even when it is desired to do so, it is possible to avoid the influence of an increase in the number of circuits such as edge extraction circuits, differentiators and selectors.

The present invention is the above-described frequency synthesizer, wherein the clock selection unit includes a first clock selection circuit that selects a first clock and a second clock selection circuit that selects a second clock. The phase number generation means includes a first register that uses the first clock and a second register that uses the second clock, and the second clock selection circuit includes: It is controlled by the output of the first register, and the first clock selection circuit is controlled by the output of the second register to supply the N / M divided clock.
With the above configuration, the first or second clock selected by the first or second clock selection circuit and the second or first register used to control the first or second clock selection circuit are used. Alternatively, since the first clock is different, it is possible to avoid the occurrence of glitches in the N / M frequency-divided clock when the first and second registers are updated.

Also, the present invention is the above-described frequency synthesizer, in which the phase number generation means compares the values of the first register and the second register and controls the output of the N / M divided clock. It shall have means.
With the above configuration, the value of the first and second registers can be compared and the clock glitch can be invalidated, so that the occurrence of a glitch of the N / M divided clock can be avoided.

The frequency synthesizer of the present invention is a frequency synthesizer that generates an N / (M + X) frequency-divided clock (N and M are integers and X is a decimal number less than 1) from an N-phase clock, and a frequency-dividing denominator M and frequency-dividing A phase number generating means for generating a predetermined phase number from the numerator N and the decimal setting X; and a clock phase corresponding to the phase number output by the phase number generating means is selected from the N phase clock, and the N / And (M + X) clock selection means for outputting a divided clock.
With the above configuration, a fractional PLL with little jitter can be realized.

Further, the present invention is the above-described frequency synthesizer, wherein the phase number generation means includes a first accumulation circuit for accumulating the value of X every cycle of the N / M divided clock, and the N / M A second accumulation circuit for accumulating the value of (MN) every cycle of the M-divided clock, and the second accumulation of carry carried up to an integer in the first accumulation circuit. It is assumed that a remainder obtained by adding to the circuit and dividing the accumulated value of the second accumulation circuit by N is the phase number.
With the above configuration, a fractional PLL can be easily realized simply by adding an accumulation circuit to the phase number generation means, and quantization noise can be greatly reduced as compared with the conventional method.

The present invention is the above-described frequency synthesizer, wherein the clock selection unit includes a first clock selection circuit that selects a first clock and a second clock selection circuit that selects a second clock. The phase number generation means includes a first register that uses the first clock and a second register that uses the second clock, and the second clock selection circuit includes: It is controlled by the output of the first register, and the first clock selection circuit is controlled by the output of the second register and supplies the N / (M + X) divided clock.
With the above configuration, the first or second clock selected by the first or second clock selection circuit and the second or first register used to control the first or second clock selection circuit are used. Alternatively, since the first clock is different, it is possible to avoid the occurrence of a glitch of the N / (M + X) divided clock when the first and second registers are updated.

Further, the present invention is the above-described frequency synthesizer, wherein the phase number generation means compares the values of the first register and the second register and controls the output of the N / (M + X) divided clock. It is assumed that a comparison means is provided.
With the above configuration, the values of the first and second registers can be compared and the clock glitch can be invalidated, so that the occurrence of a glitch of the N / (M + X) divided clock can be avoided.

Further, the present invention provides any one of the above frequency synthesizers that divides an M / N divided clock by N / M, a phase comparator that compares the phase of a clock supplied from the frequency synthesizer, and a reference clock, There is provided a phase-locked loop including a voltage controlled oscillator that generates an M / N frequency-divided clock that is phase-synchronized with the reference clock in accordance with an output of a phase comparator.
With the above configuration, both the clock and the reference clock input to the phase comparator have a frequency N times that of the conventional configuration, and the operation band of the PLL can be made N times that of the conventional configuration.

Further, the present invention provides any one of the first frequency synthesizers for dividing the M / P divided clock by P / M, and any one of the second frequency synthesizers for dividing the M / P divided clock by P / N. A phase synthesizer, a phase comparator for phase comparison of a clock supplied from the first frequency synthesizer, and a reference clock; and an M / P component phase-synchronized with the reference clock according to the output of the phase comparator. A phase-locked oscillator that generates a divided clock, wherein the second frequency synthesizer divides the M / P divided clock by P / N to generate an M / N divided clock of the reference clock Provide a loop.
With the above configuration, the frequency of the input clock of the phase comparator is N times that of the conventional configuration, and the number of stages of the voltage control oscillator can be set to P. Therefore, the value of P can be arbitrarily set according to the upper limit of the oscillation frequency. Can do.

Further, the present invention provides any one of the first frequency synthesizers for dividing the QM / P divided clock by P / QM, and any one of the second frequency synthesizers for dividing the QM / P divided clock by P / Q. A frequency synthesizer, a clock supplied from the first frequency synthesizer, a phase comparator for phase comparison with a reference clock, and a QM / P component synchronized in phase with the reference clock according to the output of the phase comparator A voltage-controlled oscillator for generating a frequency clock, wherein the second frequency synthesizer provides a phase-locked loop for generating an M-multiplied clock of the reference clock by dividing the QM / P frequency-divided clock by P / Q To do.
With the above configuration, the oscillation frequency of the voltage controlled oscillator is f * QM / P, which can realize the combination of lowering the oscillation frequency, so that the restriction on the oscillation upper limit frequency of the voltage controlled oscillator can be relaxed, and the input The frequency range can be PQ times that of the conventional configuration.

In addition, the present invention includes any one of the frequency synthesizers described above and a random number generator that outputs a random value, and adds the fixed value and the random value to set the divided denominator M, the divided numerator N, or the decimal setting. Provide a phase-locked loop X.
With the above configuration, by adding, for example, α (t) as a time series random value output from random number generation to the frequency dividing denominator M and the frequency dividing numerator N, fractional control having fluctuations in the time series can be performed. As a result, a clock having fluctuations in time series such as f ₀ * (N + α (t)) / M or f ₀ * N / (M + α (t)) as a frequency can be realized. Since the clock having such fluctuation has a spread as a frequency component, the peak amplitude of the specific frequency component is suppressed, and an effect of reducing EMI is obtained.

Further, the present invention provides any one of the frequency synthesizers described above, wherein the first and second frequency synthesizers respectively generate first and second N / M frequency-divided clocks having a difference value having a constant phase angle. First and second frequency dividers that respectively divide the first and second N / M frequency-divided clocks to generate first and second N / 2M frequency-divided clocks; There is provided a phase locked loop including a logical operation unit that generates a N / M divided clock by performing a logical operation on a second N / 2M divided clock.
With the above configuration, it is possible to generate an N / M frequency-divided clock in which the duty ratio is ideally Hi section: Lo section = 50%: 50%.

Further, the present invention provides any one of the above frequency synthesizers, one or more ½ dividers that divide a clock supplied from the frequency synthesizer, and a clock output from the frequency synthesizer, or the 1 A phase-locked loop comprising: a selection circuit that selects a clock output from the / 2 frequency divider.
With the above configuration, for example, by configuring the 1/2 frequency divider in W stages, the frequency division ratio can be realized in a range from 1 / (2 ^ W) to 1, and the frequency range can be expanded.

Further, the present invention provides any one of the frequency synthesizers described above, wherein the first and second frequency synthesizers respectively generate first and second N / M frequency-divided clocks having a difference value having a constant phase angle. A set / reset holding means having the first N / M divided clock as a set input, the second N / M divided clock as a reset input, and a set or reset result as an N / M divided clock; A phase-locked loop comprising:
With the above configuration, it is possible to generate an N / M frequency-divided clock in which the duty ratio is ideally Hi section: Lo section = 50%: 50%.

Further, the present invention provides any one of the frequency synthesizers described above, wherein the first, second, and third N / M frequency-divided clocks each having a difference value having a constant phase angle are respectively generated. A third frequency synthesizer, a phase mixer for mixing the phases of the first and second N / M divided clocks to generate a fourth N / M divided clock, and the third and fourth First and second frequency dividers that divide an N / M divided clock to generate first and second N / 2M divided clocks, and the first and second N / 2M divided clocks And a logic unit that generates an N / M frequency-divided clock by performing a logic operation on the phase-locked loop.
With the above configuration, even when the frequency division denominator M is an odd number, the duty ratio of the N / M frequency division clock can be ideally set to Hi section: Lo section = 50%: 50%.

Further, the present invention provides any one of the frequency synthesizers described above, wherein the first, second, and third N / M frequency-divided clocks each having a difference value having a constant phase angle are respectively generated. A third frequency synthesizer, a phase mixer that mixes the phases of the first and second N / M divided clocks to generate a fourth N / M divided clock, and the third N / M There is provided a phase-locked loop comprising: a set-clock holding means that uses a divided clock as a set input, the fourth N / M divided clock as a reset input, and a set or reset result as an N / M divided clock. .
With the above configuration, even when the frequency division denominator M is an odd number, the duty ratio of the N / M frequency division clock can be ideally set to Hi section: Lo section = 50%: 50%.

The clock generation method of the present invention is a clock generation method for generating an N / M frequency-divided clock (N and M are integers) of a reference clock having an N-phase clock phase, and for each N / M frequency-divided clock. For each cycle, the value of (MN) is accumulated to at least N and the least common multiple of (MN), and the accumulation result is divided by N from the clock phase of the N phases of the reference clock. Selecting a clock phase corresponding to the remainder.
According to the above procedure, it is not necessary to configure a plurality of conventional PLLs for generating a plurality of clocks, and it is possible to realize a reduction in area and power consumption when the clock generation unit is mounted on an LSI or the like. .

Moreover, this invention provides the communication apparatus provided with one of the said frequency synthesizers.
The present invention also provides an information reproducing apparatus including any one of the above frequency synthesizers.
The present invention also provides an image display device including any one of the frequency synthesizers described above.
In addition, the present invention provides an electronic device including any one of the frequency synthesizers described above.
The present invention also provides an electronic control device including any one of the frequency synthesizers described above.
In addition, the present invention provides a mobile object including any one of the frequency synthesizers described above.
With the above configuration, since the frequency synthesizer can operate with less power consumption than in the past, the power consumption of various devices such as communication devices, information reproduction devices, image display devices, electronic devices, electronic control devices, and moving objects is reduced. It becomes possible.

  According to the present invention, it is possible to provide a frequency synthesizer and a clock generation method capable of realizing a high-precision frequency dividing operation while suppressing an increase in circuit without using a phase lock loop having a conventional configuration.

  Further, according to the present invention, by applying a configuration that realizes a high-precision frequency division operation while suppressing an increase in circuit to a frequency divider for a phase-locked loop, the characteristics of the clock generation unit can be improved and the power consumption can be reduced. A frequency synthesizer and a phase-locked loop that can be realized, and a clock generation method can be provided.

(First embodiment)
FIG. 1 is a block diagram showing a configuration of a clock generator according to an embodiment of the present invention. In FIG. 1, (a) shows the components of the clock generator including the frequency synthesizer of this embodiment, and (b) shows the components of the phase selective synthesizer corresponding to the frequency synthesizer. is there.

  The clock generation device includes a reference clock (reference clock) generator 501 that outputs an N-phase clock phase, and phase selection synthesizers 502 and 503 corresponding to frequency synthesizers that perform clock phase selection and frequency division clock generation described later. It is configured.

  An N-phase clock having a frequency f is input from the reference clock generator 501 to the phase selection synthesizers 502 and 503. The phase selection synthesizers 502 and 503 respectively perform N / M0 frequency division and N / M1 frequency division, and generate clocks of (N / M0) f and (N / M1) f, respectively.

  Each of the phase selection synthesizers 502 and 503 includes a clock selection unit 504 and a phase number generation unit 505. The clock selection means 504 inputs an N-phase clock and a phase number (an integer from j: 0 to (N−1)), and selects a clock corresponding to the phase number, so that (N / M) f Generate a clock.

  On the other hand, the phase number generation means 505 inputs the clock of (N / M) f, the frequency division denominator (M), and the frequency division numerator (N). Then, the phase number generation means 505 accumulates the value (MN) calculated from the frequency division denominator (M) and the frequency division numerator (N) in synchronization with the clock of (N / M) f.

  The operation of the clock generator according to this embodiment will be described below. FIG. 2 is a diagram illustrating the relationship between the reference clock and the divided clock in the present embodiment.

  In this embodiment, the reference clock has an N-phase clock phase having a uniform phase difference from φ [0] to φ [N−1], and the divided clock is divided by N / M as the reference clock. It is defined as a circle. For example, when the reference clock is an 8-phase clock and the divided clock is a 8/12 frequency divided from the reference clock, N = 8 and M = 12.

  Here, the reference clock can be generally generated by taking out a signal of each inverter output of an oscillation circuit constituted by an inverter ring. In an actual LSI, it is generally known that the phase difference and the frequency are not exactly the same due to variations in transistor characteristics, etc., and the term “uniform” described here is “frequency, This may mean that the phase difference is approximately the same.

  In FIG. 2, assuming that the period of the reference clock is T, the phase difference is a time obtained by dividing the period T by the number of phases N, that is, T / N. The period of the divided clock obtained by dividing the reference clock by N / M is (M / N) * T (in this specification, “*” represents multiplication). Here, when (M / N) * T is transformed into an equation, the following equation (1) is obtained.

  Here, focusing on the fact that the phase difference is T / N, the first term (T / N) * N and the second term (T / N) * (MN) on the rightmost side of equation (1). Are N times and (MN) times the phase difference, respectively. Furthermore, considering that the first term on the rightmost side of Equation (1) is equal to the period T, the frequency of the divided clock is equal to the time obtained by adding (MN) times the phase difference to the period of the reference clock. I understand. That is, in FIG. 2, the rising edges 101 and 102 of the φ [0] phase of the reference clock and the φ [MN] phase of the next cycle are temporally related to the rising edges 103 and 104 of the N / M divided clock. It can be said that they are equal.

  FIG. 3 is a diagram showing a relationship over a plurality of cycles of the reference clock and the divided clock in the present embodiment.

  As described above, in consideration of the fact that the period of the N / M divided clock is equal to the time obtained by adding (MN) times the phase difference to the period of the reference clock, the phase is delayed every cycle (MN). Thus, it can be seen that an N / M divided clock can be generated over a plurality of cycles.

  That is, in FIG. 3, when the rising edge of the reference clock φ [0] and the first cycle of the N / M frequency-divided clock is the same, the second cycle of the frequency-divided clock is set to φ [MN]. In the third cycle, the edge 202 is equal to φ [2 * (MN)], and in the (h + 1) cycle, the edge 203 is equal to φ [h * (MN)].

  Here, when the phases of the reference clock and the N / M frequency-divided clock match at the time (A) in FIG. 3 (the timings of the rising edges 204 and 205 match), the number of phases h * ( MN) is a common multiple of N and (MN). For this reason, the minimum number of phases delayed from the time when the phases of the reference clock and the N / M frequency-divided clock are the same until the next time when the phases are equal is the least common multiple (Least Common Multiple) of N and (MN). : LCM).

This means that when the least common multiple of X and Y is expressed as LCM {X, Y}, the delayed phase number h * (MN) is expressed by the following equation (2).
h * (MN) = LCM {(MN), N} (2)

  Since the delayed phase number h * (MN) is a multiple of (MN), it is greater than N in the case of simple calculation. However, in consideration of periodicity, φ [0] to φ [ N-1].

  FIG. 4 is a conceptual diagram showing the relationship between the number of phases and the periodicity in a polar coordinate format. The relationship between the number of phases and the periodicity will be described with reference to FIG.

  When the N-phase clocks are generated uniformly, the reference clock phases are φ [0], φ [1], φ [2],..., Φ [N−1] as shown in FIG. To each other at an equal angle. Then, φ [N] is equivalent to φ [0] as an angle, and thereafter φ [N + 1] and φ [N + 2] are the same angles as φ [1] and φ [2], respectively.

That is, the following expression (3) is established for the clock phase φ [i] (301) of the reference clock.
φ [i] = φ [a * N + i]: a is an arbitrary integer (3)

Here, i in equation (3) is also equal to the remainder obtained by dividing the value (a * N + i) by N. This means that when a remainder obtained by dividing X by Y is expressed as (X mod Y), the clock phase φ [x] is expressed by the following equation (4).
φ [x] = φ [x mod N]: x is an arbitrary integer (4)

  FIG. 5 is a conceptual diagram for explaining generation of an N / M frequency-divided clock in the present embodiment. Based on the above description, in this embodiment, as shown in FIG. 5, a reference clock having an N-phase clock phase is used, and a value for each cycle (MN) is set to at least N and (MN). Is accumulated to the least common multiple LCM {(MN), N}, and the remainder obtained by dividing the accumulation result by N is obtained. The remainder is 0 in the first cycle, (MN) mod N in the second cycle, 2 * (MN) mod N in the third cycle, LCM {(MN), in the (h + 1) cycle. N} mod N (= 0).

  Using these remainders as phases, φ [0], φ [(MN) mod N] (401), φ [2 * (MN) mod N] (402),..., Φ [LCM { (MN), N} mod N] (403) By selecting the clock phase corresponding to the remainder, the N / M divided clock of the reference clock is generated. That is, when an integer number starting from 0 is assigned to the clock phase of the reference clock, the N / M frequency-divided clock of the reference clock is generated by selecting the clock phase corresponding to the integer number that matches the remainder number. .

  For example, when generating a 3/5 frequency-divided clock with N = 3 and M = 5, three-phase clocks φ [0], φ [1], and φ [2] of the reference clock are generated. Next, for each cycle of the 3 / 5-divided clock, the value of (5-3) = 2 is accumulated to at least 3 and the least common multiple of (5-3) = 2, and the accumulated result is Find the remainder divided by 3. The accumulation result is “0, 2, 4, 6, 8, 10”, and the remainder is “0, 2, 1, 0, 2, 1”. Then, by selecting the clock phase “φ [0], φ [2], φ [1], φ [0], φ [2], φ [1]” that matches the remainder number, A 3/5 divided clock is generated.

  Returning to FIG. 1, the specific operation of the clock generator of this embodiment will be described. The reference clock generator 501 inputs an N-phase clock having a frequency f to the phase selection synthesizers 502 and 503. Then, the phase selection synthesizer 502 performs N / M0 frequency division to obtain a clock of (N / M0) f, and the phase selection synthesizer 503 performs N / M1 frequency division to obtain a clock of (N / M1) f. Generate each.

  In the phase selection synthesizers 502 and 503, the clock selection means 504 inputs the N-phase clock and the phase number (j: an integer from 0 to (N-1)) and selects the clock corresponding to the phase number. Thus, a clock of (N / M) f is generated. Further, the phase number generation means 505 inputs the clock of (N / M) f, the frequency dividing denominator (M), and the frequency dividing numerator (N). Then, the phase number generation means 505 accumulates the value (MN) calculated from the frequency division denominator (M) and the frequency division numerator (N) in synchronization with the clock of (N / M) f.

Here, the time series value (accumulated value) ACC by accumulation is expressed by the following formula (5), and the accumulated value ACC has a value in the range of 0 to at least LCM {(MN), N}. .
ACC = (MN) * t + j0 (5)

  In Expression (5), t is a time point (an integer starting from 0), and j0 is an initial phase number (an integer from 0 to (N−1)).

Next, a remainder obtained by dividing the accumulated value ACC by N is set as a phase number (j). Here, the time-series value of the phase number is expressed by the following equation (6).
j = {(MN) * t + j0} mod N (6)

  The phase number (j) obtained in this way is input to the clock selection unit 504, and the clock selection unit 504 selects the clock corresponding to the phase number (j), thereby generating the clock of (N / M) f. Generate.

  In this embodiment, the frequency dividing denominator (M) and the frequency dividing numerator (N) are limited to integers satisfying M ≧ 3, N ≧ 2, and M> N. This is due to the circuit mounting form of the phase selection synthesizer described later with reference to FIG. 8, and the above-described restrictions do not have to be satisfied as long as it is based on the contents of the invention shown in FIG.

  The initial phase number (j0) is an effective concept when a plurality of generated (N / M) f clocks have different phases. In the third embodiment to be described later, this initial phase number is used. An example of duty ratio improvement will be described.

  In general, when performing clock switching control, it is necessary to consider so as not to cause glitches associated with switching. Here, generation of a glitch associated with switching will be described with reference to FIGS. FIG. 6 is a diagram illustrating an example of a circuit mounting form of the clock selection unit 504a and the phase number generation unit 505a, and is a configuration example in which a mechanism for preventing glitches is not provided.

  The phase number generation unit 505a includes an adder 10101 and a register (Wb reg) 10102 having a bit width W, and the clock selection unit 504a includes a multiplexer 10103 that selects one clock from the N-phase clock. The Here, the number of clock phases is set to N = 2 ^ W (power of 2: W is an integer of 1 or more, and "^" represents power in this specification), the frequency division numerator is equal to N, and the frequency division denominator is Let it be M.

  The output of register 10102 corresponds to the phase number. The clock selected by the multiplexer 10103 becomes the clock clk as it is. The register 10102 operates with the clock clk. The adder 10101 adds k = (M−N) and the contents of the register 10102 and inputs the result to the register 10102 to accumulate k = (M−N) in synchronization with the clock clk. The output of the multiplexer 10103 is output as an output clock (Synthesized clock) of the frequency synthesizer.

  Here, since N is a power of 2 (2 ^ W) and the bit width of the register 10102 is W, the storage result of the register 10102 is equal to the remainder obtained by dividing the accumulated value ACC by N, The phase number may be used as it is.

  FIG. 7 is a diagram showing an operation example at the time of clock switching control in the configuration of FIG. Here, k = M−N is shown, and a timing chart in the control of switching from phase n to phase n + k is shown. Since the stored data (reg) of the register 10102 indicates the phase n, the content of the register 10102 is updated from n to n + k by the clock of the phase n (10201). Therefore, the clock clk is switched from the phase n to the phase n + k (10202).

  Next, since the register 10102 operates with the phase n + k, it is updated from n + k to n + k + k at the rising edge of the phase n + k (10203). Then, the clock clk is switched from the phase n + k to the phase n + k + k (10204).

  The clock clk obtained in this way is a switching in which a plurality of pulses are generated within the same cycle, that is, with a glitch. In this case, a normal clock is not generated as surrounded by a one-dot chain line. In order to realize clock generation according to the present embodiment, a device is also required for mounting clock switching.

  FIG. 8 is a diagram showing an example of a circuit mounting form of the clock selection unit 504 and the phase number generation unit 505 according to the present embodiment in consideration of the above-described problem of occurrence of glitches, and is provided with a mechanism for preventing glitches. .

  The phase number generation unit 505 includes an adder 601 and bit width W registers (Wb regs) 602, 603, and 604. The clock selection unit 504 is a comparison unit that selects one clock from the N-phase clock. Multiplexers 605 and 606, a coincidence determination unit 607, a logical product element (AND) 608, and logical inversion elements 609 and 610 are configured. Here, the number of clock phases is N = 2 ^ W (W is an integer of 1 or more), the frequency division numerator is equal to N, and the frequency division denominator is M.

  The outputs of the registers 602, 603, and 604 correspond to the phase numbers. Here, the phase numbers are A, B, and C, respectively. The clock selected by the multiplexer 605 becomes the clock clk0 via the AND element 608, and the clock selected by the multiplexer 606 becomes the clock clk1 as it is.

  The register 602 operates with the clock clk0, the register 603 operates with the inverted clock of the clock clk0, and the register 604 operates with the inverted clock of the clock clk1. The adder 601 adds k = (M−N) and the contents of the register 602 and inputs the result to the register 602 to accumulate k = (M−N) in synchronization with the clock clk0.

  Here, since N is a power of 2 (2 ^ W) and the bit width of the register 602 is W, the storage result of the register 602 is equal to the remainder obtained by dividing the accumulated value ACC by N, The phase number may be used as it is. Here, the phase number is A.

  Further, since the register 603 and the register 604 only copy the storage result of the register 602 in synchronization with the inverted clock of the clock clk0 and the inverted clock of the clock clk1, they may be similarly used as phase numbers. Here, phase number B and phase number C are set, respectively.

  The coincidence determination unit 607 determines whether or not the phase number B and the phase number C match, and outputs a logical value 1 if they match, and a logical value 0 if they do not match, as a match determination result (equal). To do. The logical product element 608 generates a logical product of the output of the multiplexer 605 and the coincidence determination result equal as the clock clk0. This clock clk0 is prevented from glitches associated with clock switching control and becomes an N / M divided clock. The output of the AND element 608 is output as an output clock (Synthesized clock) of the frequency synthesizer.

  The essential point in the configuration of this embodiment shown in FIG. 8 is that the clock clk selected by the multiplexer 10103 as shown in FIG. 6 and the clock clk used by the register 10102 that controls the multiplexer 10103 are the same. It is a point that avoids the configuration of doing.

  That is, in FIG. 8, the multiplexer 605 is controlled by the register 604 and the register 604 uses the clock clk 1 selected by the multiplexer 606. Similarly, multiplexer 606 is controlled by register 602 and register 602 uses clock clk 0 selected by multiplexer 605.

  In the case of the configuration as shown in FIG. 6, a glitch is generated in the clock clk by register update as shown in FIG. 7, but in the configuration of the present embodiment in FIG. 8, the clock selected by the multiplexer and the register that controls the multiplexer Therefore, it is possible to avoid the occurrence of clock glitches at the time of register update.

  Next, it will be described that the glitch associated with the clock switching control is prevented by the configuration of the present embodiment. FIG. 9 is a diagram illustrating an operation example at the time of clock switching control in the configuration of the clock selection unit and the phase number generation unit of the present embodiment. Here, k = M−N, and as an operation condition in the control to switch from phase n to phase n + k, the minimum value (min k) of k having the closest rising edge to phase n shown in (a), and ( The timing chart in the case of each of the phase n shown in b) and the maximum value (max k) of k with the farthest rising edge is shown.

  First, the operation in the case of the minimum value (min k) of k that is closest to the phase n and the rising edge will be described. Data stored in the registers 602, 603, and 604 all indicate the phase n. Since the data stored in the register 604 indicates the phase n, the contents of the register 602 are updated from n to n + k by the clock of the phase n (701).

  Since the multiplexer 606 is controlled by the contents of the register 602, the clock clk1 output from the multiplexer 606 switches from phase n to phase n + k (702). As described above, since the register 602 operates with the clock selected by the multiplexer 605, the clock is not changed in the operation of 702, and therefore, it is not updated again (703).

  Also, the register 603 is operated by a clock obtained by logically inverting the clock for operating the register 602, and therefore is not updated by the operation of 702, like the register 602.

  On the other hand, since the register 604 operates with the inverted clock of clk1, which is the clock selected by the multiplexer 606, a glitch associated with clock switching occurs as shown by the alternate long and short dash line. However, in the portion 704 surrounded by the broken line, the register 603 which is the input data of the register 604 has not been updated as already described, so that the same value (phase n) is re-acquired, which is substantially a problem. Does not occur.

  Next, since the register 603 operates with a clock obtained by logically inverting the clock on which the register 602 operates, the content of the register 603 is updated from n to n + k by the falling edge of the phase n clock (705).

  Here, since the contents of the register 603 and the register 604 are input to the coincidence determination unit 607, the contents of the register 603 and the register 604 do not coincide with each other by the operation 705, and therefore the coincidence determination result “equal” becomes the Lo level (706). .

  The coincidence determination result “equal” is input to the AND element 608 together with the output of the multiplexer 605. The multiplexer 605 has selected the phase n by the register 604, and its output is at the Lo level (707). For this reason, the operation of 706 has no effect on the clock clk0.

  Next, since the register 604 operates with a clock obtained by logically inverting clk1 that has already been switched to the phase n + k, the content of the register 604 is updated from n to n + k with a phase difference k delayed from the operation 705 (708). The operation of 708 switches the selection of the multiplexer 605 from phase n to n + k (709).

  Further, since the contents of the register 603 and the register 604 coincide with each other by the operation 708, the coincidence determination result “equal” becomes the Hi level (710). However, the phase n + k selected by the multiplexer 605 is already at the Lo level (711). For this reason, the operation 710 has no effect on the clock clk0. Through the above operation, the registers 602, 603, and 604 again show the same value (n + k), and the switching from the phase n + k to n + k + k is repeated similarly (712).

  Next, the operation in the case of the maximum value (max k) of k that is farthest from the phase n and the rising edge will be described. Data stored in the registers 602, 603, and 604 all indicate the phase n. Since the data stored in the register 604 indicates the phase n, the contents of the register 602 are updated from n to n + k by the clock of the phase n (721).

  Since the multiplexer 606 is controlled by the contents of the register 602, the clock clk1 output from the multiplexer 606 switches from phase n to phase n + k (722). As described above, since the register 602 operates with the clock selected by the multiplexer 605, the clock does not change in the operation of 722, and therefore is not updated again (723).

  Also, the register 603 is operated by a clock obtained by logically inverting the clock for operating the register 602, and therefore, the register 603 is not updated by the operation of 722 like the register 602.

  Next, since the register 603 operates with a clock obtained by logically inverting the clock on which the register 602 operates, the content of the register 603 is updated from n to n + k by the falling edge of the phase n clock (725).

  Here, since the contents of the register 603 and the register 604 are input to the coincidence determination unit 607, the contents of the register 603 and the register 604 do not coincide with each other by the operation of 725, so the coincidence determination result equal becomes Lo level (726). .

  The coincidence determination result “equal” is input to the AND element 608 together with the output of the multiplexer 605. The multiplexer 605 has selected the phase n by the register 604, and its output is at the Lo level (707). Therefore, the operation of 726 does not affect the clock clk0 at all.

  Next, since the register 604 operates with a clock obtained by logically inverting clk1 that has already been switched to the phase n + k, the content of the register 604 is updated from n to n + k with a phase difference k delayed from the operation of 725 (728). The operation of 728 switches the selection of multiplexer 605 from phase n to n + k (729).

  Here, there is a rising edge of phase n as indicated by the alternate long and short dash line until the operation of 729 is performed. However, since the coincidence determination result “equal” is at the Lo level (727) and is invalidated by the AND element 608, no glitch is generated in the clock clk0 in the portion 724 surrounded by the broken line.

  Further, since the contents of the register 603 and the register 604 coincide with each other by the operation of 728, the coincidence determination result “equal” becomes the Hi level (730). However, since the phase n + k selected by the multiplexer 605 is already at the Lo level (731), the operation of 730 has no effect on the clock clk0. Through the above operation, the registers 602, 603, and 604 again show the same value (n + k), and the switching from the phase n + k to n + k + k is repeated similarly (732).

  As described above, generation of clock glitches at the time of register update can be avoided by avoiding the same clock selected by the multiplexer and the clock used by the register controlling the multiplexer. Furthermore, it is desirable to combine a mechanism for invalidating a clock glitch under a specific condition, such as the operation of 724 described above.

  In this embodiment, in order to realize the operation 724, the coincidence determination unit and the logical product element are used as the constituent elements. However, the present invention is not limited to this configuration, and the above operation 724 can be realized. A circuit configuration for generating the invalidation signal or a circuit configuration that substitutes for the operation of 724 may be used.

  FIG. 10 is a diagram illustrating an example of an output clock of the frequency synthesizer in the present embodiment. A predetermined output clock can be obtained by selecting a clock according to the configuration and operation of the present embodiment described above. In the example of FIG. 10, the case of frequency division by 2/3, that is, the case of M = 3 and N = 2 in FIG. In this case, a clock 801 having a phase number j = 0 and a clock 802 having a phase number j = 1 are input to the clock selection unit 504 as multiphase clocks.

  The phase number generation means 505 performs accumulation by k = M−N (= 1), and the accumulated value ACC increases as 0, 1, 2, 3,. The accumulated value ACC may be accumulated at least up to 2, which is the least common multiple of N (= 2) and MN (= 1).

  Then, with the remainder obtained by dividing the accumulated value ACC by N (= 2) as the phase number, the phase number j changes to 0, 1, 0, 1,. Further, the 2/3 frequency-divided clock 803 obtained by the device for preventing glitches shown in FIG. 8 is obtained by selecting (804, 805) the respective clock pulses of the clock 801 and the clock 802 and outputting them.

  FIG. 11 is an explanatory diagram comparing the conventional configuration and the configuration of the present embodiment. In FIG. 11, (a) shows a conventional configuration, and (b) shows the configuration of the present embodiment. In the conventional configuration as shown in FIG. 11A or FIG. 28 shown in the background art, it is necessary to configure a plurality of PLLs for generating a plurality of clocks. On the other hand, in the configuration of the present embodiment as shown in FIG. 11B, a plurality of reference clock generators (PLL) 1001 that output N-phase clock phases and phase selection synthesizers 1002 are provided. Even in the case of generating this clock, it is not necessary to configure a plurality of PLLs, and the number of PLLs can be reduced. As a result, the circuit mounting area can be reduced, and power consumption can be reduced.

(Second Embodiment)
As a second embodiment, some examples of application to a phase-locked loop using the characteristic configuration of the clock generation device according to the present invention are shown. The features of clock generation according to the present invention include the following.

(1) By changing the frequency division denominator and numerator values, other frequencies can be generated from one clock frequency.
(2) A value larger than 1 can be taken as the numerator of the division ratio.

  First, as an example using the features listed in (1) above, dynamic frequency control (DFS) is considered as a first application example.

FIG. 12 is a diagram illustrating a first application example applied to dynamic frequency control. In FIG. 12, (a) shows a conventional configuration, and (b) shows a first application example according to the present invention. In the conventional configuration shown in FIG. 12A, for example, the selection circuit 1004 switches between a clock with a frequency f ₀ obtained from a PLL and a clock with a frequency (1/2) f ₀ obtained after a 1/2 frequency divider. It was that. In this case, the resolution is such that the frequency that can be dynamically controlled is half. That is, with the conventional configuration, only a frequency that is 1/2 of the reference frequency and a frequency of 1 / (power of 2) can be generated with a general frequency divider (that is, not 90% of the reference frequency).

On the other hand, the first application example shown in FIG. 12B includes a reference clock generator (PLL) 1001 that outputs an N-phase clock and a phase selection synthesizer 1002, and realizes DFS. Yes. In this configuration, as shown in FIGS. 1 and 8, N / M frequency division can be realized. Therefore, for example, (5/6) f ₀ , (5/7) f ₀ other than the frequency f ₀ by the fraction control value 1003. Can be realized, and the resolution of frequency switching is greatly improved. That is, a frequency such as 5/6 (83%) or 5/7 (71%) can be selected with respect to the reference frequency, and the resolution of the frequency can be increased.

  Further, as an example using the feature listed in (1) above, generation of a spread spectrum clock is considered as a second application example.

  FIG. 13 is a diagram for explaining a second application example applied to spread spectrum clock generation. In the second application example, in addition to the configuration of the first application example shown in FIG. 12B, a random number generator 1501 and an adder 1502 are provided, and the fraction control value similar to the fraction control in the first application example is provided. The time series random value α (t) output from the random number generator 1501 is added to 1503 (N or M). As a result, a fractional control value 1504 having fluctuations in time series can be generated.

According to this configuration, for example, a clock having fluctuations in time series such as f ₀ * (N + α (t)) / M or f ₀ * N / (M + α (t)) can be realized. Since the clock having such fluctuation has a spread as a frequency component, the peak amplitude of the specific frequency component is suppressed, and an effect of reducing EMI is obtained.

  Next, as an example using the characteristics listed in (2) above, improvement of the characteristics of the PLL can be considered as a third application example and a fourth application example.

  FIG. 14 is a diagram illustrating a third application example and a fourth application example applied to improving the characteristics of the PLL. 14A shows a conventional configuration, FIG. 14B shows a third application example according to the present invention, and FIG. 14C shows a fourth application example according to the present invention.

  In general, in a PLL, as in the conventional configuration shown in FIG. 14A, a clock having a frequency f is divided by 1 / N to generate an f / N clock 1101, and an output clock 1103 of the VCO 1102 is set to 1. The frequency of the 1 / M frequency division clock 1105 converges to f / N by feeding the phase comparison result to the VCO 1102 and feeding it to the phase comparator (PFD) 1104. At this time, the output clock 1103 of the VCO 1102 is (M / N) f.

  Here, since the phase comparator (PFD) 1104 operates at each edge of the input clock, the phase comparator (PFD) 1104 operates at a frequency of f / N in the configuration of FIG.

  On the other hand, in the third applied example as an example shown in FIG. 14B, the phase selective synthesizer of this embodiment is applied to the frequency divider 1110 together with the phase comparator 1111 and is configured by an N-stage inverter ring. The VCO 1112 is configured to input an N-phase clock to the frequency divider 1110. In the case of this configuration, N / M frequency division is realized by the frequency divider 1110. Therefore, both the input clocks of the phase comparator 1111 have the frequency f, which is N times the clock in the conventional configuration of FIG. Thus, the phase comparator 1111 operates. This means that the operating band of the PLL has increased N times, and a wider band can be achieved.

  Although it is generally known that an N-phase clock can be generated by an N-stage VCO, the number of stages of the VCO is also a determining factor for the upper limit of the oscillatable frequency. In the fourth application example as another example shown in FIG. 14C, a P / M frequency divider 1120 and a P / N frequency are used instead of the N / M frequency divider of the third application example shown in FIG. A combination of the frequency divider 1121 is provided, and a PLL is configured using a VCO 1123 configured by a P-stage inverter ring. In the case of this configuration, the input clock of the phase comparator 1122 remains at the frequency f, and the number of stages of the VCO 1123 can be set to P stages. Therefore, the value of P can be arbitrarily set according to the upper limit of the oscillation frequency.

  Another application example to the PLL is shown as a fifth application example. FIG. 15 is a diagram for explaining a fifth application example which is another application example to the PLL. 15A shows a first conventional configuration, FIG. 15B shows a second conventional configuration, and FIG. 15C shows a fifth application example according to the present invention.

  When the frequency f * M is generated from the frequency f, a 1 / M frequency divider 1201 is provided on one side as in the conventional first configuration shown in FIG. 15A, and the phase comparator (PFD) 1202 There is a configuration in which the input clock has a frequency f. Here, similarly to FIG. 14 described above, the phase comparator 1202 is assumed to operate at the frequency f. At this time, the oscillation frequency of the VCO 1203 is f * M, that is, Mf. Here, when the frequency f is lowered, the oscillation frequency of the VCO 1203 is lowered. Therefore, the input frequency range is determined by the restriction of the oscillation lower limit frequency of the VCO.

  As a conventional configuration for improving the input frequency range, a 1 / QM instead of the 1 / M frequency divider 1201 in FIG. 15A is used as in the conventional second configuration shown in FIG. By providing the frequency divider 1210 and the 1 / Q frequency divider 1211, the oscillation frequency of the VCO 1212 can be set to f * QM, that is, QMf, thereby increasing the input frequency range by Q times.

  However, when considering the upper limit of the oscillation frequency, the conventional second configuration of FIG. 15B only increases the oscillation frequency, and therefore the input frequency range is determined by the limitation of the oscillation upper limit frequency.

  On the other hand, the fifth application example shown in FIG. 15C includes a P / QM frequency divider 1220 and a P / Q frequency divider 1221, and a P-stage VCO 1222. In this configuration, the oscillation frequency of the VCO 1222 is f * QM / P, that is, (QM / P) f. As a result, since the combination on the side of lowering the oscillation frequency can be realized, the restriction on the oscillation upper limit frequency of the VCO can be relaxed. In this case, the input frequency range is PQ times that of the conventional first configuration of FIG. 15A, so that the input frequency range can be expanded.

  Furthermore, the clock generator according to the present invention can be applied to improve the accuracy of a so-called fractional PLL using a decimal number as a frequency division ratio. FIG. 16 is a diagram for explaining a sixth application example applied to the improvement of the accuracy of the fractional PLL. 16A shows a conventional configuration, and FIG. 16B shows a sixth application example according to the present invention.

  As a conventional fractional PLL, as in the conventional configuration shown in FIG. 16A, a 1 / M frequency divider 1301 is provided on one side together with a VCO 1303, and an input clock of a phase comparator (PFD) 1302 is set to a frequency f. There is a configuration to make. Then, the M value of the 1 / M frequency divider 1301 is controlled to 1 / M or 1 / (M + 1) so as to periodically correct the frequency division ratio error corresponding to the decimal point less than M (1304). By this M value control 1304, the clock output from the VCO 1303 converges to a frequency division ratio of 1 / (M + decimal).

  Here, in the conventional configuration of FIG. 16A, when controlling the M value of the 1 / M frequency divider 1301, considering the case of M = 10, the difference between 1 / M and 1 / (M + 1) is The difference is 1/10 and 1/11. This difference is generally called quantization noise, and affects the jitter performance.

  On the other hand, the sixth application example shown in FIG. 16B is configured to include a phase comparator 1312, a P / PM frequency divider 1311, and a P-stage VCO 1313. In this way, the P / PM divider 1311 is provided on one side, the input clock of the phase comparator 1312 is set to the frequency f, and the error of the division ratio corresponding to the decimal point less than M is periodically corrected. The PM value of the P / PM frequency divider 1311 is controlled to P / PM or P / (PM + 1) (1314). By this PM value control 1314, the clock output from the VCO 1313 converges to a frequency division ratio of P / (P (M + decimal)) = 1 / (M + decimal) as in the conventional configuration of FIG. To do.

  Assuming that M = 10 and P = 5 in the configuration of the sixth application example, the difference between P / PM and P / (PM + 1) is 1/10 and 5/51 (= 1 / 10.2). That is, in the sixth application example according to the present invention, the quantization noise is reduced from 1/11 to 1 / 10.2 in the conventional configuration, and the phase quantization noise can be reduced to 1/5. In this way, a fractional PLL with less jitter can be realized.

  A configuration example of a phase selection synthesizer for realizing the above-described fractional PLL is shown in FIGS. FIG. 17 is a diagram showing components of a phase selection synthesizer that implements a fractional PLL, and FIG. 18 is a diagram showing an example of a circuit implementation form of the clock selection means 504 and phase number generation means 1401 in the phase selection synthesizer of FIG. is there.

  17 and 18 is a modification of the phase number generation means 505 in the phase selection synthesizer described in FIG. That is, the fractional PLL can be realized by inputting the decimal point error to the carry input (carry-in: ci) of the adder 601 in the phase number generation means 505 of FIG.

  Specifically, as shown in FIG. 17, a value “x” is set as the decimal number setting in the phase number generation unit 1401. Then, as shown in FIG. 18, this decimal set value x is accumulated by an accumulator circuit composed of an adder 1402 and a register 1403, and an overflow from the decimal point (carry out: co) 1404 is input to the adder 601 as a carry input. To enter. Other operations are the same as those in FIG. In this case, every time an overflow occurs, the accumulated value of the adder 601 changes from k to k + 1, and as a result, the division ratio is controlled to be P / PM or P / (PM + 1).

  As described above, according to the sixth application example, the fractional PLL can be easily realized only by adding the accumulating means in the phase number generating means 1401, and the quantization noise is greatly reduced as compared with the conventional method. it can.

(Third embodiment)
As a third embodiment, several application examples to a phase-locked loop for further enhancing the effect of the clock generation device according to the present invention will be shown.

  FIG. 19 is a diagram illustrating a seventh application example for expanding the frequency dividing range. 19A shows the basic configuration of the present embodiment, and FIG. 19B shows the seventh application example according to the present invention. In the case of the phase selective synthesizer 1002 having the basic configuration shown in FIG. 19A, a frequency division ratio in the range of 1/2 to 1 can be realized.

  On the other hand, in the seventh application example shown in FIG. 19B, in addition to the basic configuration of FIG. 19A, a configuration including a W-stage 1/2 frequency divider 1601 and a selection circuit 1604 is provided. It has become. In this improved configuration, when it is desired to realize a division ratio exceeding the above range such as 1/3, the fractional control value is separated into two, the first fractional control value 1602 and the second fractional control value 1603, and selected. The circuit 1604 selects either the clock of the phase selection synthesizer 1002 or the 1/2 frequency divider 1601.

  For example, when the division ratio is desired to be realized in the range of 1/3 to 1, since 1/3 = 2/3 * 1/2 is established, the first fraction control value 1602 is set in the range of 2/3 to 1. To do. As a result, the output of the phase selection synthesizer 1002 has a frequency division ratio in the range of 2/3 to 1, and the output of the 1/2 frequency divider 1601 has a frequency division ratio in the range of 1/3 to 1/2. Become.

  Here, by selecting the output of the phase selection synthesizer 1002 or the output of the 1/2 divider 1601 by the selection circuit 1604, the final clock division range is from 1/3, which is the sum of both outputs. 1 range. When such a configuration is generalized, by dividing the 1/2 divider into W stages, the division ratio can be realized in the range of 1 / (2 ^ W) to 1, and the division range can be further expanded. I can plan.

  Further, as an application example for further enhancing the effect of the present invention, there is an improvement in duty ratio. Since the phase selection synthesizer according to this embodiment is configured to select a clock from multiphase clocks by accumulation using the adder 601 as shown in FIG. 8, the initial value of accumulation is changed. It is possible to change the phase angle of the clock.

  An eighth application example according to the present invention will be described with reference to FIGS. FIG. 20 is a diagram showing a configuration of an eighth application example as an example for improving the duty ratio. The clock generation apparatus of the eighth application example includes 1/2 frequency dividers 1701 and 1702 and an exclusive OR negating element (XNOR) after the reference clock generator 501 and the phase selection synthesizers 502 and 503 shown in FIG. 1703 is provided.

  The change of the phase angle of the clock corresponds to the initial phase number (j0) described in the above equation (5). Therefore, as shown in FIG. 20, the clock of the reference clock generator 501 is input to the phase selection synthesizers 502 and 503, and the phase angle of the output of each phase selection synthesizer is set to 0 [deg] and 180 [deg]. In addition, after 1/2 frequency division by 1/2 frequency dividers 1701 and 1702, a logical operation of exclusive OR negating element (XNOR) 1703 is performed.

  FIG. 21 is a diagram showing clock timings in the eighth application example of FIG. Here, the phase angle of 180 [deg] corresponds to the time of (M / 2N) * T in the case of the period (M / N) * T. Therefore, for the initial phase number (j0) in equation (5), if j0 of the clock with a phase angle of 0 [deg] is j0 = 0, j0 of the clock with a phase angle of 180 [deg] is j0 = M / 2. Then, each phase angle can be obtained.

  By these operations, the output clocks of the phase selection synthesizer 502 and the phase selection synthesizer 503 are shifted in phase by 180 [deg] at a frequency of f * N / M, as indicated by clocks 1704 and 1706 in FIG. Generated in the form. Further, as shown by clocks 1705 and 1707, the output clocks of the 1/2 frequency dividers 1701 and 1702 are generated at the frequency of f * N / 2M and the phase is similarly shifted by 90 [deg].

  At this time, since the clocks 1705 and 1707 change at each rising edge of the clocks 1704 and 1706, the duty ratio is ideally Hi interval: Lo interval = 50%: 50%. Since the clocks 1705 and 1707 transition to Lo / Lo, Hi / Lo, Hi / Hi, and Lo / Hi every phase 90 [deg], logical operation of the exclusive OR negating element (XNOR) 1703 is performed. , F * N / M, and a duty ratio ideally becomes Hi section: Lo section = 50%: 50%.

  A ninth application example according to the present invention will be described with reference to FIGS. FIG. 22 is a diagram showing a configuration of a ninth application example as another example for improving the duty ratio, and FIG. 23 is a diagram showing clock timings in the ninth application example.

  In the ninth application example, a 1/2 frequency divider is not used as in the eighth application example of FIG. 20, but a set / reset latch 1901 as a set / reset holding means is used as shown in FIG. . In this configuration, clocks having phases different from each other by 180 [deg] output from the phase selection synthesizers 502 and 503 are input to the set / reset latch 1901 as the set signal 1902 or the reset signal 1903, respectively.

  As shown in FIG. 23, the output of the set / reset latch 1901 first transitions from Lo to Hi by a set signal 1902 using a clock whose phase angle is 0 [deg] (1904), and then the phase angle is 180 [ The transition is from Hi to Lo by the reset signal 1903 using the clock of [deg] (1905).

  By these operations, as the output of the set / reset latch 1901, a clock 1708 having a duty ratio of ideally Hi section: Lo section = 50%: 50% at a frequency of f * N / M is obtained.

  In the eighth application example and the ninth application example, since the value M / 2 is used as the initial phase number j0, an error occurs when M is an odd number. Therefore, even if M is an odd number, a configuration example in which the duty ratio can be ideally set to Hi section: Lo section = 50%: 50% will be described as a tenth application example.

  FIG. 24 is a diagram showing a configuration of a tenth application example as still another example for improving the duty ratio. The clock generation apparatus of the tenth application example is a modification of the ninth application example of FIG. 22, and includes a reference clock generator 501 and three phase selection synthesizers 502, 2006, 2007, and a phase selection synthesizer 2006. , 2007 is provided with a phase mixer 2003, and a set / reset latch 1901 is provided at the output of the phase selection synthesizer 502 and the phase mixer 2003.

  In the tenth application example, in order to generate a clock having a phase angle of 180 [deg], a phase selection synthesizer 2006 that generates a clock 2001 having a phase angle of 180−Δ [deg], and a phase angle of 180 + Δ [deg]. The phase selection synthesizer 2007 for generating the clock 2002 and the phase mixer 2003 for inputting and mixing the respective clocks are used.

  Here, the clocks 2001 and 2002 correspond to the phase angles obtained by applying the rounded down and rounded values of M / 2 to j0 when M is an odd number. For example, when M = 5, since 5/2 = 2.5, the clock 2001 has a phase angle of j0 = 2, and the clock 2002 has a phase angle of j0 = 3.

  FIG. 25 is a diagram showing the configuration of the phase mixer 2003 in the tenth application example. The phase mixer 2003 includes inverters 2008 and 2009 that input respective clocks, an intermediate node 2004 that short-circuits the outputs of the inverters 2008 and 2009, and an inverter 2010 that inputs the intermediate node 2004.

  FIG. 26 is a diagram showing clock timings by the phase mixer 2003 of FIG. In the phase mixer 2003 having the configuration shown in FIG. 25, the waveform of the intermediate node 2004 changes from the Hi level to the Lo level in the period Δ (2011, 2012) in which the outputs of the inverters 2008 and 2009 are different over 2Δ. It becomes a dull state (2013). At this time, the switching level 2005 generally has a half value of the power supply voltage in the case of CMOS, so that the output of the inverter 2010 has an intermediate phase between the clocks 2001 and 2002, that is, a phase angle of 180 [deg] ( 2014).

  Thus, according to the tenth application example, even when M is an odd number, the duty ratio can be ideally set to Hi section: Lo section = 50%: 50%. 24, the description has been given based on the configuration of the ninth application example of FIG. 22. However, the configuration of the eighth application example of FIG. 20 can be similarly applied by providing the phase mixer 2003. Is possible.

(Fourth embodiment)
As a fourth embodiment, several configuration examples of an apparatus to which a clock generation apparatus including a frequency synthesizer according to the present invention is applied are shown. FIG. 27 is a diagram illustrating the configuration of various apparatuses to which the frequency synthesizer according to this embodiment is applied.

  FIG. 27A is a diagram illustrating an overview of a communication device including the frequency synthesizer according to the present invention. A cellular phone 1800 as a communication device includes a baseband LSI 1801 and an application LSI 1802. The baseband LSI 1801 and the application LSI 1802 are semiconductor integrated circuits having the above-described frequency synthesizer of the present embodiment.

  Since the frequency synthesizer according to the present invention can operate with less power consumption than before, the baseband LSI 1801 and the application LSI 1802 and the mobile phone 1800 including these can also operate at low power. Further, for the semiconductor integrated circuit provided in the mobile phone 1800 other than the baseband LSI 1801 and the application LSI 1802, the logic circuit provided in the semiconductor integrated circuit is the frequency synthesizer according to the present invention, so that the same as described above. The effect of can be obtained.

  Note that the communication device including the frequency synthesizer according to the present invention is not limited to a mobile phone, and includes, for example, a transmitter / receiver in a communication system, a modem device that performs data transmission, and the like. It is a waste. That is, according to the present invention, it is possible to obtain the effect of reducing power consumption for any communication device regardless of whether it is wired / wireless, optical communication / electrical communication, or digital method / analog method.

  FIG. 27B is a diagram showing an overview of an information reproducing apparatus provided with the frequency synthesizer according to the present invention. An optical disk apparatus 1810 as an information reproducing apparatus includes a media signal processing LSI 1811 that processes a signal read from an optical disk, and an error correction / servo processing LSI 1812 that performs error correction of the signal and servo control of an optical pickup. The media signal processing LSI 1811 and the error correction / servo processing LSI 1812 are semiconductor integrated circuits having the above-described frequency synthesizer of this embodiment.

  Since the frequency synthesizer according to the present invention can operate with less power consumption than before, the media signal processing LSI 1811, the error correction / servo processing LSI 1812, and the optical disk apparatus 1810 including these can also operate at low power. . Further, for the semiconductor integrated circuit provided in the optical disc apparatus 1810 other than the media signal processing LSI 1811 and the error correction / servo processing LSI 1812, the logic circuit provided in the semiconductor integrated circuit is used as the frequency synthesizer according to the present invention. Thus, the same effect as described above can be obtained.

  Note that the information reproducing apparatus provided with the frequency synthesizer according to the present invention is not limited to the optical disk apparatus, and besides this, for example, an information recording / reproducing apparatus incorporating a magnetic disk or information using a semiconductor memory as a medium. It includes a recording / reproducing device. That is, according to the present invention, the effect of reducing power consumption can be obtained for any information reproducing apparatus (which may include an information recording function) regardless of the type of media on which information is recorded.

  FIG. 27 (c) is a diagram showing an overview of an image display device including the frequency synthesizer according to the present invention. A television receiver 1820 as an image display device includes an image / audio processing LSI 1821 that processes image signals and audio signals, and a display / sound source control LSI 1822 that controls devices such as a display screen and speakers. The image / sound processing LSI 1821 and the display / sound source control LSI 1822 are semiconductor integrated circuits having the above-described frequency synthesizer of the present embodiment.

  Since the frequency synthesizer according to the present invention can operate with less power consumption than before, the image / audio processing LSI 1821, the display / sound source control LSI 1822, and the television receiver 1820 including these can also operate at low power. It becomes. Further, for the semiconductor integrated circuit provided in the television receiver 1820 other than the image / sound processing LSI 1821 and the display / sound source control LSI 1822, the logic circuit provided in the semiconductor integrated circuit is the same as the frequency synthesizer according to the present invention. By doing so, the same effect as described above can be obtained.

  Note that the image display device provided with the frequency synthesizer according to the present invention is not limited to a television receiver, but also includes, for example, a device for displaying streaming data distributed through a telecommunication line. Is included. That is, according to the present invention, the effect of reducing power consumption can be obtained for any image display apparatus regardless of the information transmission method.

  FIG. 27 (d) is a diagram showing an overview of an electronic device including the frequency synthesizer according to the present invention. A digital camera 1830 as an electronic device includes a signal processing LSI 1831. This signal processing LSI 1831 is a semiconductor integrated circuit having the above-described frequency synthesizer of the present embodiment.

  Since the frequency synthesizer according to the present invention can be operated with less power consumption than before, the signal processing LSI 1831 and the digital camera 1830 including the signal processing LSI 1831 can also operate at low power. Further, for the semiconductor integrated circuit provided in the digital camera 1830 other than the signal processing LSI 1831, the same effect as described above can be obtained by using the logic circuit provided in the semiconductor integrated circuit as the frequency synthesizer according to the present invention. Obtainable.

  The electronic device provided with the frequency synthesizer according to the present invention is not limited to a digital camera. In addition to this, for example, various devices such as various sensor devices and electronic computers are generally provided with a general semiconductor integrated circuit. Is included. According to the present invention, the effect of reducing power consumption can be obtained for all electronic devices.

  FIG. 27E is a diagram showing an overview of an electronic control device including the frequency synthesizer of the present invention and a moving body including the electronic control device. An automobile 1840 as a moving body includes an electronic control unit 1850. This electronic control unit 1850 is a semiconductor integrated circuit having the frequency synthesizer according to the present invention, and includes an engine / transmission control LSI 1851 for controlling the engine, transmission, etc. of the automobile 1840. The automobile 1840 includes a navigation device 1841. Similarly to the electronic control unit 1850, the navigation device 1841 also includes a navigation LSI 1842 that is a semiconductor integrated circuit having the frequency synthesizer according to the present invention.

  Since the frequency synthesizer according to the present invention can be operated with less power consumption than before, the engine / transmission control LSI 1851 and the electronic control device 1840 including the same can also operate at low power. Similarly, the navigation LSI 1842 and the navigation device 1841 including the navigation LSI 1842 can also operate at low power.

  Further, for the semiconductor integrated circuit provided in the electronic control unit 1850 other than the engine / transmission control LSI 1851, the logic circuit provided in the semiconductor integrated circuit is the frequency synthesizer according to the present invention, so that the same as described above. The effect of can be obtained. The same can be said for the navigation device 1841. The power consumption of the automobile 1840 can be reduced by reducing the power consumption of the electronic control unit 1850.

  Note that the electronic control device including the frequency synthesizer according to the present invention is not limited to the one that controls the engine and the transmission described above. It includes all devices that control the power source. According to the present invention, an effect of reducing power consumption can be obtained for such an electronic control device. In addition, the mobile body including the frequency synthesizer according to the present invention is not limited to an automobile, and besides this, for example, an electronic control that controls an engine or a motor that is a power source, such as a train or an airplane. Includes all equipment with devices. According to the present invention, an effect of reducing power consumption can be obtained for such a moving body.

  As described above, according to the frequency synthesizer of the present embodiment, it is possible to realize a desired frequency by performing a high-precision frequency division operation while suppressing an increase in circuit scale. However, a plurality of frequency clocks can be generated without using a conventional PLL. Further, by applying the frequency synthesizer of this embodiment to a PLL frequency divider or a clock generation system, it is possible to improve the characteristics of the clock generation unit and reduce the power consumption, which are not found in the conventional PLL.

  It should be noted that the present invention is not limited to those shown in the above-described embodiments, and those skilled in the art can also make changes and applications based on the description in the specification and well-known techniques. Yes, included in the scope of protection.

  The present invention has an effect that a high-precision frequency dividing operation can be realized while suppressing an increase in circuit, an effect that a characteristic of a clock generation unit can be improved, and a low power consumption can be achieved. This is useful for a frequency synthesizer and a phase-locked loop for generating a clock having a frequency, a clock generation method, and the like.

The block diagram which shows the structure of the clock generation apparatus which concerns on embodiment of this invention The figure which shows the relationship between the reference clock and frequency-divided clock in this embodiment The figure which shows the relationship over multiple cycles of the reference | standard clock and frequency-divided clock in this embodiment Conceptual diagram showing the relationship between the number of phases and periodicity in polar coordinate format Conceptual diagram for explaining generation of an N / M divided clock in this embodiment The figure which shows an example of the circuit mounting form of a clock selection means and a phase number generation means The figure which shows the operation example at the time of the clock switching control in the structure of FIG. The figure which shows an example of the circuit mounting form of the clock selection means and phase number generation means which concern on this embodiment The figure which shows the operation example at the time of clock switching control in the structure of the clock selection means of this embodiment, and a phase number generation means The figure which shows an example of the output clock of the frequency synthesizer in this embodiment An explanatory diagram comparing the conventional configuration and the configuration of the present embodiment The figure explaining the 1st application example of this embodiment applied to dynamic frequency control The figure explaining the 2nd application example of this embodiment applied to the spread spectrum clock generation The figure explaining the 3rd application example and 4th application example of this embodiment applied to the characteristic improvement of PLL The figure explaining the 5th application example of this embodiment which is another application example to PLL. The figure explaining the 6th application example of this embodiment applied also to the precision improvement of fractional PLL. The figure which shows the component of the phase selection synthesizer which implement | achieves fractional PLL The figure which shows an example of the circuit mounting form of the clock selection means and phase number generation means in the phase selection synthesizer of FIG. The figure explaining the 7th application example of this embodiment for expanding the frequency range. The figure which shows the structure of the 8th application example of this embodiment as an example for improving a duty ratio. The figure which shows the timing of the clock in an 8th application example The figure which shows the structure of the 9th application example of this embodiment as another example for improving a duty ratio. The figure which shows the timing of the clock in a 9th application example The figure which shows the structure of the 10th application example of this embodiment as a further another example for improving a duty ratio. The figure which shows the structure of the phase mixer in a 10th application example. The figure which shows the timing of the clock by the phase mixer of FIG. The figure which shows the structure of the various apparatuses to which the frequency synthesizer concerning this embodiment is applied. The figure which shows the structure of the clock generation apparatus for producing | generating two types of frequencies in a prior art.

Explanation of symbols

501 Reference clock generator 502, 503, 1002, 2006, 2007 Phase selection synthesizer 504 Clock selection means 505, 1401 Phase number generation means 601, 1402, 1502 Adder 602, 603, 604, 1403, 1601 Register 605, 606 Multiplexer 607 Match determination unit 608 AND element 609, 610 Logical inversion element 1001 PLL
1110, 1120, 1121, 1222, 1221, 1311 Frequency divider 1111, 1122, 1312 Phase comparator 1112, 1123, 1222, 1313 VCO (Voltage Controlled Oscillator)
1501 random number generator 1604 selection circuit 1701, 1702 1/2 frequency divider 1703 exclusive OR negation element 1901 set / reset latch 2003 phase mixer

Claims (24)

A frequency synthesizer that generates an N / M divided clock (N and M are integers) from an N-phase clock,
Phase number generating means for generating a predetermined phase number from the frequency dividing denominator M and the frequency dividing numerator N;
A clock selection unit that selects a clock phase corresponding to the phase number output from the phase number generation unit from the N phase clock, and outputs the N / M divided clock;
A frequency synthesizer comprising: A frequency synthesizer according to claim 1,
The phase number generation means is a frequency synthesizer that accumulates a value of (MN) for each cycle of the N / M frequency-divided clock, and uses a remainder obtained by dividing the accumulated value by N as the phase number. A frequency synthesizer according to claim 1,
The clock selection means includes a first clock selection circuit that selects a first clock, and a second clock selection circuit that selects a second clock,
The phase number generating means includes a first register that uses the first clock and a second register that uses the second clock,
The second clock selection circuit is controlled by the output of the first register, and the first clock selection circuit is controlled by the output of the second register to supply the N / M divided clock. Frequency synthesizer to play. A frequency synthesizer according to claim 3,
The phase number generation means is a frequency synthesizer having comparison means for comparing the values of the first register and the second register and controlling the output of the N / M divided clock. A frequency synthesizer that generates an N / (M + X) frequency-divided clock (N and M are integers and X is a decimal number less than 1) from an N-phase clock,
Phase number generating means for generating a predetermined phase number from the frequency dividing denominator M, the frequency dividing numerator N and the decimal setting X;
A clock selection unit that selects a clock phase corresponding to the phase number output by the phase number generation unit from the N phase clock, and outputs the N / (M + X) divided clock;
A frequency synthesizer comprising: A frequency synthesizer according to claim 5,
The phase number generation means includes a first accumulation circuit that accumulates the value of X every cycle of the N / M divided clock;
A second accumulation circuit for accumulating the value of (MN) every cycle of the N / M divided clock;
A frequency obtained by adding the carry raised to an integer in the first accumulation circuit to the second accumulation circuit, and using the remainder obtained by dividing the accumulated value of the second accumulation circuit by N as the phase number. Synthesizer. A frequency synthesizer according to claim 5,
The clock selection means includes a first clock selection circuit that selects a first clock, and a second clock selection circuit that selects a second clock,
The phase number generating means includes a first register that uses the first clock and a second register that uses the second clock,
The second clock selection circuit is controlled by the output of the first register, and the first clock selection circuit is controlled by the output of the second register, and the N / (M + X) divided clock. Supply frequency synthesizer. A frequency synthesizer according to claim 7,
The phase number generation means is a frequency synthesizer having comparison means for comparing the values of the first register and the second register and controlling the output of the N / (M + X) divided clock. The frequency synthesizer according to claim 1 or 5, wherein the M / N divided clock is divided by N / M;
A phase comparator that compares the phase of a clock supplied from the frequency synthesizer with a reference clock;
A voltage-controlled oscillator that generates an M / N frequency-divided clock that is phase-synchronized with the reference clock according to the output of the phase comparator;
A phase-locked loop comprising: The first frequency synthesizer according to claim 1 or 5, wherein the M / P divided clock is divided by P / M;
6. The second frequency synthesizer according to claim 1 or 5, wherein the M / P divided clock is divided by P / N;
A phase comparator that compares the phase of a clock supplied from the first frequency synthesizer with a reference clock;
A voltage controlled oscillator that generates an M / P frequency-divided clock that is phase-synchronized with the reference clock according to the output of the phase comparator;
A phase-locked loop in which the second frequency synthesizer divides the M / P divided clock by P / N to generate an M / N divided clock of the reference clock; The first frequency synthesizer according to claim 1 or 5, wherein the QM / P divided clock is divided by P / QM;
The second frequency synthesizer according to claim 1 or 5, wherein the QM / P divided clock is divided by P / Q;
A phase comparator that compares the phase of a clock supplied from the first frequency synthesizer with a reference clock;
A voltage controlled oscillator that generates a QM / P frequency-divided clock that is phase-synchronized with the reference clock according to the output of the phase comparator;
A phase-locked loop in which the second frequency synthesizer generates an M-multiplied clock of the reference clock by dividing the QM / P divided clock by P / Q. A frequency synthesizer according to claim 1 or claim 5;
A random number generator for outputting a random value,
A phase-locked loop in which a fixed value and the random number are added to obtain the divided denominator M, divided numerator N, or decimal setting X. 6. The frequency synthesizer according to claim 1, wherein the first and second frequency synthesizers respectively generate first and second N / M frequency-divided clocks having a difference value having a constant phase angle.
First and second frequency dividers that respectively divide the first and second N / M divided clocks to generate first and second N / 2M divided clocks;
A logical operation unit that performs a logical operation on the first and second N / 2M divided clocks to generate an N / M divided clock;
A phase-locked loop comprising: A frequency synthesizer according to claim 1 or claim 5;
One or more ½ dividers for dividing the clock supplied from the frequency synthesizer;
A selection circuit for selecting a clock output from the frequency synthesizer or a clock output from the ½ divider;
A phase-locked loop comprising: 6. The frequency synthesizer according to claim 1, wherein the first and second frequency synthesizers respectively generate first and second N / M frequency-divided clocks having a difference value having a constant phase angle.
A set / reset holding means having the first N / M divided clock as a set input, the second N / M divided clock as a reset input, and a set or reset result as an N / M divided clock;
A phase-locked loop comprising: 6. The frequency synthesizer according to claim 1, wherein the first, second, and second frequency synthesizers respectively generate first, second, and third N / M frequency-divided clocks having a difference value having a constant phase angle. 3 frequency synthesizers,
A phase mixer that mixes the phases of the first and second N / M divided clocks to generate a fourth N / M divided clock;
First and second frequency dividers that divide the third and fourth N / M divided clocks to generate first and second N / 2M divided clocks;
A logical operation unit that performs a logical operation on the first and second N / 2M divided clocks to generate an N / M divided clock;
A phase-locked loop comprising: 6. The frequency synthesizer according to claim 1, wherein the first, second, and second frequency synthesizers respectively generate first, second, and third N / M frequency-divided clocks having a difference value having a constant phase angle. 3 frequency synthesizers,
A phase mixer that mixes the phases of the first and second N / M divided clocks to generate a fourth N / M divided clock;
A set / reset holding means having the third N / M divided clock as a set input, the fourth N / M divided clock as a reset input, and a set or reset result as an N / M divided clock;
A phase-locked loop comprising: A clock generation method for generating an N / M frequency-divided clock (N and M are integers) of a reference clock having an N-phase clock phase,
Accumulating the value of (MN) to at least N and the least common multiple of (MN) for each cycle of the N / M divided clock;
Selecting a clock phase corresponding to a remainder obtained by dividing an accumulation result by N from N phase clock phases of the reference clock;
A clock generation method.   A communication apparatus comprising the frequency synthesizer according to claim 1 or 5.   An information reproducing apparatus comprising the frequency synthesizer according to claim 1 or 5.   An image display device comprising the frequency synthesizer according to claim 1.   An electronic device comprising the frequency synthesizer according to claim 1.   An electronic control device comprising the frequency synthesizer according to claim 1.   A moving body comprising the frequency synthesizer according to claim 1.

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