JP4499009B2 - Frequency dividing circuit, clock generation circuit, and electronic device equipped with the same - Google Patents

Description

  The present invention relates to a frequency dividing circuit, a clock generation circuit, and an electronic device equipped with the frequency dividing circuit used in a PLL (Phase Locked Loop) or the like.

An oscillator having a PLL mechanism is widely used for frequency control by a microcomputer or the like. In a PLL using a voltage controlled oscillator (VCO) with a high frequency, the count speed of the frequency divider is not in time, so a fixed frequency divider called a prescaler may be inserted or a pulse swallow method may be adopted. . The pulse swallow method is disclosed in Patent Document 1, for example. A PLL employing a pulse swallow system includes a dual modulus prescaler that can switch between two types of frequency division ratios and a programmable frequency divider, and divides the output of the voltage controlled oscillator by N or (N + 1).
JP 2002-076884 A

  As described above, if the frequency division ratio (number of digits) of the frequency divider that divides the output of the voltage controlled oscillator is increased, it is difficult to increase the upper limit frequency that can be stably divided.

  If the division ratio (number of digits) is reduced, it is easy to make a high-speed divider, but instead, it is necessary to increase the reference frequency, and the step frequency interval that can be locked by the PLL is expanded, and fine frequencies are set. Difficult to do.

  In this regard, if a DDS (Direct Digital Synthesizer) is used, it is possible to perform numerical waveform synthesis including a decimal part. However, DDS requires a large adder to operate at a high frequency, and power consumption increases.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a frequency dividing circuit, a clock generating circuit, and a frequency generating circuit that can divide an input clock by a numerical value including a decimal part with a simple configuration. It is to provide an electronic device equipped with.

  In order to solve the above-described problem, a frequency dividing circuit according to an aspect of the present invention divides using a bit data of an integer part out of a frequency dividing ratio defined by a plurality of bits of digital data including a decimal part. A counter and an integration circuit for integrating the bit data of the decimal part according to the load cycle to the counter. The integration circuit adds 1 to the frequency division ratio when the integrated value of the decimal value becomes 1 or more.

  According to this aspect, the input clock can be divided by a numerical value including a decimal part with a simple configuration. Further, the value of the decimal part can be reflected in the frequency division ratio without being truncated.

  Another embodiment of the present invention is also a frequency divider circuit. This divider circuit is a counter that sets bit data of the integer part of the division ratio defined by digital data of a plurality of bits including a decimal part, and counts down the bit data corresponding to the input clock. Compare the integration circuit that integrates the bit data of the decimal part according to the load cycle to the counter, the reference register that holds 1 as the reference value, and the counter value and the value of the reference register. And a comparison circuit that outputs an active signal when it is activated. The integration circuit includes an integration register corresponding to the number of bits in the decimal part, and temporarily sets the reference value of the reference register to 0 when the integration value of the bit data in the decimal part overflows the integration register.

  According to this aspect, the input clock can be divided by a numerical value including a decimal part with a simple configuration. Further, the value of the decimal part can be reflected in the frequency division ratio without being truncated.

  Yet another embodiment of the present invention is also a clock generation circuit. The clock generation circuit compares a predetermined reference clock with a feedback clock starting from the output of the clock generation circuit, and outputs a control signal for canceling the error, and a control signal according to the control signal. A voltage-controlled oscillator that outputs a clock at the oscillation frequency, and a frequency-dividing circuit according to any one of the above aspects that divides the output clock of the voltage-controlled oscillator and inputs the divided clock to the phase comparator as a feedback clock; Is provided.

  According to this aspect, since it is possible to divide by a numerical value including a decimal part, the frequency of the output clock can be set flexibly.

  Yet another embodiment of the present invention is also a clock generation circuit. The clock generation circuit divides a given clock to generate a reference clock, and the frequency dividing circuit according to any one of the above-described aspects, a reference clock, and a feedback clock starting from the output of the clock generation circuit. A phase comparator that outputs a control signal for comparing and canceling those errors, a voltage-controlled oscillator that outputs a clock at an oscillation frequency corresponding to the control signal, and an output clock of the voltage-controlled oscillator are divided and divided. And the frequency dividing circuit according to any one of the above-described modes, which inputs the clock as a feedback clock to the phase comparator.

  According to this aspect, since it is possible to divide by a numerical value including a decimal part, the frequency of the output clock can be set flexibly. Since the frequency of the reference clock can be easily increased, the output response frequency of the phase comparator can be increased.

  A loop filter that reduces a noise component included in the control signal output from the phase comparator and outputs the noise component to the voltage controlled oscillator may be further provided. By making the reference frequency high, the control signal of the phase comparator output has a lower frequency component removed than before increasing the reference frequency, and even if the loop filter has a simple configuration with low cost, A high filter effect can be obtained.

  Yet another embodiment of the present invention is an electronic device. The electronic device includes a clock generation circuit and a reproduction circuit that reproduces predetermined data using a clock generated by the clock generation circuit.

  It should be noted that any combination of the above-described constituent elements and a representation obtained by converting the expression of the present invention between apparatuses, methods, systems, and the like are also effective as an aspect of the present invention.

  According to the present invention, an input clock can be divided by a numerical value including a decimal part with a simple configuration.

  First, before describing the details of the frequency dividing circuit in the embodiment of the present invention, the clock generating circuit 100 having a PLL mechanism to which the frequency dividing circuit is applied will be described. FIG. 1 is a diagram showing a configuration of a clock generation circuit 100 in which a frequency divider circuit according to an embodiment of the present invention is used. The clock generation circuit 100 includes a reference oscillator 105, a first frequency divider 110, a phase comparator 120, a loop filter 130, a voltage controlled oscillator 140, and a second frequency divider 150. At least the first divider circuit 110, the phase comparator 120, and the second divider circuit 150 may be integrated on a single semiconductor substrate.

  A crystal oscillator or the like is used as the reference oscillator 105 and generates a clock that is a source of a clock output from the clock generation circuit 100. The first frequency dividing circuit 110 generates a reference clock to be supplied to the phase comparator 120 by using a predetermined first frequency division ratio N1 for the clock input from the reference oscillator 105. The detailed configuration of the first frequency dividing circuit 110 will be described later.

  The phase comparator 120 compares the frequency of the reference clock input from the first frequency dividing circuit 110 with the frequency of the feedback clock input from the second frequency dividing circuit 150 described later, and cancels the difference therebetween. Outputs control voltage. The loop filter 130 removes high frequency components and noise included in the control voltage output from the phase comparator 120. The loop filter 130 determines the response of the PLL based on the time constant. A low-pass filter can be used as the loop filter 130. The low-pass filter may be a passive filter composed of a resistor and a capacitor, or an active filter using an operational amplifier.

  The voltage controlled oscillator 140 is an oscillator whose oscillation frequency changes according to the control voltage. The voltage control oscillator 140 controls the oscillation frequency according to the control voltage so as to approach an integrated value of the frequency of the reference clock and a second frequency division ratio N2 of the second frequency dividing circuit 150 described later. The control is repeated by the PLL mechanism, and finally locks to the product of the frequency of the reference clock and the frequency of the second frequency division ratio N2. The output clock of the voltage controlled oscillator 140 is output to the outside as an output signal of the clock generation circuit 100 and is fed back to the second frequency dividing circuit 150.

  The second frequency dividing circuit 150 generates a feedback clock output to the phase comparator 120 using the output clock of the voltage controlled oscillator 140 and a predetermined second frequency division ratio N2. The detailed configuration of the second frequency dividing circuit 150 will be described later.

Assuming that the frequency of the output clock of the clock generation circuit 100 having such a PLL mechanism is fo, the oscillation frequency of the reference oscillator 105 is fosc, the first division ratio is N1, and the second division ratio is N2, the following equation: 1 holds.
fo = fosc / N1 × N2 (Formula 1)

  Here, if a value including a decimal part can be set in the first frequency division ratio N1 and the second frequency division ratio N2, a desired output frequency fo can be generated flexibly and easily. That is, a desired output frequency can be set without dividing the frequency down to the frequency step at which the reference frequency is desired to be changed. Also, from the frequency spectrum of the control signal included in the phase comparator output, the reference frequency, the first division ratio N1, and the second division ratio N2 that can reduce the influence of noise on useful bands such as the voice band are selected. It becomes possible.

  Hereinafter, a detailed configuration of the first frequency dividing circuit 110 will be described. FIG. 2 is a diagram illustrating a detailed configuration of the first frequency dividing circuit 110 according to the first embodiment of the present invention. The first frequency dividing circuit 110 according to the first embodiment includes a buffer 12, a programmable counter 14, an integration circuit 16, an integration register 17, a comparison circuit 18, and a reference register 20. The first frequency dividing circuit 110 may be integrated on a single semiconductor substrate. In FIG. 2, the first frequency division ratio N1 is defined by 20-bit digital data, with the upper 15 bits corresponding to the integer part and the lower 5 bits corresponding to the decimal part. The upper 15 bits are input to the programmable counter 14 via the buffer 12, and the lower 5 bits are input to the integrating circuit 16.

  The programmable counter 14 counts down the data for the upper 15 bits of the set first frequency division ratio N1 according to the input clock. The reference register 20 is a register that holds a reference value to be compared with the value of the programmable counter 14. A register that holds either 0 or 1 may be used, or a register that holds a plurality of bits. In this case, the value of the least significant bit can be used as a reference value. The reference register 20 is set to 1. The comparison circuit 18 compares the value of the programmable counter 14 with the value of the reference register 20 and outputs an active signal to the phase comparator 120 when they match. For example, a low level signal is output when both values do not match, and a high level signal is output when they match. Normally, when the value set in the programmable counter 14 is counted down to 1, an active signal is output, and the input clock is divided by the value of the integer part of the first frequency division ratio N1. .

  The integration circuit 16 includes an integration register 17 and integrates data for the lower 5 bits of the first frequency division ratio N1 into the integration register 17. The integration register 17 corresponds to the number of decimal bits of the first frequency division ratio N1, and is a 5-bit register in this embodiment. The integration register 17 outputs a carry signal for temporarily setting 0 to the reference register 20 when the integration value overflows. Here, a carry signal is output when the integrated value is 32 or more.

  When the value of the reference register 20 or the value of the least significant bit thereof becomes 0, the comparison circuit 18 outputs an active signal when the value of the programmable counter 14 is counted down to 0. That is, the programmable counter 14 counts 0 and divides the setting value by adding 1.

  The active signal output from the comparison circuit 18 defines the load timing from the buffer 12 to the programmable counter 14 and the integration timing of the integration circuit 16. The buffer 12 sets the data for the upper 15 bits of the first frequency division ratio N1 held in the programmable counter 14 according to the input timing of the active signal. The integrating circuit 16 integrates data for the lower 5 bits of the first frequency division ratio N1 in accordance with the input timing of the active signal. The reference register 20 is reset to 1 when holding 0 after the comparison circuit 18 outputs the active signal. When the least significant bit is used as a reference value, the least significant bit is reset to 1.

  In the configuration of FIG. 2, the lower 5 bits of the first frequency division ratio N1 have a function similar to that of a pulse swallow counter used in a pulse swallow PLL mechanism. That is, the decimal part of the first frequency division ratio N1 is used as reference information for switching control between the value of the integer part of the frequency division ratio and the value of the integer value +1.

  Although FIG. 2 shows the configuration of the first frequency dividing circuit 110, the second frequency dividing circuit 150 has the same configuration. Instead of the first frequency division ratio N1, the second frequency division ratio N2 is used. The programmable counter 14 counts down the data for the upper 15 bits of the set second frequency division ratio N2 in accordance with the output clock of the phase comparator 120. Others are the same as the description of the first frequency dividing circuit 110.

  FIG. 3 is a diagram illustrating an operation example of the first frequency dividing circuit 110 according to the first embodiment. An example in which 192.25 is set as the first frequency division ratio N1 will be described. If the first frequency division ratio N1 is defined by 20-bit digital data, 192.25 is described as “000000011000000.01000”. This digital data is separated into upper 15 bits “000000011000000” corresponding to the integer part and lower 5 bits “01000” corresponding to the decimal part. The upper 15 bits “000000011000000” are set in the programmable counter 14, and the lower 5 bits “01000” are input to the integrating circuit 16. When the upper 15 bits “000000011000000” corresponding to 192 is used as the frequency division ratio, the decimal part is not reflected in the generated clock. In the present embodiment, a mechanism for reflecting this decimal part in the frequency division ratio is provided.

  In FIG. 3, the first division ratio N1 is set such that the upper 15 bits “000000011000000” are set in the programmable counter 14 and the lower 5 bits “01000” are accumulated in the integration register 17. The reference register 20 holds 1. The programmable counter 14 counts down, and when it reaches 1, it enters the next load cycle with the first frequency division ratio N1. In the next load cycle, the upper 15 bits “000000011000000” are set in the programmable counter 14 and the lower 5 bits “01000” are accumulated in the integration register 17. The integration register 17 holds “10000” as a result of integration. The reference register 20 holds 1.

  Similarly, the accumulation register 17 becomes “11000” in the next load cycle, and further becomes “00000” in the next load cycle and overflows. In response to this, the reference register 20 transits to 0. In this load cycle, the programmable counter 14 counts down to 0, and the division ratio becomes 193. In the next load cycle, the integration register 17 becomes “01000” and the reference register 20 returns to 1. The following similar processing is repeated.

  If data remains when the integration register 17 overflows, the data is used as it is. For example, if “11000” is accumulated twice, it overflows but “10000” remains in the accumulation register 17. Then, when accumulated next, it overflows again and "01000" remains. In this way, all values of the decimal part are reflected in the frequency division ratio.

  FIG. 4 is a diagram illustrating a detailed configuration of the first frequency dividing circuit 110 according to the second embodiment of the present invention. In the first frequency dividing circuit 110 according to the second embodiment, the integer part of the first frequency dividing ratio N1 is set in the reference register 21 as compared with the first embodiment. The first frequency dividing circuit 110 according to the second embodiment includes a buffer 12, a programmable counter 15, an integration circuit 16, an integration register 17, a comparison circuit 19, and a reference register 21. The first frequency dividing circuit 110 may be integrated on a single semiconductor substrate. Also in FIG. 4, the first frequency division ratio N1 is defined by 20-bit digital data, with the upper 15 bits corresponding to the integer part and the lower 5 bits corresponding to the decimal part. The upper 15 bits are input to the reference register 21 via the buffer 12, and the lower 5 bits are input to the integrating circuit 16.

  The programmable counter 15 counts up according to the input clock until it matches a reference value described later from 1. The reference register 21 is a register that holds a reference value to be compared with the value of the programmable counter 15. In the reference register 21, the upper 15 bits of the first frequency division ratio N1 are set. The comparison circuit 19 compares the value of the programmable counter 15 and the value of the reference register 21 and outputs an active signal to the phase comparator 120 when they match. Normally, when the value set in the programmable counter 15 is counted up to the value of the integer part of the first division ratio N1, an active signal is output, and the input clock is set to the first division ratio N1. It is divided by an integer value.

  The integration circuit 16 includes an integration register 17 and integrates data for the lower 5 bits of the first frequency division ratio N1 into the integration register 17. The integration register 17 corresponds to the number of decimal bits of the first frequency division ratio N1, and is a 5-bit register in this embodiment. The integration register 17 outputs a carry signal for temporarily adding 1 to the reference register 21 when the integration value overflows. Here, a carry signal is output when the integrated value is 32 or more.

  When the value of the reference register 21 becomes +1 of the integer part of the first frequency division ratio N1, the comparison circuit 19 outputs an active signal when the value of the programmable counter 15 is counted up to the value of the integer part +1. become.

  The active signal output from the comparison circuit 19 defines the load timing from the buffer 12 to the reference register 21 and the integration timing of the integration circuit 16. The buffer 12 sets the data for the upper 15 bits of the first frequency division ratio N1 held in the reference register 21 according to the input timing of the active signal. The integration circuit 16 integrates the values of the lower 5 bits of the first frequency division ratio N1 according to the input timing of the active signal. The reference register 21 is reset to the value of the integer part of the first division ratio N1 when the comparison circuit 19 holds the value +1 of the integer part of the first division ratio N1 after the comparison circuit 19 outputs the active signal. .

  As described above, according to the frequency dividing circuit in the first and second embodiments, an input clock can be divided by a numerical value including a decimal part. If a clock generation circuit having a PLL mechanism divides the oscillation frequency of a crystal oscillator including a decimal part by this frequency dividing circuit, the reference clock of the phase comparator can be easily increased. Therefore, a high frequency output clock can be easily obtained. In addition, it can be realized with a simple configuration as compared with the case where the pulse swallow method or the DSS is used.

  In addition, a method that employs a pulse swallow method and repeats n division and n + 1 division by a prescaler generates an error pulse at the output of the phase comparator that is difficult to remove by a loop filter. In this respect, according to the present frequency dividing circuit, the error pulse can be dispersed at a high frequency because the integration method is employed to reflect the fraction. Therefore, the ripple of the error pulse can be shaped to a band that can be easily formed as a filter.

  Further, the frequency of the reference clock of the phase comparator can be easily set outside the audio band, and the factor of the characteristic deterioration of the clock generation circuit provided with the PLL mechanism can be greatly improved. That is, a high-quality clock source can be constructed at a low cost by a simple loop filter. Therefore, the adverse effect on the sound quality from the clock source can be reduced, and the filter design is facilitated.

  Next, an electronic device 200 equipped with the clock generation circuit 100 will be described. FIG. 5 is a diagram illustrating a configuration of an electronic device 200 in which the clock generation circuit 100 is mounted. The electronic device 200 corresponds to a set device such as a television and has a function of reproducing video data and audio data. In FIG. 5, only the block for reproducing the audio data ADATA is drawn.

  The electronic device 200 includes a clock generation circuit 100, an audio data reproduction circuit 210, an audio data processing block 220, and a speaker 230. The audio data reproduction circuit 210 reproduces the audio data ADATA according to the clock generated by the clock generation circuit 100 in the above embodiment. The audio data processing block 220 performs digital / analog conversion, various effect processing, and the like on the reproduced audio data ADATA, and outputs the result to the speaker 230. In the case of video data, it is displayed on a display (not shown) through a video data reproduction circuit (not shown) and a video data processing block.

  Since the electronic device 200 includes the clock generation circuit 100 according to the above-described embodiment, a clock having a desired frequency can be generated with a simple configuration, and the clock can be used for reproducing audio data and video data. Can do.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there.

  For example, in FIG. 2 and FIG. 4, the example in which the clock input to the first frequency dividing circuit 110 is supplied from the reference oscillator 105 has been described. In this regard, a clock transmitted from the outside may be used as a given clock for the first frequency dividing circuit 110.

  Further, in order to adjust the frequency of the output clock, a prescaler that divides the frequency by a predetermined division ratio may be provided at the subsequent stage of the voltage controlled oscillator.

It is a figure which shows the structure of the clock generation circuit in which the frequency divider circuit in embodiment is used. FIG. 3 is a diagram illustrating a detailed configuration of a first frequency divider circuit in the first embodiment. FIG. 4 is a diagram illustrating an operation example of a first frequency divider circuit in the first embodiment. FIG. 6 is a diagram illustrating a detailed configuration of a first frequency divider circuit in the second embodiment. It is a figure which shows the structure of the electronic device carrying a clock generation circuit.

Explanation of symbols

  12 buffers, 14 programmable counters, 16 accumulation circuits, 17 accumulation registers, 18 comparison circuits, 20 reference registers, 100 clock generation circuits, 105 reference oscillators, 110 first divider circuits, 120 phase comparators, 130 loop filters, 140 voltages Control oscillator 150 second frequency divider 200 electronic device 210 audio data reproduction circuit 220 audio data processing block 230 speaker

Claims (6)

Of the division ratio defined by the digital data of multiple bits including the decimal part, the bit data of the integer part is set, and the counter counts down the bit data corresponding to the input clock,
An integration circuit that integrates the fractional bit data according to a load cycle to the counter; and
A reference register that holds 1 as a reference value;
A comparison circuit that compares the value of the counter with the value of the reference register and outputs an active signal when they match, and
The integration circuit includes an integration register corresponding to the number of bits of the decimal part, and temporarily sets the reference value of the reference register to 0 when the integration value of the bit data of the decimal part overflows the integration register A frequency dividing circuit characterized by: Frequency dividing circuit according to claim 1, characterized in that it is integrated on a single semiconductor substrate. A phase comparator that compares a predetermined reference clock with a feedback clock starting from the output of the clock generation circuit and outputs a control signal for canceling the error;
A voltage controlled oscillator that outputs a clock at an oscillation frequency according to the control signal;
The frequency dividing circuit according to claim 1 or 2 , wherein the output clock of the voltage controlled oscillator is divided, and the divided clock is input to the phase comparator as the feedback clock;
A clock generation circuit comprising: The frequency dividing circuit according to claim 1 or 2 , which divides a given clock to generate a reference clock;
A phase comparator that compares the reference clock with a feedback clock starting from the output of the clock generation circuit and outputs a control signal for canceling the error;
A voltage controlled oscillator that outputs a clock at an oscillation frequency according to the control signal;
The frequency dividing circuit according to claim 1 or 2 , wherein the output clock of the voltage controlled oscillator is divided, and the divided clock is input to the phase comparator as the feedback clock;
A clock generation circuit comprising: 5. The clock generation circuit according to claim 3 , further comprising a loop filter that reduces a noise component included in the control signal output from the phase comparator and outputs the noise component to the voltage controlled oscillator. A clock generation circuit according to any one of claims 3 to 5 ,
A reproducing circuit for reproducing predetermined data using a clock generated by the clock generating circuit;
An electronic device comprising:

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