JPH0951273A - A/d converter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a timing in the A/D signal conversion in matching with each other at all times by generating a conversion clock for signal conversion synchronously with a timing when a control signal is given to a sample-and-hold circuit. SOLUTION: A conversion block is outputted from a voltage controlled oscillator 3 and fed to an A/D converter 2, frequency-divided by a frequency divider 4 and the result is fed to a phase comparator 5, in which a phase with a control signal is compared. When the phase comparator 5 detects a phase difference and a harmonic being a noise component is cut from the phase difference signal by a low pass filter 6 and the resulting signal is fed to the voltage controlled oscillator 3. Then the voltage controlled oscillator 3 generates newly a conversion clock based on the supplied phase difference and provides an output. The conversion clock outputted from the voltage controlled oscillator 3 is synchronously with the phase of the control signal through a series of feedback operations.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-digital conversion circuit, and more particularly to a high speed analog-digital conversion circuit used in a demodulation circuit for digital communication.

[0002]

2. Description of the Related Art Conventionally, an analog-digital conversion circuit for converting a voltage value of an analog signal into a digital signal has been used in various signal processing devices.

FIG. 2 is a block diagram showing a configuration example of a conventional analog-digital conversion circuit.

In this conventional example, as shown in FIG. 2, a sample-and-hold circuit 101 for sampling an input analog signal and sequentially holding and outputting the sampled value at the timing of a control signal from the outside, and a sample-and-hold circuit. An analog-digital converter 102 that converts the value output from 101 into a digital signal in synchronization with an external control signal, and an oscillator that generates a conversion clock for performing a signal conversion operation in the analog-digital converter 102. And 108.

The operation of the analog-digital conversion circuit configured as described above will be described below.

First, when an analog signal is input to the analog-to-digital conversion circuit, the sample and hold circuit 101 samples the voltage value of the analog signal, and every time a control signal is input from the outside, the sampled value is sampled. Is held and output, and the sampling value is updated.

Then, the analog-digital converter 102
At the timing of the external control signal, conversion of the voltage value held and output into a digital value is started.

Here, the conversion operation of the voltage value to the digital value is performed stepwise by the conversion clock supplied from the oscillator 108.

The interval at which the control signal is input needs to be longer than the time required to convert the voltage value into a digital value in the analog-digital converter 102.

Here, the sample and hold circuit 10
The necessity of 1 is described.

In general digital communication, the modulated carrier wave is converted directly into a digital value, or is converted into a digital value after being converted into an intermediate frequency, and then converted into a digital value. Conversion is taking place.

However, since the frequency of the carrier wave and the intermediate frequency is higher than several tens of kHz which is the throughput of the general analog-digital converter (the number of times the analog-digital converter 102 can repeatedly convert per unit time). , It is not possible to directly convert a carrier wave or an intermediate frequency that becomes an analog signal into a digital value.

Therefore, the analog signal is sent to the analog-digital converter 1 via the sample-and-hold circuit 101.
If the sample-and-hold circuit 101 is configured to be input to the H.02, and the sample-and-hold circuit 101 performs sample-and-hold at a long interval that does not exceed the throughput of the analog-digital converter 102, aliasing occurs. Apparently, the frequency can be converted by the analog-digital converter 102. As a result, even when a signal having a frequency exceeding the throughput of the analog-digital converter 102 is input, conversion into a digital value is possible.

[0014]

However, in the above-mentioned conventional example, since the conversion operation to the digital value in the analog-digital converter is performed in synchronization with the conversion clock, the cycle of the conversion clock and the timing of the control signal. If the values do not match, all the ringing generated in the sample and hold switching of the sample and hold circuit is included in the converted value as noise.

Therefore, a method is used in which a flip-flop is provided in the analog-digital conversion circuit to match the above timings.

FIG. 3 is a block diagram showing a configuration example of a conventional analog-digital conversion circuit including a flip-flop.

The circuit shown in FIG. 3 samples the input analog signal and outputs the sampled value from the sample-and-hold circuit 201, which sequentially holds and outputs the sampled value at the timing of the control signal from the outside. Sample-and-hold circuit 201, and an analog-digital converter 202 that converts the converted value into a digital signal in synchronization with an external control signal.
And a flip-flop 209 for controlling the operation timing of the analog-digital converter 202, and a flip-flop 2 for generating a conversion clock for executing a signal conversion operation in the analog-digital converter 202.
And an oscillator 208 that outputs a pulse for 09.

The operation of the analog-digital conversion circuit configured as described above will be described below.

First, when an analog signal is input to the analog-digital conversion circuit, the sample-and-hold circuit 201 samples the voltage value of the analog signal, and every time a control signal is input from the outside, the sampled value is sampled. Is held and output, and the sampling value is updated.

Then, the analog-digital converter 202
At the timing of the external control signal, conversion of the voltage value held and output into a digital value is started.

Here, the conversion operation of the voltage value into the digital value is performed stepwise by the conversion clock supplied from the oscillator 208.

Further, the sample and hold circuit 201
The timing at which the control signal is input to the input terminal coincides with the timing of the conversion clock under the control of the flip-flop 209.

The interval at which the control signal is input must be longer than the time required to convert the voltage value into a digital value in the analog-digital converter 202.

However, when the timing of the control signal is adjusted, the adjustment accuracy is limited by the cycle of the conversion clock, so that the timing error is large and the phase of the conversion clock is asynchronous with the input analog signal. However, there is a problem that the control noise is generated due to a situation in which the adjustment is repeated.

The present invention has been made in view of the problems of the above-described conventional technique, and the timings of sampling value output and analog-digital signal conversion are always maintained without degrading the decoding accuracy. An object is to provide an analog-digital conversion circuit that can be matched.

[0026]

In order to achieve the above object, the present invention is a sample-and-hold method for sampling an input analog signal and sequentially holding and outputting the sampled value at the timing of a control signal arbitrarily input. In an analog-digital conversion circuit comprising a circuit and an analog-digital converter that converts a value output from the sample-and-hold circuit into a digital value using a conversion clock, the conversion clock is converted into a control signal of the control signal. It is characterized in that it has a clock generation means that is generated in synchronization with the phase.

Further, the clock generating means is a PLL circuit which controls the phase of the conversion clock based on the phase difference between the generated conversion clock and the control signal.

(Operation) In the present invention configured as described above, since the conversion clock of the analog-digital converter is generated in synchronization with the timing of the control signal, control of sample-and-hold and analog-digital conversion. Since the conversion operations of the converters are synchronized and the ringing generated when switching the sample and hold always shows the same value for the same change, it does not appear as noise in the converted digital value.

Further, since the conversion clock is synchronized with the control signal, the phase of the conversion clock follows when the timing of the control signal is adjusted, so that the timing can be finely adjusted and the adjustment is not repeated periodically.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the analog-digital conversion circuit of the present invention.

In the present embodiment, as shown in FIG. 1, a sample-and-hold circuit 1 for sampling an input analog signal and sequentially holding and outputting the sampled value at the timing of a control signal from the outside, and a sample-and-hold circuit 1. The analog-digital converter 2 for converting the value output from the converter into a digital signal in synchronization with an external control signal, and the conversion clock for executing the signal conversion operation in the analog-digital converter 2 are the phases of the control signal. PLL that is a clock generation means that is generated in synchronization with
And a circuit 7. In the PLL circuit 7, a voltage-controlled oscillator 3 that generates and outputs a conversion clock for executing the signal conversion operation in the analog-digital converter 2, and a frequency divider 4 that divides the conversion clock.
A phase comparator 5 that detects the phase difference between the converted clock and the control signal, and a low-pass filter 6 that limits the band of the phase difference detected by the phase comparator 5 are provided.

The operation of the analog-digital conversion circuit configured as described above will be described below.

First, when an analog signal is input to the analog-digital conversion circuit, the sample-and-hold circuit 1 samples the voltage value of the analog signal, and every time a control signal is input from the outside, the sampled value is sampled. Is held and output, and the sampling value is updated.

Then, in the analog-digital converter 2, the conversion of the voltage value held and output into the digital value is started at the timing of the control signal from the outside.

Here, the conversion operation of the voltage value into the digital value is performed stepwise by the conversion clock supplied from the voltage controlled oscillator 3.

Up to this point, the basic operation is as usual.

The conversion clock is output from the voltage controlled oscillator 3 and supplied to the analog-digital converter 2, divided by the frequency divider 4 and supplied to the phase comparator 5 for comparison with the phase of the control signal. To be done.

When the phase difference is detected by the phase comparator 5, the detected phase difference is supplied to the voltage controlled oscillator 3 after the high frequency component which becomes a noise component is cut off by the low pass filter 6.

Then, in the voltage controlled oscillator 3, a new conversion clock is newly generated based on the supplied phase difference and is output.

By the series of feedback operations as described above, the conversion clock output from the voltage controlled oscillator 3 becomes synchronized with the phase of the control signal.

In this embodiment, the PLL circuit is applied as the phase synchronizing circuit, but any circuit that synchronizes the phase of the converted clock with the phase of the control signal as described above may be applied as the clock generating means. May be.

[0043]

Since the present invention is constructed as described above, it has the following effects.

According to a first aspect of the present invention, there is provided a phase locked loop circuit for generating a conversion clock for signal conversion, which is synchronized with the timing when a control signal is input to the sample and hold circuit. Since it is provided, the timing at which the control signal is input to the sample-and-hold circuit and the timing at which the control signal is input to the analog-to-digital conversion circuit do not deviate, and as a result, the sampling value does not decrease in decoding accuracy. It is possible to always match the timings of the output and the analog-digital signal conversion.

According to the second aspect of the invention, since the PLL circuit is applied to the phase locked loop circuit to perform the feedback operation, the phase difference between the conversion clock and the control signal is reduced,
More accurate phase synchronization can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an analog-digital conversion circuit of the present invention.

FIG. 2 is a block diagram showing a configuration example of a conventional analog-digital conversion circuit.

FIG. 3 is a block diagram showing a configuration example of a conventional analog-digital conversion circuit including a flip-flop.

[Explanation of symbols]

 1 sample and hold circuit 2 analog-digital converter 3 voltage controlled oscillator 4 frequency divider 5 phase comparator 6 low-pass filter 7 PLL circuit

Claims (2)

[Claims] 1. A sample-and-hold circuit that samples an input analog signal and sequentially holds and outputs the sampled value at the timing of a control signal that is input, and a value output from the sample-and-hold circuit. An analog-digital conversion circuit comprising an analog-digital converter for converting a digital value using a clock, comprising a clock generation means for generating the conversion clock in synchronization with the phase of the control signal. An analog-digital conversion circuit. 2. The analog-digital conversion circuit according to claim 1, wherein the clock generation means controls a phase of the conversion clock based on a phase difference between the generated conversion clock and the control signal. An analog-to-digital conversion circuit characterized by: