JPS6332297B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improving the S/N of a decoder and/or encoder (hereinafter referred to as a codec) having a filter having a sampling function. FIG. 1 is a block diagram showing the basic structure of the codec. In FIG. 1, when an input PCM signal 1 is input to a decoder 3 in synchronization with a read clock signal 2, the decoder 3 performs digital-to-analog conversion, and the output is applied to a filter 4. Filter 4 is a switched capacitor filter (hereinafter referred to as filter 4) that has a sample function.
SCF) is used. An output analog signal 5 from which high frequency components are removed by a filter 4 is obtained. In this case, the decoder 3 and the filter 4 are controlled by the control unit 6.
It is controlled by timing control signals 7 and 8 from. The internal clock signal 9 supplied to the control section 6 is obtained by applying a synchronous clock signal 10 to the PLL circuit 20.

Analog-to-digital conversion to obtain the output PCM signal 11 from the input analog signal 5' can be performed by the reverse operation as described above. That is, the input analog signal 5' passes through the filter 4' and is sent to the encoder 1.
2 is input. An output PCM signal 11 is obtained from the encoder 12 in synchronization with the readout clock signal 2. In this case, as in the case of digital-to-analog conversion, the control section 6 outputs the timing control signal 1.
3 and 14 control the encoder 12 and filter 4'. PLL circuit 2 used in Figure 1
The configuration of 0 is shown in FIG. The phase comparator 21 compares the frequency of the synchronous clock signal 10 and the frequency of the output signal 23 of the frequency divider 22 and outputs the voltage controlled oscillator 24.
(VCO). The frequency of the internal clock signal 9, which is the output of the VCO, is determined by the division ratio of the frequency divider 22. If the frequency division ratio is n, the frequency of the internal clock signal 9 will be n times the frequency of the synchronous clock signal 10.

Conventionally, in audio processing codecs, the frequency division ratio of the PLL circuit 20 is set to 16 or 32 for the frequency of the synchronized clock signal 10 of 8 kHz, and the frequency of the internal clock signal 9 is set to 128 kHz or 256 KHz. The frequency is 1544kHz or
2048kHz was often used. In such a configuration, if an SCF or the like having a filter and sampling function is used, the sampling pulses of the control signals 8 and 14 supplied from the control unit 6 to the filters 4 and 4' may overlap with the pulses of the readout clock signal 2. When this happens, the S/N ratio deteriorates. That is, the internal clock signal 9 obtained through the PLL circuit 20 is often accompanied by jitter, and as described above, the internal clock signal 9 is applied to the filters 4 and 4' via the control section 6. This is because, if the pulses of the read clock signal 2 overlap with each other, a passing noise will be generated. Here, the passing noise will be explained.

FIG. 3 is a waveform diagram for explaining the passing noise, where 31 is the sampling clock, 32 is the noise synchronized with the sampling clock 31, 33 is the noise in which the phase of the noise 32 fluctuates, and 34 is the noise 33.
Noise whose sampling point is shifted from the peak of 3.
5 and 36 are sampling points, and 37 and 38 are sample and hold waveforms.

Now, if noise 32 enters the circuit sampling with sampling clock 31, a sample-and-hold waveform 37 will be generated, but it will not become noise because of the DC component. However, in the case of noise whose phase changes with the sampling point, such as the noise 33, alternating current component noise, such as the sample-and-hold waveform 38, is generated. The noise below the sampling frequency that is generated due to the sampling point and the noise passing each other in this way is called passing noise.

In order to reduce this passing noise, it is possible to make the noise completely synchronized like the noise 32, or to shift the timing of the noise like the noise 34.

Now, if the frequency division ratio of the PLL circuit 20 is set to 16, the internal clock signal 9 will be 128kHz, so if the readout clock signal 2 is 1544kHz, the two signals will overlap because they are not in a multiple relationship. Since the probability is low, there is no need to consider S/N deterioration due to passing noise, but if readout clock signal 2 is 2048kHz, internal clock signal 9
Because it is a multiple of 128kHz, both signals always overlap, resulting in significant S/N deterioration. It is undesirable that the S/N characteristic deteriorates depending on the frequency relationship between the internal clock signal and the readout clock signal in this way.

In order to eliminate this drawback, the present invention selects the internal clock frequency so that the frequencies of the internal clock signal and the read clock signal are not in a multiple relationship, and will be described in detail below. In FIG. 1, when the frequency of the synchronous clock signal 10 is 8kHz and the readout clock frequency is 2048kHz, the frequency divider 22 of the PLL circuit 20 in FIG.
If the frequency division ratio is selected to be 17, the frequency of the internal clock signal 9 will be 136kHz. In this way, since the two signals are not in a multiple relationship, the overlap of the signals is greatly reduced, and the S/N deterioration due to the passing noise is also reduced to a small extent. Generally, in audio processing codecs, the frequency of the synchronous clock signal 10 is selected to be 8kHz, so depending on the frequency of the readout clock signal 2,
By simply selecting the frequency division ratio of the frequency divider 22 in the PLL circuit 20, it is possible to obtain an internal clock signal 9 that reduces generation of cross noise.

In the above explanation, the internal clock signal and
We have described the case of obtaining a frequency relationship between the clock signals that does not degrade the S/N for a codec that has two types of clock signals, the read clock signal. A similar effect can be achieved by selecting frequencies so that there is no relationship. This invention has the excellent effect of significantly reducing S/N deterioration in analog-to-digital or digital-to-analog conversion simply by changing the frequency division ratio of the frequency divider in the PLL circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the codec, FIG. 2 is an internal configuration diagram of the PLL circuit shown in FIG. 1, and FIG. 3 is a waveform diagram for explaining the passing noise. 1...Input PCM signal, 2...Reading clock signal, 3...Decoder, 4, 4'...Filter,
5... Output analog signal, 5'... Input analog signal, 6... Control section, 7, 8, 13, 14... Control signal, 9... Internal clock signal, 10... Synchronous clock signal, 11... Output PCM signal, 12...
...encoder, 22...frequency divider.

Claims (1)

[Scope of Claims] 1. A first input terminal to which a read clock signal is input; a filter to which an input analog signal is input; and an output of the filter to which the output of the filter is input, and outputs a PCM signal in synchronization with the read clock signal. a second input terminal into which a synchronous clock signal is input; and a frequency divider having a specific frequency division ratio, and converts the synchronous clock signal input by the frequency divider into the readout clock signal. an encoder comprising a PLL circuit that outputs an internal clock signal having a frequency that is not a multiple of the frequency of the encoder; and a control section to which this internal clock signal is input and supplies a timing control signal to the encoder and filter. .