JPH0363249B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a loop filter used in a PLL circuit, and particularly to a loop filter that is suitable for integration into an integrated circuit due to its structure.

FIG. 1 is a block diagram showing the basic configuration of a PLL circuit. The signal (pulse signal) input to the input terminal 101 and the output signal of the frequency divider 102 are input to a frequency phase comparator 103, and the phases or frequencies of both signals are compared. Frequency phase comparator 10
3 outputs a difference signal (PU or PD) between both signals.
This difference signal is integrated by a loop filter 104,
applied to voltage controlled oscillator 105. As a result,
An output signal having an oscillation frequency corresponding to the output of the loop filter 104 is obtained at the output terminal 106 of the voltage controlled oscillator 105. This output signal is divided by frequency divider 1
02 to the input of the frequency phase comparator 103. Therefore, if the frequency division ratio of the frequency divider 102 is N (N is a positive integer) and the frequency of the input signal is _i , the frequency of the output signal is
N _i .

This operation is repeated until the frequency phase comparator 103 no longer outputs the difference signal, and when the difference signal is no longer output, the input signal and the output signal of the frequency divider 102 are synchronized in frequency and phase.

The frequency phase comparator 103 is a so-called digital phase comparator that compares only the edges (rising or falling) of pulses, and the voltage controlled oscillator is a voltage controlled multivibrator (hereinafter referred to as VCM) that directly outputs the pulse waveform. ) is usually used.

Further, as the loop filter, a C-MOS type integrated circuit loop filter as shown in FIG. 2 is used.

Next, the loop filter shown in FIG. 2 will be explained. A difference signal and PD from the frequency phase comparator 103 shown in FIG. 1 are input to input terminals 201 and 202, respectively. (denotes the inverted output of PU.) This loop filter has a transfer function equivalent to a fully integral quadratic loop filter. The bias circuit 203 is a stable voltage source, and a current corresponding to the voltage value flows through the transistors M1, M2, and M3. The difference signal PD is a pulse signal, and the transistors M4 and M8 or M7 and M9 are turned on and off by this signal. Transistor M8
is a switch for charging the capacitor 205, and the transistor M9 is a switch for charging the capacitor 205.
This is a switch for discharging the charge from the
It works to speed up the tracking of the loop filter output. When the difference signal PU or PD is +V (v),
Transistor M4, M8 or transistor M7,
M9 turns on. Transistors M5 and M6 constitute a current mirror circuit with respect to transistors M1 and M3, respectively, and a current corresponding to the mirror ratio flows through transistors M5 and M6 when transistors M4 and M7 are turned on.

The level conversion circuit 204 is a circuit that converts the level of the input signal in order to turn on and off the transistor M9 connected to the negative power supply (-V) according to the level of the difference signal PD.

FIG. 3 is a waveform diagram showing waveforms of various parts of the loop filter for explaining the synchronization pull-in process. Here, to simplify the explanation, the capacitor 205
It is assumed that the initial terminal voltage of is O(V) and that the VCM 105 is free-running oscillating at a frequency lower than the input signal frequency. In addition, VCM105 is
It is assumed that as the loop filter output increases, the oscillation frequency follows. FIG. 3a shows the input signal, and FIGS. 3b and 3c show the difference signal, PD, which is the output of the frequency phase comparator 103, respectively.
Figure 3d shows the terminal voltage of capacitor 205, Figure 3e
The figure shows the waveform of the output voltage of the loop filter output terminal 206.

When the voltage generated between the terminals of the capacitor 205 due to charging and discharging of the capacitor 205 is V _C , V _C =I·t/C (1) Equation (1) holds true. Here I is the transistor M5
or the constant current value flowing through M6, t is the transistor M
4 or the time that M7 is on, C is the capacitance of the capacitor 205. Voltage generated between this terminal
Figure 3d shows the change in V _C over time.

In FIG. 3e, the rising voltage or falling voltage of the output voltage of the loop filter output terminal 206 is shown as V _S , and this V _S is: V _S =R ₁ /R ₁ +R ₂ ·V (2) ( 2) It is expressed as Eq. Here, R ₁ and R ₂ are the resistance values shown in Figure 2, and V is the transistor M8.
and the voltage of the voltage source connected to the source of M9.

When the PLL locks in synchronization, in an ideal system, the output difference signal of the frequency phase comparator 103
PU and PD will no longer occur.

However, in the system actually used, the detection sensitivity of the frequency phase comparator, the characteristics of the loop filter, the sensitivity of the VCM, etc. are finite values, so
An error occurs in the PLL loop. Furthermore, errors due to noise also occur. When such an error occurs, the output difference signal PU of the frequency phase comparator 103
Or manifested as PD.

Since the PU or PD signal generated by the error at this time is usually a thin pulse, the integrating capacitor 2
05 is I・Δt/C (Δt is the time indicating the pulse width)
However, when the transistor M8 or M9 turns on, a pulse of R ₁ /R ₁ +R ₂ V is generated at the loop filter output terminal 206. Since this pulse component is directly input to the subsequent VCM 105, this pulse component is eventually superimposed on the output of the VCM 105. FIGS. 4a to 4f are waveform diagrams showing various waveforms appearing in the loop filter and VCM due to error pulses. Figure 4a shows the input signal, Figures 4b and 4c
The figures show the difference signal and PD which are the outputs of the frequency phase comparator 103, Fig. 4d shows the loop filter output voltage signal, Fig. 4e shows the charge/discharge waveform of the VCM 105, and Fig. 4f shows the VCM output signal. . The waveforms shown by dotted lines in Figures 4e and 4f are as follows:
This is the waveform when there are no error pulses in the PU and PD signals.

As is clear from FIGS. 4e and 4f, it can be seen that jitter occurs in the VCM output signal due to the error pulse.

SUMMARY OF THE INVENTION An object of the present invention is to provide a PLL loop filter that is improved so that the PLL output is free from jitter due to errors and noise within the loop.

In order to achieve the above object, the present invention includes an integrating capacitor, a charging current source connected to one end of the capacitor for charging the capacitor, and one end of the capacitor.
a discharge current source connected to the end for discharging charge from the capacitor;
a rising voltage source that is connected to the other end of the capacitor and raises the terminal potential of the capacitor by a certain value; and a falling voltage source that is connected to the other end of the capacitor and lowers the terminal potential of the capacitor by a certain value. A loop filter for a PLL which obtains an output by switching the charging current source, the discharging current source, and the rising voltage source and falling voltage source by an output signal of a frequency phase comparator, A pulse removal circuit is provided between the frequency phase comparator and the voltage source for increasing and/or between the frequency phase comparator and the voltage source for decreasing, which prevents a pulse signal of a certain width or less from passing through. characterized by things. The present invention will be described in detail below based on examples.

FIG. 5 is a circuit diagram showing an embodiment of the present invention.
Note that the same parts shown in FIG. 2 are denoted by the same reference numerals, and the explanation thereof will be omitted.

Pulse erasing circuits 507 and 5 are added to the conventional circuit shown in FIG.
Figure 5 is the result with 08 inserted. Next, the operation of the embodiment shown in FIG. 5 will be explained.

When the PLL is synchronously pulled in, the pulse canceling circuits 507 and 508 hardly affect the characteristics of the loop filter, and operate as described in the conventional circuit. This is the pulse erasing circuit 50
This is because 7,508 has a function of erasing only narrow pulse signals, and has no effect on wide PU and PD signals that occur during synchronization pull-in. The configuration of the pulse erasing circuit having such a function will be described in detail later. When the PLL synchronous pull-in is completed (steady state),
For the PU or PD signal, which is a thin pulse generated by an error or noise in the PLL, the pulse canceling circuits 507 and 508 cancel the pulse that causes switching of transistor M8 or M9, so the loop filter Output terminal 2
The voltage change ΔV _C appearing in 06 is only that expressed by the equation (3): ΔV _C =I/C·Δt (3).

In this way, due to the function of the pulse cancellation circuit,
Since the PU or PD signal generated by errors or noise in the PLL occurring in the steady state of the PLL does not appear directly at the loop filter output, the output of the subsequent VCM 105 also becomes a stable signal. 6th
The figure is a circuit diagram showing an example of pulse erasing circuits 507 and 508.

Consisted of transistors M10 and M11
CMOS type inverter and transistor M12
and an inverter of the same CMOS type made up of M13 are connected in cascade, and an integrating capacitor C _d is inserted at the connection point. When the input pulse to the input terminal 601 is negative, the conductance of the transistor M10 is changed to the transistor M
Even if the capacitance value of capacitor C _d is small, if it is selected so that it is smaller than the conductance of 11,
Pulse erasure can be performed. Figure 7a shows the input terminal 60.
Figure 7b is a waveform diagram showing changes in the voltage between the terminals of the capacitor _Cd .

As shown in FIG. 7b, transistors M12, M
If the threshold value V _T of the inverter according to No. 13 is set to be greater than the maximum value of the voltage between the terminals of _C
Although the inverter using transistors M12 and M13 does not operate for narrow pulses due to errors or noise, it operates for wide normal PD or PU signals, so unnecessary pulses can be effectively rejected. I can do it.

Further, when the input pulse to the input terminal 601 is a positive pulse, the same effect as described above can be obtained by selecting the conductance of the transistor M11 to be smaller than the conductance of the transistor M10. As explained above, in this embodiment, the PU with a narrow width or
A pulse canceling circuit that operates only on the PD signal is placed in the loop filter to remove this signal, making it possible to remove negative effects such as jitter on the PLL output.

In the above embodiment, the pulse cancellation circuit is
a path through which the PU signal is applied to transistor M8;
We have explained the case where the PD signal is inserted into both paths that are applied to transistor M9, but if there are almost no errors or narrow pulses due to noise in either signal, it is necessary to insert a pulse cancellation circuit in that path. May be removed. It goes without saying that the configuration of the pulse erasing circuit is not limited to the circuit shown in FIG. 6, but can be realized by any circuit having the same function as appropriate.

According to the present invention, since a pulse canceling circuit is provided to remove unnecessary pulses in the steady state of the PLL, a stable PLL output can be obtained. Also,
It is convenient to configure the pulse cancellation circuit with a CMOS circuit because the entire loop filter can be integrated.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the basic configuration of a PLL circuit, Figure 2 is a circuit diagram of a conventional C-MOS type loop filter, and Figures 3a to 3e are diagrams of each part of the loop filter to explain the synchronization pull-in process. Figures 4a to 4f are waveform diagrams showing various waveforms appearing in the loop filter and VCM due to error pulses. Figure 5 is a circuit diagram showing one embodiment of the present invention. Figure 6 FIG. 7a is a circuit diagram showing one example of a pulse erasing circuit used in the present invention;
FIG. 7b shows a waveform diagram within the pulse cancellation circuit. 205... Integrating capacitor, 507, 508
...Pulse erasure circuit.

Claims (1)

[Scope of Claims] 1. An integrating capacitor, a charging current source connected to one end of the capacitor for charging charge to the capacitor, and a charging current source connected to one end of the capacitor for charging charge from the capacitor. a discharge current source for discharging; a rising voltage source connected to the other end of the capacitor to increase the terminal potential of the capacitor by a certain value; and a voltage source connected to the other end of the capacitor to increase the terminal potential of the capacitor. a voltage drop source that lowers the voltage by a certain value, and a frequency phase comparator; In a PLL loop filter that obtains an output by switching according to an output signal, a constant width is provided between at least the frequency phase comparator and the rising voltage source or between the frequency phase comparator and the falling voltage source. A loop filter for PLL, characterized in that it is equipped with a pulse erasure circuit that prevents the following pulse signals from passing through.