JPS58134531A - Loop filter for pll - Google Patents

Abstract

PURPOSE:To stabilize the output signal of a voltage-controlled oscillator by providing a pulse eliminating circuit to the output terminal of a voltage source for controlling the charging and discharging of a capacitor for integration in a loop filter. CONSTITUTION:To terminals 201 and 202 of the loop filter, difference signals from a phase comparator are supplied. If pulses are mixed with the difference signals, pulse eliminating circuits 507 and 508 detect those pulses to turn on a transistor (TR) M8 or M9. From the other terminal of the capacitor 205 for integration constituting the loop filter to the output terminal 206 of the loop filter, a voltage for eliminating appearing pulses is applied. At the output terminal of the loop filter, no influence of a pulse noise appears, so the PLL circuit oscillates stably and continuously.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a loop filter used in a PLL circuit, and relates to a loop filter that is suitable for integration into an integrated circuit due to its structure.

FIG. 1 is a diagram showing the basic configuration of a PLL circuit. The signal input to the input terminal 101 (base pulse signal) and the output signal of the frequency divider 102 are connected to the frequency phase comparator 103.
and the phases or frequencies of both signals are compared.

The frequency phase comparator 103 detects the difference signal (PU or I
'D) is output. This difference signal is passed through the loop filter 104
is integrated by the voltage controlled oscillator 105. As a result, an output signal having an oscillation frequency corresponding to the output of the loop filter 104 is transmitted to the output terminal i of the voltage controlled oscillator 105.
Obtained in oq. This output signal is fed back to the input of a frequency phase comparator 103 via a frequency divider 102. Therefore, the frequency division ratio of the divider 102 is set to N
(N is a positive integer), and if the frequency of the input signal is f, then
The frequency of the output signal is Nfi.

This operation is repeated until the frequency phase comparator 103 no longer outputs the difference signal, and when the difference signal is no longer output, the input signal and the output signal of the frequency divider 102 have a frequency of 2.
Phases are synchronized.

The frequency phase comparator 103 is a so-called digital phase comparator that compares only the edge (rising or falling edge) of the pulse, and the voltage controlled oscillator is a voltage controlled multivibrator (hereinafter referred to as "voltage controlled multivibrator") that directly outputs the Noculus waveform. VCM
) is usually used.

In addition, the loop filter has a C-M as shown in Fig. 2.
An OS-type integrated circuit loop filter is used.

Next, the loop filter shown in Fig. 2 will be explained.The input terminals 2011 and 202 have the first
The difference from the frequency phase comparators 7 and 8 shown in the figure)'' indicates the transferred output.) This loop filter has a transfer function equivalent to a fully integral quadratic loop filter. A current corresponding to the voltage value of the voltage source flows through the transistors M1, M2, and M3.

The difference signals PU and PD are /IP pulse signals, and this signal causes the transistors M4. M8 or M7, M9 is on.

It's supposed to turn off. Difference signal PU or PD is +V
(v), transistor M4. M8 or transistor M7. M9 turns on. Transistor M5t
M6 constitutes a current mirror circuit with respect to the transistors M1 and M3, respectively, and a current corresponding to the mirror ratio is transmitted to the transistors M4. When M7 is turned on, transistor M5. Flows to M6.

The level conversion circuit 204 is a circuit 1 that converts the level of the input signal in order to turn on/off the transistor M9 connected to the negative power supply (-■) according to the level of the difference signal PD.

:'l FIG. 3 is a waveform diagram showing the □'□:l waveforms of each part of the loop filter for explaining the □' period pull-in process.

Here, to simplify the explanation, it is assumed that the initial terminal voltage of the capacitor 205 is 0 (V) and that the 70M 105 is free-running oscillating at a frequency lower than the input signal frequency. Further, it is assumed that the VCM 105 tracks the oscillation frequency to become higher as the loop filter output becomes higher. 3(a) shows the input signal, FIGS. 3(b) and 3(C) show the difference signals PU and PD which are the outputs of the frequency phase comparator 103, and FIG. 3(d) shows the capacitor 20.
Figure 3(e) shows the waveform of the output voltage at the loop filter output terminal 206.

If the voltage generated between the terminals of the capacitor 205 due to charging and discharging of the capacitor 205 is vc, then V=I-t/C
...(1) Equation (1) holds true. Here, ■ is the constant current value flowing through the transistor M5 or M6, and t is the value of the constant current flowing through the transistor M4 or M7.
C is the capacitance of the capacitor 205 during the time that the capacitor 205 is on. FIG. 3(d) shows the change over time of the voltage (2) generated between the terminals.

g 3 (e) In the figure, the loop filter output terminal 206
The rising or falling voltage of the output voltage is shown as V, and this V is expressed as in equation (2). Here, R1+R2 is the resistance value shown in FIG. 2, and ■ is the transistor M8 and M9.
is the voltage of the voltage source connected to the source of .

- When the PLL pulls in synchronization, in an ideal system, the output difference signals PU, PD of the frequency phase comparator 103
will no longer occur.

However, in a system that is actually used, the detection sensitivity of the frequency phase comparator, the characteristics of the loop filter, the sensitivity of the VCM, etc. have finite values, so errors occur in the PLL Luso. Furthermore, errors due to noise also occur. When such an error occurs, the output difference signal PU or PD of the frequency phase comparator 103 and the PU generated by the error at this time
Or, since the PD signal is usually a thin pulse, the integrating capacitor 205! Although only a voltage change of Δt/C (Δt is the time indicating f pulse width) is applied, the transistor M8 or M9 is turned on at the loop filter output terminal 206. Since this /4' pulse component is directly input to the subsequent VCM 105, this pulse component is eventually superimposed on the output of the VCM 105. Figures 4(a) to 4(f)
The figure shows the loop filter and VCM due to error and Cruz.
FIG.

FIG. 4(1) shows the input signal, FIG. 4(b) and FIG. 4(C) show the difference signals PU and PD which are the outputs of the frequency phase comparator 103, respectively, and FIG. 4(d) shows the loop filter output. The voltage signal, FIG. 4(e) shows the charge/discharge waveform of VCM J 05, and FIG. 4(f) shows the VCM output signal. Fourth
The waveforms indicated by dotted lines in Figures (e) and 4(f) are PU
, PD scratch signal error pa/l/ , 7! As is clear from FIGS. 4(e) and 4(f), jitter occurs in the VCM output signal due to the error pulse. 1 The object of the present invention is to provide an improved PLL output so that the PLL output does not have jitter7 due to errors and noise in the loop.
To provide a loop filter for LL.

In the present invention, in order to achieve the above object.

an integrating capacitor, a charging current source connected to one end of the capacitor for charging the capacitor, a discharging current source for discharging the charge from the capacitor, and a charging current source connected to the other end of the capacitor. A rising voltage source that is connected to raise the terminal potential of the capacitor by a certain value, and a falling voltage source that lowers the terminal potential of the capacitor by a certain value, the current source for charging and discharging, and the voltage source for rising and falling. PL that obtains the output by switching between and by the output signal of the frequency phase comparator.
In the L loop filter.

- A pulse signal of a certain width or less cannot pass between the frequency phase comparator and the voltage source for increasing and/or between the frequency phase comparator and the voltage source for decreasing. It is characterized by being equipped with a 1 pulse removal circuit. The present invention will be described in detail below based on examples. : FIG. 5 is a circuit diagram showing an embodiment of the present invention.

Note that the same parts shown in FIG. 2 are designated by the same reference numerals.

The explanation will be omitted.

FIG. 5 shows the conventional circuit shown in FIG. 2 with ie pulse erasing circuits 507 and 508 inserted therein. Next, the operation of the embodiment shown in FIG. 5 will be explained.

When the PLL is synchronously pulled in, the pulse erasing circuit 50
7.5013 has almost no effect on the characteristics of the loop filter, and operates as described in the conventional circuit. This is because the Cruz elimination circuits 507 and 508 have narrow widths.
This is because it has the function of erasing only the damage signal, and has no effect on the wide PU and PD damage signals that occur during synchronization pull-in. The configuration of the pulse erasing circuit having such a function will be described in detail later. PLL
When the synchronization pull-in is completed (steady state), the pulse elimination circuit 507 is used to deal with the PU or PD flaw signal, which is a thin or slight pulse that often occurs due to errors or noise in the PLL.
．． 508 eliminates the voltage change Δ■ appearing at the loop filter output terminal 206 because the IE pulse that causes the switching of transistor M8 or M9 is eliminated.

teeth.

Only those expressed by equation (3) are available.

In this way, due to the function of the Jars elimination circuit,) PLL
PU or PD flaws, which often occur due to errors or noise in the PLL that occur in the steady state, do not appear directly on the loop filter output, so the subsequent VCM J6s
The output of is also a stable signal. FIG. 6 is a circuit diagram showing an example of the virus erasing circuits 507 and 508.

0MO8 composed of transistors MIO and Mll
An inverter of the same type (0MO8 type) configured with transistors M12 and M2S is connected in cascade, and an integrating capacitor C6 is inserted at the connection point. If the conductance of the transistor MIO is selected to be smaller than the co/conductance of the transistor Mll, Noculus cancellation can be achieved even if the capacitance value of the capacitor C4 is small. 7(a) is a two-pulse waveform diagram input to the input terminal 601, and FIG. 7(b) is a waveform diagram showing changes in the voltage between the terminals of the capacitor C4.

As shown in FIG. 7(b), transistors M12°M13
If the threshold value vT of the inverter is set to be greater than or equal to the maximum value of the voltage between the CD terminals, errors and noise can be reduced.
Transistor M12. M
Although the inverter based on 13 does not operate, it operates for normal PD or PU multiplied signals having a wide width, so that unnecessary signals can be effectively rejected.

Further, when the Noculus input to the input terminal 601 is a positive Noculus, the same effect as described above can be obtained by selecting the conductance of the transistor Mll to be smaller than the conductance of the transistor MIO. As explained above, in this embodiment, the f. Since this signal is removed, it is possible to remove adverse effects such as jitter on the PLL output.

In the above-mentioned embodiment, the case where the Cruz cancellation circuit was inserted into both the path applied to the PU double signal transistor M8 and the path applied to the PD double signal transistor M9 was explained. If there are almost no errors or narrow traces due to noise,
The mother pulse cancellation circuit for that route may be removed. It goes without saying that the configuration of the pulse removal circuit is not limited to the circuit shown in FIG. 6, but can be realized by any circuit having the same function as appropriate.

According to the present invention, since the present invention is equipped with a pulse canceling circuit that removes unnecessary pulses in the steady state of the PLL, stable PL
L output can be obtained. In addition, the pulse cancellation circuit is
If it is configured with a MOS circuit, it is convenient because the entire loop filter can be integrated. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of a PLL circuit. Figure 2 is a circuit diagram of a conventional C-MO8 type loop filter.
3(a) to 3(e) are waveform diagrams showing the waveforms of each part of the loop filter to explain the synchronization pull-in process.
Figures (a) to 4(f) are waveform diagrams showing various waveforms appearing in the loop filter and VCM due to errors and base pulses, Figure 5 is a circuit diagram showing one embodiment of the present invention, and Figure 6 is FIGS. 7(a) and 7(b), which are circuit diagrams showing one example of the pulse erasing circuit used in the present invention, show waveform diagrams in the pulse erasing circuit. 205... Integrating capacitor, 507.508...
Pulse cancellation circuit. Patent Applicant Oki Electric Industry Co., Ltd. Nippon Telegraph and Telephone Public Corporation Procedural Amendment (Voluntary) 57.4 Noah Showa Year 1998 Director General of the Japanese Patent Office 1. Indication of the Case 1988 Patent Application No. 015469 2. Title of Invention Luso Filter for PLL 3. Relationship with the case of the person making the amendment Patent application office (
Address (105) 1-7-12-4 Toranomon, Minato-ku, Tokyo (1 other person) Address (105)
Torinokl, 1-7-12, Toranomon, Minato-ku, Tokyo [
- circuit”.

Claims (1)

[Scope of Claims] An integrating capacitor, a charging current source connected to one end of the # marked capacitor for charging the capacitor, and a discharging current source for discharging the charge from the capacitor. , a rising voltage source that is connected to the other end of the capacitor and raises the terminal potential of the capacitor by a certain value, and a falling voltage source that lowers the terminal potential of the capacitor by a certain value, and includes a current source for charging and discharging. The output is obtained by switching the rising and falling voltage sources by the output signal of the frequency phase comparator.
In a loop filter for LL. between the frequency phase comparator and the rising voltage source or/
And between the frequency phase comparator and the falling voltage source, there is a gap of less than a certain width. Make it impossible to pass through the Luz signal/4
' A PLL loop filter characterized by being provided with a pulse removal circuit.