JPH04343524A - Pll circuit - Google Patents

Abstract

PURPOSE:To allow a VCO to generate clocks with frequency of wide range without extending the high frequency characteristics of a loop filter. CONSTITUTION:A phase detecting circuit 21 detects the phases of a data clock signal and a clock outputted from the VCO 25 and a formation circuit 22 forms control voltage corresponding to their phase difference. The control voltage is supplied to the VCO 25 through a loop filter 23 and an adder 24. On the other hand, control voltage corresponding to a frequency error between the data input signal and the clock is outputted from a frequency detecting circuit 26 and supplied to the VCO 2 through the adder 24.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit suitable for use in extracting a clock for reproducing PCM audio data, such as in an R-DAT (rotating head type digital audio tape recorder).

0002

2. Description of the Related Art For example, in order to read digital audio data in an R-DAT, it is necessary to extract a clock component from reproduced data. For example, as shown in FIG.
Extracted by L circuit. The phase comparator 1 compares the phases of the input reproduced data and the clock output from the VCO 3, and outputs the phase error. After this phase error is compensated to a predetermined frequency characteristic by the loop filter 2, it is supplied to the VCO 3 as a control voltage. VCO3 is
A clock having a frequency and phase corresponding to the control voltage inputted from the loop filter 2 is generated. In this way, the clock corresponding to the reproduced data is extracted.

The loop filter 2 is composed of an operational amplifier 11, resistors 13 and 14, and a capacitor 12, as shown in FIG. 10, for example. Assuming that the values of the resistors 13 and 14 are R1 and R2, respectively, and the value of the capacitor 12 is C, the frequency characteristics of the low-pass filter are as shown in FIG. The angular frequency ω of the cutoff point at this time is 1/
(CR2), and the gain A at that time is (R2/R1).

By the way, the oscillation frequency of the VCO 3 changes depending on the temperature. When the oscillation frequency (center frequency) of the VCO 3 changes in accordance with the temperature, the frequency deviation from input reproduction data becomes large. Therefore, VCO3
In order to bring the phase of the input reproduced data into the phase of the input reproduced data, it is necessary to extend the high-pass band of the loop filter 2.

[0005]

[Problem to be Solved by the Invention] In the conventional device, the high-pass band of the loop filter 2 is widened in this way to cope with temperature changes, so that the noise can be passed by the widening of the pass band. Bandwidth also expanded, and eventually VCO
There was a problem in that the jitter of the clock output from 3 increased.

The present invention has been made in view of the above situation, and it is an object of the present invention to make it possible to draw in a wide band of frequencies without increasing the amount of jitter.

[0007]

[Means for Solving the Problems] The PLL circuit of the present invention has the following features:
An oscillation circuit that generates a clock corresponding to a control signal, a phase comparison circuit that detects a phase error between the clock and the input signal, a loop filter that compensates the output of the phase comparison circuit to a predetermined frequency characteristic, and an input signal It is characterized by comprising a frequency comparison circuit that detects a frequency error of the clock, and an addition circuit that adds the output of the loop filter and the output of the frequency comparison circuit to generate a control signal.

[0008]

[Operation] In the PLL circuit configured as described above, a frequency error between the input signal and the clock is detected, and the frequency error is supplied to the oscillation circuit as a control signal without going through a loop filter. Therefore, it is possible to generate a clock that corresponds to input signals with a wide range of frequencies without increasing the high frequency characteristics of the loop filter.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the configuration of an embodiment of a PLL circuit according to the present invention. The phase detection circuit 21 includes a clock output from a voltage controlled oscillator (VCO) 25,
A data input signal is supplied from a circuit not shown. The phase detection circuit 21 detects a phase error between an input signal and a clock, and outputs an up (UP) signal or a down (DOWN) signal in response to the phase error. resistance 31
This up signal or down signal is input as a switching signal to the switch 33 to which the resistor 32 is connected in parallel and the switch 34 to which the resistor 32 is connected in parallel. In this way, the generation circuit 22 having the switches 33 and 34 and the resistors 31 and 32 generates a signal corresponding to the phase error between the data input signal and the clock signal in response to the up signal and down signal output from the phase detection circuit 21. generate. This phase error signal is input to an adder 24 via a loop filter 23.

On the other hand, the phase detection circuit 21 generates a CHG signal in response to the data input signal and the clock signal, and outputs this to the frequency detection circuit 26. Frequency detection circuit 2
6 detects the frequency error between the data input signal and the clock signal from the input CHG signal, and outputs the frequency error signal to the adder 24. The adder 24 adds the output of the loop filter 23 and the output of the frequency detection circuit 26, and outputs the result to the VCO 25 as a control signal.

The phase detection circuit 21 is configured as shown in FIG. 2, for example. In this example, the data input (
REF) signal is latched by the latch circuit 41 using the clock supplied from the VCO 25 as a reference. Also,
The output of the latch circuit 41 is latched by the latch circuit 42 using a clock obtained by inverting the clock (VAR) outputted by the VCO 25 by an inverter 43 . The exclusive OR circuit 44 calculates the exclusive OR of the data input signal and the output of the latch circuit 41, and outputs this as a CHG signal (i signal). In addition, exclusive OR circuit 4
5 calculates the exclusive OR (i signal) of the outputs of the latch circuit 41 and the latch circuit 42.

The outputs of the exclusive OR circuits 44 and 45 are input to a NAND circuit 46, and the output (k signal) of the NAND circuit 46 is input to AND circuits 47 and 48. The outputs of exclusive OR circuits 44 and 45 are supplied to the other inputs of AND circuits 47 and 48, respectively. The output of the AND circuit 47 is output as an up signal, and the output of the AND circuit 48 is output as a down signal to the generation circuit 22.

Further, the frequency detection circuit 26 is configured as shown in FIG. 7, for example.
It is configured as shown in . In this example,
The rising edge (HE) of the CHG signal is detected by the inverter 67 and the AND circuit 69. Further, the falling edge (LE) of the CHG signal is detected by the inverter 68 and the NOR circuit 72. The constant current output from the constant current source 51 is configured to charge a capacitor 55 via a switch 52. The charge stored in the capacitor 55 is transferred to the capacitor 56 via the switch 54 or transferred to the capacitor 56 via the switch 53.
It is designed to be discharged through.

Comparator 57 compares the voltages charged in capacitors 55 and 56, and the comparison result is sent to latch circuit 58.
The output of the latch circuit 58 is further latched by the latch circuit 59. The output of the latch circuit 58 and the output of the latch circuit 59 are input to an AND circuit 60, and the output of the AND circuit 60 is supplied to the positive input terminal of the counter 62. Further, the outputs of the latch circuits 58 and 59 are input to a NOR circuit 61, and the output of the NOR circuit 61 is supplied to a negative input terminal of a counter 62. counter 62
The output of the PWM circuit 63 is supplied to the adder 24 in FIG. 1 via a low-pass filter 66 consisting of a resistor 64 and a capacitor 65.

Next, its operation will be explained. First, the operation of the phase detection circuit 21 shown in FIG. 2 will be described with reference to the timing charts of FIGS. 3 to 5. The latch circuit 41 converts the data input signal REF (FIG. 3(A)) to V
It is latched in synchronization with the rising edge of the clock VAR (FIG. 3(B)) output by the CO25 (FIG. 3(C)). The signal g (FIG. 3(C)) latched by the latch circuit 41 is supplied to the latch circuit 42, and the rising edge of the clock inverted by the inverter 43 (the falling edge of the clock VAR not inverted by the inverter 43) is latched in synchronization with (FIG. 3(D)).

The exclusive OR circuit 44 calculates the exclusive OR of the data input signal (FIG. 3(A)) and the data g latched by the latch circuit 41 (FIG. 3(C)) (FIG. 3(A)). (E)). The output i (FIG. 3(E)) of this exclusive OR circuit 44 is sent to the frequency detection circuit 2 as a CHG signal.
6, and is also supplied to an AND circuit 47 and a NAND circuit 46.

The exclusive OR circuit 45 also connects the output g of the latch circuit 41 (FIG. 3(C)) and the latch circuit 42.
(FIG. 3(F)).

The NAND circuit 46 is an exclusive OR circuit 44
The negative logical product k of the output i (FIG. 3(E)) and the output j (FIG. 3(F)) of the exclusive OR circuit 45 is calculated (FIG. 3(E)).
G)). The AND circuit 47 outputs the output i of the exclusive OR circuit 44 (FIG. 3(E)) and the output k of the NAND circuit 46 (FIG. 3(E)).
G)) and this is used as the up signal (Fig. 3(
H)) is output as a switching signal of the switch 33 of the generation circuit 22.

Furthermore, the AND circuit 48 calculates the logical product of the output j of the exclusive OR circuit 45 (FIG. 3(F)) and the output k of the NAND circuit 46 (FIG. 3(G)), and The down signal (FIG. 3(I)) is output as a switching signal for the switch 34 of the generation circuit 22.

As shown in FIG. 3, the input signal REF (FIG. 3
(A)) and the rising edge of clock VAR (Figure 3 (B)) are out of phase by T/2 (T is the period of clock VAR) (90 degrees of the phase of the lowest frequency signal of the data input signal) If so, the lengths (high level periods) of the up signal (FIG. 3(H)) and down signal (FIG. 3(I)) are equal.

On the other hand, as shown in FIG. 4, the clock VAR (
When the phase of Fig. 4 (B)) advances, the up signal (Fig. 4 (H)
) becomes narrower.

Conversely, data input signal REF (FIG. 5(A)
), the length of the up signal (Figure 5 (H)) becomes longer and the length of the down signal (Figure 5 (I)) becomes shorter. .

The output signal i of the exclusive OR circuit 44 changes from the rising edge of the data input signal REF to the clock VAR.
It corresponds to the period up to the rising edge of . Signal i(C
Considering the width of the HG signal, as shown in Figure 6, the width of the signal i is T/2 when the phase difference is 90 degrees, and 18
When it is 0 degrees, it becomes T. The width changes in direct proportion to the phase difference between 0 degrees and 180 degrees. Furthermore, 18
The angle changes between 0 degrees and 360 degrees in the same way as between 0 degrees and 180 degrees. That is, the width of the signal i (CHG signal) changes like a sawtooth wave with a period of 180 degrees of phase difference.

When the up signal is at a high level, switch 3
3 is turned on. At this time, a predetermined voltage VDD is output to the loop filter 23. When the down signal is at a high level, switch 34 is turned on. At this time, a zero level signal is input to the loop filter 23. When both the up signal and the down signal are at low level, a voltage VD is obtained by dividing a predetermined voltage VDD by two resistors 31 and 32.
D/2 is supplied to loop filter 23. In this way, a voltage corresponding to the phase error between the data input signal REF and the clock signal VAR is input to the loop filter 23. This phase error signal is processed into a predetermined frequency characteristic by a loop filter 23 and then input to an adder 24 .

Next, the operation of the frequency detection circuit 26 shown in FIG. 7 will be explained. The CHG signal is supplied to an AND circuit 69 after its polarity is inverted by an inverter 67 . The inverter 67 outputs the input signal after slightly delaying it for inversion processing. As a result, AND circuit 6
9 outputs a pulse synchronized with the rising edge of the CHG signal. Similarly, since the inverter 68 slightly delays the CHG signal and generates an inverted output, the NOR circuit 70 outputs a pulse synchronized with the falling edge of the CHG signal.

When the CHG signal is at a high level, the switch 52 is turned on and the capacitor 55 is charged by the constant current output from the constant current circuit 51. And CHG
When the signal falls from a high level to a low level, the switch 52 is turned off in synchronization with the falling edge, the switch 54 is turned on, and the charge stored in the capacitor 55 is transferred to the capacitor 56. . after that,
When the CHG signal flips from low level to high level again,
The switch 53 is turned on for a moment in synchronization with the rising edge, and the charge stored in the capacitor 55 is discharged. Since the switch 52 is turned on while the CHG signal is at a high level, the capacitor 55 is charged again by the constant current output from the constant current source 51.

That is, the capacitor 55 is charged with a voltage corresponding to the high level period of the CHG signal, and the capacitor 56 is charged with a voltage corresponding to the immediately preceding high level period of the CHG signal. Become. As a result, by comparing the voltages of capacitors 55 and 56, comparator 57 compares the high level period of the CHG signal with the immediately preceding high level period.

Comparator 57 is at logic 1 when the period of the current CHG signal is longer than the length of the period of the immediately preceding CHG signal.
and outputs logic 0 when it is short. Latch circuit 58
and 59 latch the signal input from the comparator 57 in synchronization with the falling edge of the CHG signal. That is, the latch circuit 58 latches the logic output from the comparator 57 at that time, and the latch circuit 59 latches the data corresponding to the immediately preceding period of the CHG signal output from the latch circuit 58.

If the frequency of the data input signal is higher than the clock frequency, the length of the CHG signal tends to gradually increase. As a result, the output of the comparator 57 continuously outputs logic 1. When the outputs of latch circuits 58 and 59 are both logic 1, AND circuit 60 becomes conductive and logic 1 is input to counter 62.

On the other hand, when the frequency of the data input signal is lower than the frequency of the clock signal, the length of the CHG signal tends to become gradually shorter. the result,
The output of the comparator 57 continuously outputs logic 0. When the outputs of latch circuits 58 and 59 are both logic 0, the output of NOR circuit 61 is logic 1. The output of this NOR circuit 61 is supplied to a negative input terminal of a counter 62.

The counter 62 increments the count value by 1 when a logic 1 is input to the positive input terminal. Further, when a logic 1 is input to the negative input terminal, the count value is counted down by 1. The PWM circuit 63 outputs a pulse having a width corresponding to the count value of the counter 62. The pulse output from this PWM circuit 63 is
The signal is smoothed by a low-pass filter 66 and output to the adder 24 .

That is, when the frequency of the data input signal tends to be higher than that of the clock, the count value of the counter 62 is increased, and the high level period of the pulse output from the PWM circuit 63 becomes longer. As a result, the control voltage output through the low-pass filter 66 becomes larger. On the other hand, when the frequency of the input signal tends to be smaller than the frequency of the clock signal, the count value of the counter 62 becomes lower and the width of the high level of the pulse output from the PWM circuit 63 becomes smaller. As a result, the level of the control voltage output from the low-pass filter 66 also decreases.

On the other hand, when the frequencies of the data input signal and the clock signal are equal, the frequencies of occurrence of the up signal and the down signal are approximately equal. At this time, the width of the CHG signal is often almost the same as in the previous case. As a result, the same logic is less likely to be continuously output from the comparator 57, and the number of occurrences of logic 1 and logic 0 becomes approximately equal. As a result, the count value of the counter 62 remains approximately constant. As a result, the width of the pulse output from the PWM circuit 63 also becomes constant. As a result, the control voltage output to the adder 24 also becomes approximately constant.

The adder 24 adds the control voltage corresponding to the phase error supplied from the loop filter 23 and the control voltage corresponding to the frequency error supplied from the frequency detection circuit 26, and outputs the final control voltage to the VCO 25. supply to. The VCO 25 generates a clock having a frequency and phase corresponding to this input control voltage.

When the center frequency of the VCO 25 changes in response to temperature changes, the control voltage output from the frequency detection circuit 26 changes. As a result, the frequency of the clock output by the VCO 25 is corrected. A control voltage corresponding to this frequency error is supplied to the VCO 25 without passing through the loop filter 23. Therefore, it is no longer necessary to set the loop filter 23 to a wide passband in consideration of frequency fluctuations corresponding to temperature changes.

The control voltage corresponding to the phase error is compensated to a predetermined frequency (phase) characteristic by the loop filter 23 and then supplied to the VCO 25 via the adder 24. Therefore, the correction corresponding to the phase error between the data input signal and the clock is set in accordance with the characteristics of the loop filter 23.

In this way, without comparing the data input signal with a preset fixed frequency reference signal, the V
If the frequency of the data input signal is compared with the frequency of the clock output from the CO 25, even if the frequency of the data input signal deviates considerably from a preset standard value, it is possible to follow the frequency well.

FIG. 8 is a block diagram showing the configuration of another embodiment of the frequency detection circuit 26. In this embodiment, during the period when the CHG signal is at a high level, a predetermined clock for clock operation (VCO 25
(not the clock output from the CHG signal) is counted by a counter 82, and the count value is reset in synchronization with the rising edge of the CHG signal. Further, the count value of the counter 82 is latched by the latch circuit 83 in synchronization with the falling edge of the CHG signal. That is, the latch circuit 83 stores the count value corresponding to the immediately previous high level period of the CHG signal.

The comparison circuit 84 calculates a count value corresponding to the high level period of the immediately preceding LHG signal latched by the latch circuit 83 and a count value corresponding to the high level period of the current CHG signal counted by the counter 82. Compare with the count value. When the output of the counter 82 is greater than the output of the latch circuit 83, a logic 1 is output to the latch circuit 85. Further, when the output of the counter 82 is smaller than the output of the latch circuit 83, a logic 1 is output to the latch circuit 87.

Latch circuits 85 and 87 latch the output of comparison circuit 84 in synchronization with the falling edge of the LHG signal. Also, the latch circuits 86 and 88 are connected to the latch circuit 85 or 87 in synchronization with the falling edge of the CHG signal.
Latch the output of That is, the latch circuits 86 and 88 latch the count value corresponding to the immediately previous period of the CHG signal.

The AND circuit 89 connects the latch circuits 85 and 86.
When the outputs of both are logic 1, the counter 91 has logic 1.
Output. Similarly, when the outputs of the latch circuits 87 and 88 are both logic 1, the AND circuit 90 outputs the counter 9.
Logic 1 is output to the negative input terminal of 1. The counter 91 is
When a logic 1 is input from the AND circuit 89, the count value is incremented by 1, and a logic 1 is input from the AND circuit 90.
When is input, the count value is counted down by 1. PWM circuit 92 outputs a pulse with a width corresponding to the output of counter 91. The pulses output from the PWM circuit 92 are smoothed by a low-pass filter 93 and output to the adder 24.

Even in this case, a control voltage corresponding to the frequency error between the data input signal and the clock can be generated. In addition, also in the case of this example, CHG
The rising edge and falling edge of the signal can be detected by an inverter and an AND circuit or an inverter and a NOR circuit, as in the case in FIG.

[0043]

As described above, according to the PLL circuit of the present invention, since the control signal corresponding to the frequency error between the input signal and the clock is supplied to the oscillation circuit without going through the loop filter, the height of the loop filter can be reduced. It becomes possible to generate a clock corresponding to an input signal in a wide frequency range without increasing the frequency characteristics. As a result, increase in clock jitter is prevented. Furthermore, it becomes possible to use an oscillation circuit that is unstable with respect to temperature, which is advantageous for LSI implementation. Furthermore, costs can also be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a PLL circuit of the present invention.

FIG. 2 is a block diagram showing the configuration of an example of the phase detection circuit 21 in the example of FIG. 1;

FIG. 3 is a timing chart illustrating the operation of the embodiment of FIG. 2 when the phase difference is 90 degrees.

FIG. 4 is a timing chart illustrating the operation of the embodiment of FIG. 2 when the phase difference is smaller than 90 degrees.

FIG. 5 is a timing chart illustrating the operation of the embodiment of FIG. 2 when the phase difference is greater than 90 degrees.

FIG. 6 is a diagram illustrating the characteristics of a CHG signal in the embodiment of FIG. 2;

7 is a block diagram showing the configuration of an embodiment of the frequency detection circuit 26 in the embodiment of FIG. 1. FIG.

8 is a block diagram showing the configuration of another embodiment of the frequency detection circuit 26 in the embodiment of FIG. 1. FIG.

FIG. 9 is a block diagram showing the configuration of an example of a conventional PLL circuit.

10 is a diagram illustrating an example of a configuration of a loop filter 2 in the example of FIG. 9. FIG.

11 is a diagram showing frequency characteristics of the loop filter in FIG. 10. FIG.

[Explanation of symbols] 21 Phase detection circuit 22 Generation circuit 23 Loop filter 24 Adder 25 Voltage controlled oscillator 26 Frequency detection circuit 41, 42 Latch circuit 44, 45 Exclusive OR circuit

Claims (1)

[Claims] 1. An oscillation circuit that generates a clock corresponding to a control signal, a phase comparison circuit that detects a phase error between the clock and an input signal, and a loop that compensates the output of the phase comparison circuit to a predetermined frequency characteristic. A filter, a frequency comparison circuit that detects a frequency error between the input signal and the clock, and an addition circuit that adds the output of the loop filter and the output of the frequency comparison circuit to generate the control signal. PLL circuit.