JP2844596B2 - PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a digital VT capable of variable speed reproduction.
The present invention relates to a PLL circuit including a charge pump type phase comparator suitable for use in R and the like. SUMMARY OF THE INVENTION The present invention relates to a PL having a charge pump type phase comparator.
In the L circuit, the center frequency of the VCO is controlled using a current output type operational amplifier, and the gain of this operational amplifier is adaptively controlled based on the mode signal, thereby impairing the hold characteristic during normal reproduction. Instead, the tracking characteristic is improved at the time of variable speed reproduction or the like. [Prior Art] In a clock recovery PLL circuit used in a digital VTR or the like, a charge pump type phase comparator is generally used. This charge pump type phase comparator has a feature that a high conversion gain can be obtained, and an output voltage can be held very easily due to its configuration. It also functions effectively when a timing component cannot be extracted for a long time due to dropout or the like. FIG. 3 shows a conventional charge pump type phase comparator.
1 shows a configuration of a PLL circuit. As shown in FIG. 3, a pulse shaping circuit 32, a charge pump type phase comparator 33, a capacitor 34 for forming a control voltage, a variable voltage source 40 and a resistor 35 for setting a center frequency, a buffer circuit 36, a loop filter 37, A PLL circuit is composed of a VCO (voltage controlled oscillator) 38 and the like. In FIG. 3, reference numeral 31 denotes an input terminal,
The input terminal 31 supplies data such as a digital video signal as an input signal. Digital data from the input terminal 1 is supplied to one input terminal of the phase comparator 33 via the pulse shaping circuit 32. The output of the VCO 38 is supplied to the other input terminal of the phase comparator 33. A capacitor 34 for forming a control voltage is connected to an output stage of the phase comparator 33. The other end of the resistor 35 whose one end is connected to the variable voltage source 40 is connected to a connection point between the control voltage forming capacitor 34 and the buffer circuit 36, and a predetermined DC voltage from the variable voltage source 40 Is applied to the capacitor 34 and the buffer circuit 36 via the resistor 35. In the phase comparator 33, the output of the pulse shaping circuit 32 and VC
The phase of the output of O38 is compared with the output, and an output corresponding to the phase difference is formed. The output of the phase comparator 33 charges and discharges the control voltage forming capacitor 34, and forms a control voltage so that the VCO 38 follows the frequency and phase of the input signal. The control voltage extracted via the capacitor 34 is supplied to the buffer circuit 36, which outputs a control voltage proportional to the charging / discharging time of the capacitor 34 centering on the voltage of the variable voltage source 40. This control voltage is supplied to the control terminal of the VCO 38 via the loop filter 37. The VCO 38 is controlled by a predetermined control voltage from which a noise component supplied through the buffer circuit 36 and the loop filter 37 has been removed, and the VCO 38 oscillates at a predetermined frequency and phase according to the control voltage. The output of the VCO 38 that matches the frequency and phase of the input signal is extracted from the output terminal 39 and supplied to each unit as a clock signal. FIG. 4 shows an example of a specific configuration of the charge pump type phase comparator 33 described above. In FIG. 4, reference numerals 59 and 60 indicate PNP transistors, and reference numerals 53, 54, 57 and 58 indicate NPN transistors. A transistor is connected to the power supply terminal 61 to which a positive DC voltage is supplied.
The emitter of 59 and the emitter of transistor 60 are connected. The base of the transistor 59 and the base of the transistor 60 are connected, and the collector of the transistor 59 is connected to this connection point. The collector of the transistor 59 and the collector of the transistor 53 are connected, and the transistor 60
And the collector of the transistor 54 are connected. The emitter of the transistor 53 is connected to the emitter of the transistor 54, and the connection point is connected to the collector of the transistor 58. An emitter of the transistor 57 whose collector is grounded is connected to an emitter of the transistor 58, and a current source 62 is connected to this connection point. A predetermined negative DC voltage is supplied to the current source 62 via a power supply terminal 63. The inverted output terminal of the amplifier 52 is connected to the base of the transistor 53, and the non-inverted output terminal of the amplifier 52 is connected to the base of the transistor. An input terminal 51 is derived from the amplifier 52. The inverted output terminal of the amplifier 56 is connected to the base of the transistor 57, and the non-inverted output terminal of the amplifier 56 is connected to the base of the transistor 58. An input terminal 55 is derived from the amplifier 56. The other end of the control voltage forming capacitor 34 whose one end is grounded is connected to the connection point between the collector of the transistor 60 and the collector of the transistor 54, and one end of the resistor 35 connected to the variable voltage source 40 is connected. ing. The input terminal 51 is supplied with the output of the aforementioned VCO 38,
The output of the pulse shaping circuit 32 is supplied to the input terminal 55. When the input terminal 55 is set to the high level, the transistor 58 is turned on. At this time, the VCO3 applied to the input terminal 51 is
The charging and discharging of the capacitor 34 is performed according to the output of 8. For example, with transistor 58 turned on,
When the level of 51 is set high and the transistor 54 is turned on,
The capacitor 34 discharges. When the transistor 58 is turned on and the input terminal 51 is set to low level, and the transistor 53 is turned on, the capacitor 34 is charged. Accordingly, a control voltage proportional to the charging / discharging time of the capacitor 34 is output from the buffer circuit 36 with the DC voltage of the variable voltage source 40 as the center. As described above, the resistor 35 and the variable voltage source 40 are for controlling the center frequency of the VCO 38. Even when the input terminal 55 is not set to the high level by the input signal, the oscillation frequency of the VCO 38 becomes unstable. Has been prevented. Further, the variable voltage source 40 is varied according to, for example, the reproduction speed of the digital VTR, and is used so that the PLL circuit follows a large change in the frequency of the reproduced data without pseudo-locking to some extent. [Problems to be Solved by the Invention] However, in the conventional PLL circuit, a high-resistance resistor is used as the resistor 35, and the voltage of the variable voltage source 40 is supplied to the control voltage forming capacitor 34 through the resistor 35. Is applied, it takes a very long time to draw in a predetermined oscillation frequency due to the large charging time constant, and there is a problem that a sufficient tracking characteristic cannot be obtained. Therefore, in order to solve the above problem, the value of the resistor 35 is reduced.
It is conceivable that the center frequency of the VCO 38 can be easily changed.However, if the value of the resistor 35 is set to a small value, a discharge occurs due to the resistor 35 during normal operation, which causes a problem of deteriorating the hold characteristic. In addition, there is a problem that the loop gain becomes small. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a PLL circuit capable of obtaining a sufficient tracking characteristic without impairing a hold characteristic during a normal operation. If the variable range of the VCO is wide, a so-called pseudo lock that is fixed at an integral multiple of a predetermined frequency may occur. In the case of such a pseudo lock, the state easily escapes from the state. Therefore, the oscillation frequency is returned to a predetermined value by turning off the power and turning on the power again. Therefore, another object of the present invention is to provide a PLL circuit that can easily return to a normal frequency without using a means such as power-on and the like. Means for Solving the Problems The present invention relates to a voltage controlled oscillator, a charge pump type phase comparator for comparing the phase of an output signal and an input signal of the voltage controlled oscillator, and a charge pump type phase comparator A control voltage forming capacitor to which an output signal is supplied and a control circuit to which a control voltage output from the capacitor is supplied to control the voltage-controlled oscillator so that an output signal is obtained from the voltage-controlled oscillator. The output terminal of the current output type operational amplifier is connected to the output side of the charge pump type phase comparator, and the output signal of the charge pump type phase comparator is supplied to one input terminal of the current output type operational amplifier. A predetermined voltage for setting the center frequency of the voltage controlled oscillator is supplied to the other input terminal of the amplifier, and the current output type operational amplifier is supplied to the other input terminal. Comparing means for comparing a predetermined voltage with an output signal of the charge pump type phase comparator; voltage-current converting means for supplying a comparison output from the comparing means and supplying a control signal, and outputting an output signal to an output terminal And first and second switching circuits for supplying a control signal for controlling the gain of the current output type operational amplifier are connected to the voltage-current conversion means, and the first and second switching circuits are connected to the first and second switching circuits. In the switching state, a control signal for setting the gain to 0 is supplied to the voltage-to-current converter so that the current output type operational amplifier is disconnected from the output of the charge pump type phase comparator, and the first and second switching circuits perform the switching operation. In the switching state of 2, the gain is set to the first
Is supplied to the voltage-current conversion means,
When the control voltage of the capacitor is equal to the predetermined voltage, the frequency of the output signal of the voltage controlled oscillator is controlled to the center frequency corresponding to the predetermined voltage, and when the first and second switching circuits are in the third switching state, A control signal having a gain equal to or higher than the first gain is supplied to the voltage-current converter, and the control voltage of the capacitor becomes equal to the predetermined voltage so that the frequency of the output signal of the voltage controlled oscillator corresponds to the predetermined voltage. And the first and second switching circuits are brought into the second switching state for a predetermined period from the time of switching to the variable-speed reproduction, and the first and second switching circuits generate a pseudo lock. A third switching state for a predetermined period from when
This is a PLL circuit. [Operation] A current output type operational amplifier 5 is used as means for controlling the center frequency of the VCO 8, and the output terminal 15 of the operational amplifier 5 is connected to the capacitor 4 and the buffer circuit 6 connected to the output stage of the charge pump type phase comparator 3. Is connected to the connection point. The output of the buffer circuit 6 is supplied to one input terminal 11 of the operational amplifier 5, and the output of the variable voltage source 10 that is varied according to the reproduction speed is supplied to the other input terminal 12. One end of a resistor 18 whose other end is grounded via a switch circuit 20 is connected to the control terminal 16 of the operational amplifier 5, and one end of a resistor 19 whose other end is grounded via a switch circuit 21 is connected. During normal operation, both the switch circuits 20 and 21 are turned off, the gain of the operational amplifier 5 is set to (gm = 0), and the operational amplifier 5 is disconnected from the output of the phase comparator 3. You. Further, when the power supply voltage is turned on and during variable speed reproduction, the switch circuit 21 is turned on for a predetermined period, and the gain of the operational amplifier 5 is reduced by the resistance 19.
Is a gm ₁ defined by is drawn forcibly so that the voltage of the capacitor 4 becomes equal to the voltage of the variable voltage source 10. Further, when a pseudo lock occurs, the switch circuit 20 is turned on for a predetermined period, and the operational amplifier 5 is turned on.
Is set to gm ₂ (gm ₂ > gm ₁ ) defined by the resistor 18, and the voltage of the capacitor 4 is forcibly pulled in so as to be equal to the voltage of the variable voltage source 10. Embodiment An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. A case where the present invention is applied to a digital VTR capable of variable speed reproduction will be described. In FIG. 1, reference numeral 1 denotes an input terminal, and a digital video signal is supplied to the input terminal 1 as an input signal. Input digital data from an input terminal 1 is supplied to a pulse shaping circuit 2. In the pulse shaping circuit 2, digital data whose waveform has been shaped and output as a rectangular wave is supplied to one input terminal of the charge pump type phase comparator 3. The output of the VCO 8 is supplied to the other input terminal of the phase comparator 3. A capacitor 4 for forming a control voltage is connected to an output stage of the phase comparator 3. The connection point between the control voltage forming capacitor 4 and the buffer circuit 6 is connected to an output terminal of a current output type operational amplifier 5 called a transconductance OP amplifier, which is enclosed by a broken line in FIG. I have. The output of the operational amplifier 5 is supplied to a connection point between the capacitor 4 and the buffer circuit 6. The operational amplifier 5 provided as a means for controlling the center frequency of the VCO 8 includes an arithmetic circuit 13 having a gain A and a voltage-current converting circuit 14, from which two input terminals 11, 12 are derived. An output terminal 15 and a control terminal 16 are derived from the voltage-current conversion circuit 14. The output of the buffer circuit 6 is supplied to one input terminal 11, and a predetermined DC voltage from the variable voltage source 10 is supplied to the other input terminal 12. In the arithmetic circuit 13, the output level of the buffer circuit 6 is compared with the level of the variable voltage source 10, an output corresponding to the difference is formed, and this comparison output is supplied to the voltage-current conversion circuit 14. The control signal from the control terminal 16 is supplied to the voltage / current conversion circuit 14, and the conversion gain gm 'of the voltage / current conversion circuit 14 is adaptively controlled in a manner, for example, in inverse proportion to the level of the control signal. For this reason, the gain gm of the entire operational amplifier 5 is set to (gm = A × gm ′) according to the level of the control terminal 16. One end of a resistor 18 whose other end is grounded via a switch circuit 20 is connected to the control terminal 16 of the operational amplifier 5, and one end of a resistor 19 whose other end is grounded via a switch circuit 21 is connected. Have been. Relationship between the value R ₂ of the values R ₁ and the resistor 18 of the resistor 19 connected to the control terminal 16, (R _1>
R ₂ ). The switch circuit 21 has a control terminal, for example,
When this control terminal is set to the high level, the switch circuit 21
Turns on. OR of negative input to control terminal of switch circuit 21
The output of circuit 24 is provided. A control signal that is at a low level for a predetermined period is supplied to a terminal 25 derived from one input terminal of the OR circuit 24 of the negative input from a timing of switching between the normal speed reproduction mode and the variable speed reproduction mode. Further, a control signal which is kept at a low level for a predetermined period in response to the power supply voltage is supplied to a terminal 26 derived from the other input terminal of the OR circuit 24 having a negative input. That is, the switch circuit 21 is turned on when the power supply voltage is turned on or during variable speed reproduction, and the gain of the operational amplifier 5 is set to gm ₁ defined by the value R ₁ of the resistor 19. The switch circuit 20 has a control terminal. For example, when the control terminal is set to a high level, the switch circuit 20 is turned on. Terminal to control terminal of switch circuit 20
A control signal from 23 is supplied via an inverter 22.
Terminal 23 was detected due to a sudden increase in code errors, etc.
A control signal which is set to a low level in accordance with the pseudo lock information of the PLL circuit is supplied. That is, when the occurrence of the pseudo lock is detected, the switch circuit 20 is turned on, and the gain of the operational amplifier 5 is set to gm ₂ (gm ₂ > gm) defined by the value R ₂ of the resistor 18.
₁ ) To be. As described above, the output of the voltage-current converter 14 whose gain is made variable according to the state of the digital VTR is taken out from the output terminal 15 as the output of the operational amplifier 5 and supplied to the connection point of the capacitor 4 and the buffer circuit 6. You. In the phase comparator 3, the output of the pulse shaping circuit 2 and VC
The phase of the output of O8 is compared, and an output corresponding to the phase difference is formed. The output of the phase comparator 3 charges and discharges the capacitor 4 for forming a control voltage, and forms a control voltage so that the VCO 8 follows the frequency of the input signal. The control voltage extracted via the capacitor 4 is supplied to the buffer circuit 6, and the buffer circuit 6 outputs a control voltage proportional to the charging / discharging time of the capacitor 4 centering on the voltage of the variable voltage source 10. The control voltage is supplied to the loop filter 7. As the loop filter 7, for example, a low-pass filter is used, and a noise component included in the control voltage is removed by the low-pass filter, and a control voltage having only a DC component is supplied to the control terminal of the VCO 8. The VCO 8 is controlled by a predetermined control voltage from the loop filter 7, oscillates at a predetermined oscillation frequency according to the control voltage, and is controlled to match the frequency and phase of the input signal. The output of the VCO 8 is taken out via the output terminal 9 and supplied to each section as a clock signal. The operation of each state in the above-described embodiment will be described in more detail. For example, the oscillating frequency of the VCO 8 is controlled according to the phase of the input signal, and during normal operation in which the VCO 8 is locked, the switches 20 and 21 are turned off and the control terminal of the operational amplifier 5 is opened. As described above, the voltage-current conversion circuit 14 converts the conversion gain gm ′ in a form inversely proportional to the level of the control signal.
Is controlled, (gm ′ = 0), and (gm = 0). That is, the voltage-current conversion circuit 14 may be equivalently expressed as an NPN transistor 14 'as shown in FIG. 2, and as easily understood from the equivalent circuit shown in FIG. And 21 are off, the transistor 14 'equivalent to the voltage-current converter 14 is off regardless of the voltage supplied to the base, the resistance from the capacitor 4 is equivalently infinite, and the operational amplifier 5 The state is disconnected from the output of the phase comparator 3. For this reason, the capacitor 4 does not discharge via the operational amplifier 5, sufficient hold characteristics are secured, and the loop gain is increased. When the power supply voltage is turned on, a low-level control signal is supplied to the terminal 26 for a predetermined period required for locking to a predetermined oscillation frequency, and the switch circuit 21
Is turned on, and the gain gm ₁ defined by the value R ₁ of the resistor 19 is
, The operational amplifier 5 operates. Therefore, the voltage of the capacitor 4 is forcibly pulled in so as to be equal to the voltage of the variable voltage source 10, and the center of the oscillation frequency of the VCO 8 is quickly set to a predetermined value. During variable speed reproduction, the output voltage of the variable voltage source 10 is set to a different value, and a control signal that is set to low level for a predetermined period required for locking the frequency is supplied to the terminal 25. , The switch circuit 21 is turned on. For this reason, the voltage of the capacitor 4 is forcibly pulled in so as to be equal to the voltage of the variable voltage source as in the above-described power supply voltage application, and the center of the oscillation frequency of the VCO 8 is quickly set to a predetermined value corresponding to the variable speed reproduction speed. Set to something. When the pseudo lock occurs, the control signal supplied to the terminal 23 is set to the low level, the switch circuit 20 is turned on, and the operational amplifier 5 operates with the gain gm ₂ specified by the value R ₂ of the resistor 18. I do. As described above, the relationship between the value R ₂ of the values R ₁ and the resistor 18 of the resistor 19, (R _1> R ₂₎ and because it is selected so that the power supply voltage-on and speed playback or more The operational amplifier 5 operates with the gain gm ₂ , and the voltage of the capacitor 4 changes with a large forcing force due to the pull-in of the phase comparator 3.
A predetermined oscillation frequency is easily set. [Effect of the Invention] In the present invention, a current output type operational amplifier is used as means for controlling the center frequency of the VCO, and the gain of the operational amplifier is adaptively controlled based on the mode signal. During normal operation, the gain of the operational amplifier is set to 0, the operational amplifier is disconnected from the output of the charge pump type phase comparator, and operates stably.
Further, when the power supply voltage is turned on and during variable speed reproduction, the gain of the operational amplifier is set to a predetermined value over a predetermined period,
The voltage of the control voltage forming capacitor is forcibly pulled so as to be equal to the voltage of the variable voltage source. Further, when the pseudo lock occurs, the gain of the operational amplifier is set to a predetermined value over a predetermined period, and when the power supply voltage is turned on so that the voltage of the control voltage forming capacitor becomes equal to the voltage of the variable voltage source. It is forcibly pulled in more strongly than during variable speed playback. Therefore, according to the present invention, it is possible to prevent unnecessary discharge of the control voltage forming capacitor during normal operation, and to forcibly cope with a large change in frequency when the power supply voltage is turned on or during variable speed reproduction. The control voltage can be largely varied, sufficient tracking characteristics can be obtained without impairing the hold characteristics, and a wide lock range can be secured. Further, according to the present invention, it is possible to easily return to the normal frequency without using a means such as turning on the power again. Therefore, if the PLL circuit of the present invention is used for a digital VTR for performing multi-channel recording, for example,
Even if one channel is pseudo-locked and the data cannot be played back, it is possible to restore the pseudo-locked channel from the pseudo-lock without turning off the power while restoring the image from the data of the other channel.
Function can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a connection diagram used for describing a current output type operational amplifier in one embodiment of the present invention, and FIG. FIG. 4 is a block diagram illustrating a PLL circuit, and FIG. 4 is a connection diagram as an example of a specific configuration of a charge pump type phase comparator. Explanation of main symbols in the drawing 1: input terminal, 2: pulse shaping circuit, 3: charge pump type phase comparator, 4: capacitor for forming control voltage, 5: current output type operational amplifier, 8: VCO, 9: Output terminal, 10: variable voltage source, 18, 19: resistor, 20, 21: switch circuit.

Claims (1)

(57) [Claims] A voltage-controlled oscillator, a charge-pump type phase comparator for comparing the phase of an output signal and an input signal of the voltage-controlled oscillator, and a control voltage forming circuit to which an output signal of the charge-pump type phase comparator is supplied. A capacitor and a PLL circuit that is supplied with a control voltage output from the capacitor and controls the voltage-controlled oscillator to obtain an output signal from the voltage-controlled oscillator. Connected to the output terminal of the current output type operational amplifier, to supply the output signal of the charge pump type phase comparator to one input terminal of the current output type operational amplifier, and to the other input of the current output type operational amplifier A predetermined voltage for setting a center frequency of the voltage controlled oscillator is supplied to a terminal, and the current output type operational amplifier is connected to the other input terminal. Comparing means for comparing the supplied predetermined voltage with an output signal of the charge pump type phase comparator; a comparison output from the comparing means is supplied and a control signal is supplied, and the output signal is supplied to an output terminal. A voltage-current converter for outputting the control signal for controlling the gain of the current output type operational amplifier, and a first and a second switching circuit connected to the voltage-current converter, And when the second switching circuit is in the first switching state, the control signal for setting the gain to 0 so that the current output type operational amplifier is disconnected from the output of the charge pump type phase comparator is the voltage / current conversion. And when the first and second switching circuits are in the second switching state, the control signal for setting the gain to the first gain is applied to the voltage / current change. And the control voltage of the capacitor becomes equal to the predetermined voltage, and the frequency of the output signal of the voltage controlled oscillator is controlled to a center frequency corresponding to the predetermined voltage, and the first and second switching operations are performed. When the circuit is in the third switching state, the control signal for setting the gain to a second gain equal to or higher than the first gain is supplied to the voltage-current converter, and the control voltage of the capacitor and the predetermined voltage And the frequency of the output signal of the voltage-controlled oscillator is controlled to a center frequency corresponding to the predetermined voltage. The first and second switching circuits perform the first and second switching circuits for a predetermined period after switching to variable-speed reproduction. 2 and the first and second switching circuits are in the third switching state for a predetermined period after the occurrence of the pseudo lock. PLL circuit according to claim Rukoto.