JPH10340544A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To widen a capture range as wide as possible and to reduce the clock jitter at the time of phase synchronization by detecting the output level of a delay means at the rise or fall based on a reproducing data signal and chang ing the loop gain. SOLUTION: A phase comparator 4 performs phase comparison of a reproducing data signal with the output of a frequency divider 14 inverted through an inverter 15 and a signal corresponding to the phase difference is sent to a charging pump 81 through a switch 6b. A loop gain becomes a loop gain determined by the current value of the charging pump 81 when the phase difference is <±90 deg. and when it is >=±90 deg., the loop gain becomes a gain determined by the current sum of charging pumps 81, 82. When VCO 12 oscillates at the objective frequency and is phase synchronized, the phase difference becomes zero and the clock jitter is determined by the current value of the charging pump 81. When the oscillating frequency of VCO 12 is deviated from the objective frequency, the phase difference is gradually changed, becomes ±90 deg., the loop gain in a phase comparator 42 is increased and the capture range is widened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit for extracting a clock from a reproduced data signal, and is particularly used for an information recording device such as an HDD, an optical disk, and a DAT.

[0002]

2. Description of the Related Art Generally, an HDD (Hard Disk Driver),
Optical disk or DAT (Digital Audio Tape record
In an information recording apparatus such as er), information is basically recorded depending on whether or not there is a pulse. Therefore, the reproduced data sequence of the information recording device does not always have pulses appearing at the same interval as the clock synchronized with the data sequence.
Therefore, the PLL circuit used in the information recording device compares the phase with the clock only when a pulse appears in the reproduced data.

FIG. 1 shows the configuration of such a conventional PLL circuit.
3 is shown. The PLL circuit includes a frequency comparator 2, a phase comparator 4, a selector circuit 6, a charge pump 8,
A loop filter 10 and a voltage controlled oscillator (hereinafter, VCO)
) 12 and an inverter 15.

[0004] The frequency comparator 2 uses a PLL to reproduce the reproduced data signal.
When the signal is not sent to the circuit, the frequency of the reference clock is compared with the frequency of the output of the VCO 12 inverted by the inverter 15, and a signal corresponding to the frequency difference is output to the selector circuit 6
To the charge pump 8 via. Selector circuit 6
Are switches 6a and 6b that open and close based on a control signal.
have. The switch 6a sets the reproduction data signal to the PL
Turns on when not input to the L circuit and sends the output of the frequency comparator 2 to the charge pump 8. Switch 6b
Is ON when the reproduction data signal is input to the PLL circuit
Then, the output of the phase comparator 4 is sent to the charge pump 8.

The phase comparator 4 includes flip-flops 4a, 4
b and AND circuits 4c, 4d, and 4e. When a reproduced data signal is input to the PLL circuit, the reproduced data signal and the VCO1 inverted by the inverter 15 are output.
2 and outputs a signal corresponding to the phase difference to the charge pump 8 via the selector circuit 6. The charge pump 8 operates to supply current to the loop filter 10 and to extract current from the loop filter 10 based on the output of the frequency comparator 2 or the phase comparator 4 sent via the selector circuit 6. The input voltage of the VCO 12 is adjusted so that the frequency difference or the phase difference becomes zero.

The VCO 12 outputs a pulse corresponding to the input voltage as a clock signal, and controls the frequency difference or the phase difference to be zero.

The flip-flop 4 of the phase comparator 4
As for a, a signal of "H" level is always applied to the D terminal, and a reproduced data signal is inputted as a clock. On the other hand, in the flip-flop 4b, the Q output of the flip-flop 4a is input to the D terminal, the output of the VCO 12 inverted by the inverter 15 is input as a clock, and the "L" level signal is always input to the reset terminal. AND
The circuit 4c performs an AND operation based on the Q output of the flip-flop 4a and the Q output of the flip-flop 4b, and sends the operation result to the flip-flop 4a as a reset signal. The AND circuit 4d performs an AND operation based on the Q output of the flip-flop 4a and the Q bar output of the flip-flop 4b, and sends the operation result to the charge pump 8 via the switch 6b as a charge signal. A
The ND circuit 4e is connected to the Q output of the flip-flop 4b and the VCO
A logical AND operation is performed on the basis of the output of the switch 12 and the operation result is sent to the charge pump 8 via the switch 6b as a discharge signal.

The operation of the PLL circuit thus configured will be described with reference to FIGS. Now, FIG.
When the reproduced data signal shown in (a) is input to the phase comparator 4, the rising of the pulse of the reproduced data signal is detected by the flip-flop 4a. From the rising edge of this pulse (time t ₁ ), VCO1 shown in FIG.
Until the output 2 falls (time t ₂ ), the AND circuit 4d outputs the charge pulse shown in FIG. 14C. And, from the rising of the next output of the VCO 12 (time t ₃ ) to the falling (time t ₄ ), AND
A discharge pulse shown in FIG. 14D is output from the circuit 4e.

When the charge pump 8 receives the charge pulse, a constant current is supplied from the charge pump 8 to the loop filter 10 while the charge pulse is at "H" level. When a discharge pulse is received, a constant current is drawn from the loop filter 10 to the charge pump 8 while the discharge pulse is at the “H” level. As a result, a series of charge and discharge operations allow the charge pump 8 to move the loop filter 10
Is proportional to the phase difference between the reproduced data signal and the output pulse of the VCO 12, and VC is set so that the phase difference becomes zero.
The input voltage of O12 is controlled.

The output of the VCO 12 of this PLL circuit (FIG. 1)
5 (a) is shown in FIG. 15 (b). The vertical axis in FIG. 15B is an amount proportional to the difference between the pulse widths of the charge pulse and the discharge pulse, that is, P
3 illustrates a loop gain of the LL circuit.

[0011]

In such a PLL circuit, there are many oscillation frequencies of the VCO 12 synchronized with data. That is, the oscillation frequency of the VCO 12 that can be pulled to the target frequency is limited to a finite frequency range. This is called a capture range. Since the capture range is finite, such a PLL circuit has a frequency comparator 2 in addition to the phase comparator 4, and synchronizes the oscillation frequency of the VCO 12 with the reference clock when no reproduction data is input. Is kept within the capture range.

The frequency of the reference clock is the same as the clock frequency of the data at the time of recording. Therefore, the frequency of the reference clock and the clock frequency of the reproduced data are generally substantially the same. However, there may be a case where a difference occurs between the frequency of the reference clock and the clock frequency of the reproduced data due to a factor such as rotation fluctuation of the motor. For this reason, the capture range of the PLL circuit must be wide enough to allow this shift.

In such a PLL circuit, the capture range is proportional to the loop gain. That is, the capture range of the PLL circuit can be expanded by increasing the current of the charge pump or increasing the gain of the VCO 12 (the ratio Δf / ΔV of the frequency change Δf to the voltage change ΔV). However, when the loop gain is increased, the frequency fluctuation of the VCO 12 in a series of charge-discharge operations when the phases are synchronized increases, and the clock jitter increases. That is, when the loop gain is increased to widen the capture range, there is a problem that clock jitter increases.

The present invention has been made in view of the above circumstances, and provides a PLL circuit capable of expanding a capture range as much as possible and reducing clock jitter during phase synchronization. With the goal.

[0015]

A PLL circuit according to the present invention comprises: a voltage controlled oscillator for outputting a clock signal according to an input voltage; a frequency divider for dividing the output of the voltage controlled oscillator by n; Frequency comparing means for comparing the frequency of the clock with the frequency of the output of the frequency dividing means, and outputting a signal corresponding to the frequency difference; and comparing the phase of the reproduced data signal with the output of the frequency dividing means. A first phase comparison means for outputting a signal corresponding to the following, a selection means for selecting an output signal of the frequency comparison means or an output signal of the first phase comparison means based on a control signal, and an output of the selection means Input voltage control means for controlling an input voltage of the voltage controlled oscillation means so that the frequency difference or the phase difference becomes zero based on the output of the voltage controlled oscillation means and the output of the frequency dividing means. Delay means for outputting a signal delayed by a predetermined clock from the output of the frequency dividing means, level detecting means for detecting the output level of the delay means at the time of rising or falling as a reference time of the reproduced data signal, Loop gain changing means for changing the loop gain based on the output of the level detecting means. Further, the frequency dividing means divides the output of the voltage controlled oscillator by two, the delay means outputs a signal delayed by 1/4 clock from the output of the frequency dividing means, and the loop gain changing means comprises: When the phase difference between the reproduced data signal and the output of the frequency dividing means is in the range of -90 degrees to 90 degrees, the loop gain is not changed, and when the phase difference is in the other range, the loop gain is increased. May be.

Further, the input voltage control means includes a loop filter connected to an input terminal of the voltage controlled oscillation means, and a current supplied to the loop filter based on an output of the selection means, or a current supplied from the loop filter. A first charge pump for controlling the input voltage applied to the input terminal of the voltage-controlled oscillating means by pulling out the voltage-controlled oscillator may be provided.

Further, the first charge pump may be of a variable current type, and the loop gain changing means may control the current of the first charge pump based on an output of a level detecting means. .

The loop gain changing means compares the phase of the reproduced data signal with a signal obtained by inverting a clock signal output from the voltage control oscillating means, and outputs a signal corresponding to a phase difference between these signals. A second phase comparison means for outputting the first phase comparison means, a logic circuit for performing an AND operation of an output of the second phase comparison means and an output of the level detection means, A switch means that is turned on only when an output signal is selected and that allows a current to flow into the loop filter based on an output of the logic circuit obtained through the switch means and the output of the logic circuit, A second charge pump that controls the input voltage applied to the voltage controlled oscillator by extracting a current from the loop filter. There.

The delay means includes an inverter for inverting the output of the voltage controlled oscillation means, and a D-type flip-flop to which the output of the inverter is input as a clock signal and the output of the frequency dividing means is input to a D terminal. And may be provided.

The delay means may be an exclusive OR circuit.

The level detecting means receives a signal obtained by inverting the output signal of the voltage controlled oscillation means as a clock, and outputs the output of the delay means to a D terminal.
A type flip-flop may be provided.

[0022]

FIG. 1 shows a configuration of a first embodiment of a PLL circuit according to the present invention. PL of this embodiment
The L circuit includes a frequency comparator 2 and phase comparators 4 ₁ , 4
_2, a logic circuit 5, a selector circuit 6, a charge pump _81, 82, a loop filter 10, voltage controlled oscillator (hereinafter also referred to as VCO) 12, a frequency divider 14, inverters 15, 16 And flip-flops 18 and 20.

The frequency comparator 2 determines that the reproduced data signal is PL
When the frequency is not sent to the L circuit, the frequency of the reference clock is compared with the frequency of the output of the frequency divider inverted by the inverter 15, and a signal corresponding to the frequency difference is supplied to the charge pump 8 via the switch 6 a of the selector circuit 6. Send to ₁ . The frequency divider 14 operates so as to divide the output of the VCO 12 by two, and the output of the frequency divider 14 becomes a clock output to be output to the outside.

The phase comparator 4 _1, conventional P shown in FIG. 13
Like the phase comparator 4 of the LL circuit, the flip-flop 4
a, 4b and AND circuits 4c, 4d, 4e. Then the reproduced data signal, via the inverter 15 performs phase comparison between the output of the divider 14 is reversed, and sends a signal corresponding to the phase difference to the charge pump ₈₁ via the switch 6b of the selector circuit 6 .

The phase comparator 4 _2, a reproduction data signal, V
The flip-flops 4a and 4b and the AND circuits 4c and 4c are used to perform a phase comparison with a signal obtained by inverting the output of the CO12, similarly to the phase comparator 4 of the conventional PLL circuit shown in FIG.
4d and 4e. The logic circuit 5 is an AND circuit 5
a and 5b. The output of the phase comparator 4 VCO 12 as a clock of the _second flip-flop 4b is input, the inverted signal is used to output the VCO 12 as one input of AND circuit 4e by the inverter 16.

The logic circuit 5 has AND circuits 5a and 5b. The AND circuit 5a outputs the output of the AND circuit 4d,
ANDs based on the output of the flip-flop 20, and sends the operation result via the switch 6c of the selector circuit 6 to the charge pump ₈₂ as a charge signal. The AND circuit 5a has an output of the AND circuit 4e,
ANDs based on the output of the flip-flop 20, and sends the operation result via the switch 6c of the selector circuit 6 as a discharge signal to the charge pump _82.

[0027] The charge pump ₈₁ performs the same operation as the charge pump of the conventional PLL circuit shown in FIG. 13. The charge pump ₈₂ is switched 6c of the selector circuit 6
Based on the output of the logic circuit 5 transmitted through the circuit, the operation is performed so that a current flows into the loop filter 10 and a current is extracted from the loop filter 10.

The flip-flop 18 uses a signal obtained by inverting the output of the VCO 12 by the inverter 16 as a clock, and uses the output of the frequency divider 14 as the input of the D terminal.
Therefore, from the flip-flop 18, the frequency divider 1
A signal whose phase is delayed from 4 to 1/4 clock, that is, 90 degrees is output.

The flip-flop 20 uses the reproduced data signal as a clock and uses the output of the flip-flop 18 as the D terminal input. Therefore, this flip-flop 20 has a phase difference between the reproduced data signal and the clock output of-
It is detected whether it is in the range of 90 degrees to 90 degrees. That is, the flip-flop 20 operates at the time of reference of the reproduced data signal (at the time of rising or falling of the reproduced signal (at the time of rising in the present embodiment)).
Output level is detected.

Next, the operation of the first embodiment will be described with reference to FIG. Phase comparator 4 ₁ of the PLL circuit of this embodiment, since performs a phase comparison between the output of the reproduced data signal and a frequency divider 14 (see FIG. 2 (a)), the phase comparison characteristic diagram A characteristic graph shown in FIG.
This characteristic graph can be easily analogized from the conventional characteristic graph shown in FIG.

Further, the phase comparator 4 ₂ and the reproduced data signal, since it is intended to a phase comparison between the inverted signal of the output of VCO 12 (see FIG. 2 (c)), the phase comparison characteristic 2 ( The characteristic graph shown in d) is obtained.

On the other hand, the output of the flip-flop 18 (FIG. 2)
(E) is a clock output signal (see FIG. 2 (a)) delayed by 1/4 clock. Therefore, the output of flip-flop 18 is "L" when the phase difference from the rising edge of the clock output signal is in the range of -90 to 90 degrees.
Level, in the range of -180 degrees to -90 degrees or 90 degrees to
In the range of 180 degrees, it is at the "H" level. The output of the flip-flop 18 is the flip-flop 2
0, and the reproduced data signal is used as the clock signal of the flip-flop 20. Therefore, when the output of the flip-flop 18 is at the "L" level at the rise of the reproduced data signal, the output of the flip-flop 20 is It becomes “L”, and the operation of the logic circuit 5 stops. That is, when the logic circuit 5 operates, the output is only when the output of the flip-flop 18 is at the “H” level at the time of the rise of the reproduction data signal.

[0033] Thus, the phase comparator 4 ₂ and the logic circuit 5
FIG. 2F shows the phase comparison characteristic of the circuit composed of. That is, this phase comparison characteristic is shown in FIG.
In the characteristic graph shown in (1), the phase difference from the rising edge of the clock output signal is zero in the range of -90 degrees to 90 degrees.

Therefore, the PLL of the first embodiment
The phase comparison characteristic of the circuit is obtained by superimposing the phase comparison characteristic shown in FIG. 2B and the phase comparison characteristic shown in FIG. 2F (see FIG. 2G).

As described above, the PL of the present embodiment is
In L circuit, the loop gain becomes a gain determined by the charge pump 8 _first current value when the phase difference is less than ± 90 degrees, when the phase difference is more than ± 90 degrees, the charge pump ₈₁ and charge pump ₈₂ current The gain is determined by the sum of the values. Therefore, when the VCO 12 oscillates at the target frequency and the phases are synchronized, the phase difference becomes substantially equal to zero, and the clock jitter is reduced by the charge pump 8 ₁
Is determined by the current value. On the other hand, when the oscillation frequency of the VCO 12 is deviated from the target frequency, the phase difference gradually changes and always exceeds ± 90 degrees. Therefore, the phase comparator 4 ₂
Increases the capture range due to the effect of increasing the loop gain.

Thus, the capture range can be made as wide as possible, and the clock jitter during phase synchronization can be reduced.

[0037] In this first embodiment, the phase comparison characteristic 4 _2, the logic circuit 5, the circuit consisting of the switch 6c and the charge pump _82, is operated to change the loop gain of the PLL circuit Will be.

Next, the configuration of a PLL circuit according to a second embodiment of the present invention is shown in FIG. P of the second embodiment
The LL circuit is the same as the PLL circuit of the first embodiment shown in FIG. 1 except that an exclusive OR circuit 19 is provided instead of the flip-flop 18.

The exclusive OR circuit 19 performs an exclusive OR operation based on the output of the VCO 12 and the output of the frequency divider 14, and sends the operation result to the D terminal of the flip-flop 20. Therefore, the output of the exclusive OR circuit 19 is delayed by 1/4 clock from the clock output, similarly to the output of the flip-flop 18 of the first embodiment.

Thus, it goes without saying that the second embodiment also has the same effect as the first embodiment.

FIG. 4 shows the configuration of a third embodiment of the PLL circuit according to the present invention. P of the third embodiment
LL circuit, in the first embodiment shown in FIG. 1, the phase comparator 4 _2, the logic circuit 5, and the charge pump 8
It deletes the _2, in which the charge pump ₈₁ was replaced with a charge pump 9.

The charge pump 9 can change the amount of current based on the Q output of the flip-flop 20. In particular, the phase difference between the reproduced data signal and the clock output (output of the frequency divider 14) is -90 degrees. It operates to increase the amount of current when it is less than or equal to or more than 90 degrees.

Next, the operation of the third embodiment will be described with reference to FIG. Since the phase comparator 4 compares the phase difference between the reproduced data signal and the clock output (see FIG. 5A), the phase comparison characteristic of the phase comparator 4 is as shown in FIG.
The graph shown in FIG. And flip-flop 1
As shown in FIG. 5 (c), the output of FIG.
This is delayed by four clocks. Based on the Q output of the flip-flop 18 and the reproduced data signal, the flip-flop 20 determines whether or not the phase difference between the reproduced data signal and the clock output is in the range of -90 degrees to 90 degrees. When the phase difference is out of the range, a signal is sent from the flip-flop 20 to the charge pump 9 to operate so that the current amount of the charge pump increases. When the phase difference is within the above range, no signal is sent from the flip-flop 20 to the charge pump 9, and the charge pump operates based on the output of the phase comparator 4.

Therefore, the PLL of the third embodiment
FIG. 5 shows the loop gain characteristic (phase difference comparison characteristic) of the circuit.
The nonlinear characteristic shown in FIG.

That is, when the phase difference between the reproduced data signal and the clock output is within the range of -90 degrees to +90 degrees, the characteristic is linear, and when the phase difference is outside the range, the loop gain increases. ing.

As a result, the PLL of the third embodiment
As with the first embodiment, the circuit can increase the capture range and reduce clock jitter during phase synchronization.

FIG. 6 shows the configuration of a fourth embodiment of the PLL circuit according to the present invention. P of the fourth embodiment
The LL circuit is the same as the PLL circuit of the third embodiment shown in FIG.
Instead of using an exclusive OR circuit 19.
The exclusive OR circuit 19 delays the output of the frequency divider 14, that is, the clock output, by １ ／ clock based on the output of the VCO 12 and the output of the frequency divider 14.

Therefore, the PLL of the fourth embodiment
It goes without saying that the circuit also has the same effect as the PLL circuit of the third embodiment.

Next, a specific example of the charge pump used in the above embodiment will be described. FIG. 7 shows the configuration of a first specific example of the charge pump. The charge pump of the first specific example is of a fixed current type, and includes a constant current source 31;
Switches 32 and 33 and a constant current source 34 are provided.
These constant current source 31, switch 32, switch 33,
The constant current source 34 is connected in series, and one end of the loop filter 10 is connected to a connection point between the switch 32 and the switch 33. The switch 32 can be realized by a PNP-type bipolar transistor.

Assume that the current values of the constant current sources 31 and 34 are both I. During the charging operation, the switch 32 is turned on and the switch 33 is turned off. Then, the current I flows into the loop filter 10. On the other hand, at the time of the discharge operation, the switch 31 is turned off and the switch 33 is turned on. Then, a current −I flows through the loop filter 10. When neither the charging operation nor the discharging operation is performed, the switches 32 and 33 are both turned off.

Therefore, the operation of the first specific example is as follows.

Normally At the time of charging At the time of discharging Switch 32 OFF ON OFF switch 33 OFF OFF ON filter current 0 I−I Next, FIG. 8 shows the configuration of a second specific example of the charge pump. The charge pump of the second specific example is of a fixed current type, and includes constant current sources 31, 34, and 37, a switch 33,
36.

The constant current source 31, the switch 33, and the constant current source 34 are connected in series. The switch and the constant current source 37 constitute a series circuit, and this series circuit is connected in parallel with the series circuit including the switch 33 and the constant current source 34. One end of the loop filter 10 is
It is connected to a connection point between the constant current source 31 and the switches 33 and 36.

It is assumed that the current values of the constant current sources 31, 34 and 37 are all I. During the charging operation, the switches 33, 3
6 are both turned off. Then, the current I flows from the constant current source 31 into the loop filter 10. During the discharge operation, both the switches 33 and 36 are turned on. Then, the current I flowing from the constant current source 31 and the current 2I extracted from the constant current sources 34 and 37 are supplied to the loop filter 10.
And a current -I having a difference from the current flows. When neither the charging operation nor the discharging operation is performed, the switch 33 is turned on and the switch 36 is turned off. At this time, since the current I flowing from the constant current source 31 is equal to the current I drawn from the constant current source 34, no current flows through the loop filter 10.

Therefore, the operation of the charge pump of the second specific example is as follows.

Switch 33 ON OFF ON switch 36 OFF OFF ON filter current 0 I-I Normal time At the time of discharging At the time of discharging The switch 33 of the second specific example can be composed of an NPN type bipolar transistor.

Next, the configuration of a third specific example of the charge pump is shown in FIG. The charge pump of the third specific example is of a fixed current type, and the output of the loop filter 10 is a differential output. The third specific example is a constant current source 3
1, 34, 35 and 37 and switches 33 and 36 are provided. It is assumed that the current values of the constant current sources 31, 34, 35, and 37 are the same.

During the charging operation, the switches 33 and 36 are both connected to the R side, that is, to the constant current source 35. At this time, the current of the constant current source 31 flows to the constant current sources 34 and 37 via the loop filter 10, and the current of the constant current source 35 directly flows to the constant current sources 34 and 37. Therefore, the current I flows through the loop filter 10.

During the discharge operation, the switch 3
3 and 36 are both connected to the L side, that is, to the constant current source 31 side. At this time, the current of the constant current source 31 flows directly to the constant current sources 34 and 37, and the current of the constant current source 35 flows to the constant currents 34 and 37 via the loop filter 10. As a result, the current -I flows through the loop filter.

When neither the charging operation nor the discharging operation is performed, the switch 33 is connected to the L side, and the switch 36 is connected.
To the R side. Then, the current of the constant current source 31 directly flows to the constant current source 34, and the current of the constant current source 35 directly flows to the constant current source 37, so that no current flows to the loop filter 10.

The operation of the charge pump of the third specific example is as follows.

Normally At the time of charge At the time of discharge Switch 33 LRL switch 36 RRL filter current 0 I-I The charge pumps of the first to third specific examples are the same as those of the first or second embodiment. Used for PLL circuits.

Next, the configuration of a fourth specific example of the charge pump is shown in FIG. The charge pump according to the fourth specific example is of a variable current type capable of changing the magnitudes of the charge current and the discharge current, and includes constant current sources 41, 44, 45, and 48, and switches, 43, and. 4
6, 47. The current values of the constant current sources 41 and 44 are both I, and the current values of the constant current sources 45 and 48 are both I ′.

The relationship between the state of each switch of the charge pump of the fourth embodiment and the current flowing through the loop filter 10 is as follows. Switch 42 OFF ON OFF ON OFF OFF OFF Switch 46 OFF OFF ON ON OFF OFF OFF Switch 43 OFF OFF OFF OFF ON OFF ON Switch 47 OFF OFF OFF OFF OFF ON ON Filter current 0 II 'I + I' -I -I ' -(I + I ') Here, if I' = I, the charge of the charge pump,
The discharge current value can be changed in two stages of -2I, -I, 0, I, and 2I. Also, I '= 2
If I, -3I, -2I, -I, 0, I, 2I, 3
I and three stages.

Next, the structure of a fifth specific example of the charge pump is shown in FIG. The charge pump of the fifth specific example is of a variable current type, and includes constant current sources 51, 53, 55,
57, 59 and switches 52, 54, 56, 58. The current value of the constant current source 51 is I + I ', the current values of the constant current sources 53 and 57 are I, and the constant current sources 55 and 59
Is a current value of I ′. The relationship between the state of each switch of the charge pump of the fifth specific example and the current flowing through the loop filter 10 is as follows. Switch 52 ON OFF ON OFF ON ON ON Switch 54 ON ON OFF OFF ON ON ON Switch 56 OFF OFF OFF OFF ON OFF ON Switch 58 OFF OFF OFF OFF OFF ON ON Filter current 0 II 'I + I' -I -I ' -(I + I ') Here, if I' = I, the charge and discharge currents change in two steps as in the fourth embodiment, and I '= 2I
Then, it is possible to change in three stages.

Next, the configuration of a sixth specific example of the charge pump is shown in FIG. The charge pump of the sixth specific example is of a variable current type, and the output of the loop filter 10 is a differential output. This charge pump includes constant current sources 60, 61, 63, 65, 67, 69 and switches 62, 64, 66, 68. Here, the current values of the constant current sources 60 and 61 are both I + I ′, and the current values of the constant current sources 63 and 67 are both I.
Both the current values of 69 are I '. The state of each switch of the charge pump of the sixth specific example and the loop filter 1
The relationship with the current flowing to 0 is as follows.

Switch 62 LLRLLLLL Switch 64 LLRRLLLL Switch 66 RRRRRL Switch 68 RRRRRL Filter Current 0 II ′ I + I ′ -I -I '-(I + I') Here, if I '= I, the charge and discharge currents change in two steps as in the fourth example, and if I' = 2I, they change in three steps. It becomes possible.

The charge pumps of the fourth to sixth specific examples can be used for the PLL circuit of the third or fourth embodiment.

[0069]

As described above, according to the present invention, the capture range can be made as wide as possible, and the clock jitter at the time of phase synchronization can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a characteristic graph illustrating the operation of the first embodiment.

FIG. 3 is a block diagram showing a configuration according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration according to a third embodiment of the present invention.

FIG. 5 is a characteristic graph illustrating the operation of the third embodiment.

FIG. 6 is a block diagram showing a configuration according to a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a first specific example of a charge pump according to the present invention.

FIG. 8 is a circuit diagram showing a configuration of a second specific example of the charge pump.

FIG. 9 is a circuit diagram showing a configuration of a third specific example of the charge pump.

FIG. 10 is a circuit diagram showing a configuration of a fourth specific example of the charge pump.

FIG. 11 is a circuit diagram showing a configuration of a fifth specific example of the charge pump.

FIG. 12 is a circuit diagram showing a configuration of a sixth specific example of the charge pump.

FIG. 13 is a block diagram showing a configuration of a conventional PLL circuit.

FIG. 14 is a timing chart illustrating the operation of a conventional PLL circuit.

FIG. 15 is a characteristic graph illustrating the operation of a conventional PLL circuit.

[Explanation of symbols]

2 Frequency comparators 4, 4 _i (i = 1, 2) Phase comparators 4a, 4b, 18, 20 Flip-flops 4c, 4d, 4e, 5a, 5b AND circuit 5 Logic circuit 6 Selector circuit 6a, 6b, 6c Switch 8, 8 _i (i = 1, 2), 9 Charge pump 10 Loop filter 12 Voltage controlled oscillator (VCO) 14 Divider 15, 16 Inverter 19 Exclusive OR circuit

Claims (8)

[Claims] A voltage-controlled oscillating means for outputting a clock signal corresponding to an input voltage; a frequency-dividing means for dividing the output of the voltage-controlled oscillating means by n; a frequency of a reference clock and an output of the frequency-dividing means; Frequency comparing means for comparing a frequency and outputting a signal corresponding to the frequency difference; and a first phase for comparing a phase of the reproduced data signal and an output of the frequency dividing means and outputting a signal corresponding to the phase difference. Comparing means; selecting means for selecting an output signal of the frequency comparing means or an output signal of the first phase comparing means based on a control signal; and determining whether the frequency difference or the phase difference is based on the output of the selecting means. An input voltage control means for controlling an input voltage of the voltage control oscillation means so as to be zero; a predetermined clock based on an output of the frequency division means based on an output of the voltage control oscillation means and an output of the frequency division means. Delay means for outputting a delayed signal; level detection means for detecting the level of the output of the delay means at the time of rising or falling as a reference time of the reproduced data signal; and a loop based on the output of the level detecting means. A PLL circuit, comprising: a loop gain changing means for changing a gain. 2. The frequency dividing means divides the output of the voltage controlled oscillator by two, the delay means outputs a signal delayed by 1/4 clock from the output of the frequency dividing means, and the loop gain changing means. Is such that the loop gain is not changed when the phase difference between the reproduced data signal and the output of the frequency dividing means is in the range of -90 degrees to 90 degrees, and is increased when the phase difference is in the other range. 2. The PLL circuit according to claim 1, wherein the PLL circuit operates. 3. The input voltage control means includes: a loop filter connected to an input terminal of the voltage controlled oscillation means; a current flowing into the loop filter based on an output of the selection means; 3. The PLL circuit according to claim 1, further comprising: a first charge pump that controls the input voltage applied to an input terminal of the voltage-controlled oscillating means by extracting the input voltage. 4. The apparatus according to claim 1, wherein said first charge pump is of a variable current type, and said loop gain changing means controls a current of said first charge pump based on an output of said level detecting means. Item 3. The PLL circuit according to Item 3. 5. The loop gain changing means compares a phase of the reproduced data signal with a signal obtained by inverting a clock signal output from the voltage controlled oscillating means, and outputs a signal corresponding to a phase difference between these signals. A second phase comparison unit that outputs the first phase comparison unit; a logic circuit that performs an AND operation of an output of the second phase comparison unit and an output of the level detection unit; A switch means that is turned on only when an output signal is selected and allows the output of the logic circuit to pass therethrough, based on an output of the logic circuit obtained through the switch means, to flow a current into the loop filter, A second charge pump for controlling the input voltage applied to the voltage controlled oscillator by extracting current from a loop filter. PLL circuit of claim 3, wherein. 6. The delay means comprises: an inverter for inverting the output of the voltage controlled oscillation means; and a D-type flip-flop to which the output of the inverter is input as a clock signal and the output of the frequency dividing means is input to a D terminal. The PLL circuit according to any one of claims 1 to 5, further comprising: 7. The PL according to claim 1, wherein said delay means is an exclusive OR circuit.
L circuit. 8. The level detecting means includes a D-type flip-flop in which a signal obtained by inverting an output signal of the voltage controlled oscillating means is input as a clock, and an output of the delay means is input to a D terminal. The PLL circuit according to any one of claims 1 to 7, wherein: