JPH046914A - Pll device - Google Patents

Abstract

PURPOSE:To enhance the pulling-in capability of a PLL and to suppress the frequency fluctuation of a clock signal when jitter is present on an input signal DIN at the time of the locking of the PLL by changing an output voltage into a voltage different from a voltage before the locking of the PLL is detected when the locking of the PLL is detected. CONSTITUTION:When an input signal DIN and the oscillated clock of a VCO 14 are locked from the unlocked state and the lock of the PLL is detected, a voltage control circuit 18 changes the reference voltage of a differential amplifier of an LPF 23 into a voltage different from a voltage before the locking is detected. Thus, when the PLL is locked, a loop gain is increased to enhance the pulling-in capability of the PLL is increased and when the PLL is locked, a VAR current is decreased to decrease a loop gain when a charging pump capacitor 5 is discharged. Moreover, clock jitter is suppressed even the DIN includes jitter at the locking of the PLL so as to prevent unlocking.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a rotary head digital audio tape recorder (hereinafter referred to as R-DA) capable of recording 100 digital inputs.
PL of a digital recording or reproducing device, such as a digital amplifier capable of reproducing digital input signals.
This relates to the L device.

BACKGROUND OF THE INVENTION FIG. 4 shows a block diagram of a PLL device for receiving digital input data (hereinafter referred to as DIN) of this conventional R-DAT. 1 is a voltage controlled oscillator (hereinafter referred to as VC) whose output signal is CLKl, which is a clock synchronized with DIN.
1.2 is a divider that outputs CLK2 which is obtained by dividing CLKl by 2, and 3 is a RE F 1.2 which receives DIN and CLK2 as input and serves as a charge signal for the charge pump.
A phase comparator 4 outputs the @ signal (hereinafter abbreviated as REF1) and the VAR1 @ signal (hereinafter abbreviated as VAR1) as a charge pump discharge signal.
This is a low-pass filter (hereinafter referred to as I, PF) 4 which receives Fl as an input signal and outputs a frequency control voltage of vCQl. The LPF4 has the following configuration. 6 is a charge pump capacitor, 6 is a resistor that limits the charging current of capacitor 5, T is a resistor that limits the discharge current of capacitor 5, 8 is a resistor that changes the gain and cutoff frequency of LPF 4, and 9 is a resistor that changes the cutoff frequency. The variable capacitor 10 is the bias resistance of the transistor 13. 11, 12, and 13 are NPN) transistors that constitute the inverting amplifier of LPF3. Further, the base of the transistor 110 is defined as a point A.

FIG. 4 shows a timing chart when the conventional PLL is synchronized. As shown in Figure 4, VA
Rl is high impedance from the rising edge of DIN to the rising edge of CLKl when it is not Ov and other times. REFl is 5 during the next high level (6v) of CLK2 after VAR1 becomes Ov. ■, and becomes high impedance at other times.

A conventional PLL device configured as follows will be explained.

The operation when the PLL is synchronized will be explained. Fourth
As shown in the figure, VARl is oV from the rising edge of DIN to the rising edge of CLKl, and is high impedance at other times REFlu, VAR1
From 7%OVK r-r to the next CLK2 high level (5
v), it becomes 5V, and becomes high impedance at other times. Next, in FIG. 3, each transistor 11.1
2゜13 is in the activated state, so each transistor f
1, 12. Assuming that the bake emitter voltage (hereinafter abbreviated as VBE) of 13 is equal to j7, the voltage at point A is V = 3 - VBE
- fixed at about taV. The voltage at point A is constant regardless of whether the PLL is synchronous or asynchronous. When REFl, which is the output of the phase comparator 3, is 6■, the current flowing through the resistor 6 -(6
~3·VBE)/R1 (R1 is the resistance value of the resistor 6).

Since the gain of the inverting amplifier composed of the transistors 11, 12, and 13 is infinite, all the current flowing through the resistor 6 flows from the point A to the capacitor 5, and the capacitor 5 is charged. VAR1, which is the output of phase comparison 3g3, is oV
At O time, the current flowing through the resistor 7 = 3-VRE/R2 (R2 is the resistance value of the resistor 7), and as before, all the current flowing from the capacitor 5 to A flows to the resistor 7, and the capacitor 5 is discharged. Ru. REFl, VAR
When both the resistors 1 and 1 are at high impedance, no current flows through either the resistors or the resistor T, so the charge in the capacitor 6 is held.

The above operations are repeated at the timing shown in FIG. 4, and the frequency control voltage of the VCOI is controlled.

Problems to be Solved by the Invention However, in the above configuration, when the loop gain is increased to increase the PLL's pull-in ability, the PLL
If there is jitter in DIH when synchronizing, the oV of VAR1
Since the O width changes, the discharge time of the capacitor 6 changes, and the frequency fluctuation of the vCol output clock increases due to the high loop gain, which has the problem of increased jitter and the problem of becoming easily out of synchronization. was.

In view of this, an object of the present invention is to provide a PLL device that suppresses clock frequency fluctuations when there is jitter in the DIH during synchronization of the PLL, even if the loop gain of the PLL is increased, in order to improve the pull-in ability of the PLL. do.

The only way to solve the problem is to use vCo which oscillates a clock synchronized with DIN, a phase comparator which outputs N phase comparison signals by inputting the oscillation clocks of DIN and VCO, and an asynchronous oscillation clock of DIN and VCO. When synchronizing from the state, as soon as PLL synchronization is detected, a voltage control circuit changes the output voltage to a voltage different from the voltage before synchronization is detected, and N phase comparison signals that are the output of the phase comparison section. and a low-pass filter composed of an inverting amplifier whose input stage is a differential amplifier whose input signal is the output voltage of the voltage control circuit.
It is a device.

Effects The present invention has the following effects due to the above-described configuration.

When synchronizing the oscillation clocks of DIN and VC○ from an asynchronous state using PLL, as soon as PLL synchronization is detected,
When the voltage control circuit synchronizes the PLL by changing the reference voltage of the differential amplifier of the low-pass filter to a voltage different from the voltage before synchronous detection, the loop gain is increased and the PLL is pulled in. ability can be improved, P
When LL is synchronized, by reducing the VAR current and lowering the loop gain during dinu charging of the charge pump capacitor, there is jitter in DIN and VAR (
7) Even if the OVO width fluctuates, the clock frequency fluctuation can be suppressed, and even when there is jitter in DIN, the clock jitter can be suppressed and synchronization will not be lost.

Embodiment FIG. 1 shows a configuration diagram of a PLL for DIN reception of an R-DAT using a PLL device in an embodiment of the present invention. 14 is CLK which is a clock synchronized with DIH
VC○ whose output signal is 3, 16 is a 4 frequency divider which outputs CLK4 which is the frequency of CLK3 divided by 4, 16 is DIN and CLK
4 as input, the REF2 signal (hereinafter abbreviated as REF2) as the charge pump charge signal and the VAR2 signal (hereinafter referred to as VAR2) as the charge pump discharge signal.
17 is a phase comparator that outputs DIN and C
A PLL synchronization detection circuit takes LK4 as an input and outputs a PLL synchronization detection signal of DIN and CLK3. 18 uses the PLL synchronization detection signal as an input signal to synchronize the PLI from an asynchronous state, as soon as PLL synchronization is detected. To,
This voltage control circuit 18 is a voltage control circuit that makes the output voltage smaller than the voltage before synchronous detection, and has the following configuration. 19, 20, and 21 are resistors for voltage division of 5V, respectively. 22 is set to 0N by the PLL synchronization detection signal.
This is a 10FF transistor.

23 is an LPF that outputs the frequency control voltage of the VCO 14 using VAR2, REF2 and the voltage control circuit 18 as input signals.
It is. The LPF 23 has the following configuration. 5 is a charge pump capacitor, 6 is a resistor that limits the charge current of capacitor 6, 7 is a resistor that limits the dinu charge current of capacitor 5, 8 is a resistor that changes the gain and cutoff frequency of LPF 3, and 9 is a cutoff frequency 24 is an operational amplifier which is an inverting amplifier of LPF23.

The operation of the PLI and device of this embodiment configured as described above will be explained below. First, the operation when synchronizing the PLL will be explained. The PLL synchronization detection signal, which is the output of the PLL synchronization detection circuit 17, becomes Ov since it is asynchronous, and the transistor 22 is turned off and the resistor 21
Since no current flows through the operational amplifier 2, the voltage v1 determined by the resistor voltage division ratio of the resistor 19 of the voltage control circuit 18 and the resistor 2° is
It is output to the manual input of 4. Since the voltage of manual input to the operational amplifier and that of one person's input are equal, -manual input becomes the voltage v1.

VAR when synchronized by synchronizing PLL under those conditions
A timing chart of REF2 and REF2 is shown in FIG.

As shown in Figure 2, VAR2 becomes Ov from both edges of DIN to the rising edge of CLK4, and is high impedance at other times. 5■) between 6v
and becomes high impedance at other times.

Since the loop gain is increased to improve the PLL pull-in ability, the OV interval t of VAR2 is shorter than the half cycle of CLK4. After the PLL is synchronized,
The PLL synchronization detection signal, which is the output of the PLL synchronization detection circuit 17, is 5V because it is synchronized.The transistor 22 is turned on and current flows through the resistor 21, so the voltage control circuit 1
Since the output voltage of the resistor 8 is determined by the voltage division ratio of the combined resistance of the resistor 19, the resistor 2o, and the resistor 21, a voltage v2 lower than the voltage v1 is inputted to the manual input of the operational amplifier 24. Since the manual input voltage of the operational amplifier 24 and the voltage generated by one person are equal, -
The voltage of human power becomes the voltage v2. Since the gain of the operational amplifier 24 is infinite, all the current flowing from the capacitor 6 to the single power of the operational amplifier 24 flows through the resistor 7 and the capacitor 5 is discharged. At this time, MAR2N current flowing through resistor 7 = V2/R2 (R21ti resistor 7 (D
(mM value), the VAR2 current becomes smaller than when the voltage v1 described in Table 11 is inputted to the manual input of the operational amplifier 24. VAR2 and R when the PLL is synchronized under the condition that the voltage of the operational amplifier 24 is the voltage (2) above.
The timing chart of EF2 is shown in FIG. VAR
2 current is smaller, the time when VAR2 is OV is no longer t+Δt, and the voltage of the operational amplifier 24 shown in FIG. Therefore, as shown in FIG. 3, the period in which VAR2 is OV and the period in which REF2 is 5V (7) overlap by time tc. During tc, the amount of current in the capacitor 6 becomes very small, so the loop gain becomes significantly small by the amount of tc. As described above, according to this embodiment, the voltage manually input to the operational amplifier 24 when the PLL is synchronized is lowered by the voltage control circuit, compared to when the PLL is synchronized by the PLL synchronization detection signal.
When synchronizing L, the loop gain can be increased to widen the PLL capture range, and when the PLL is synchronized, the VAR current can be reduced to lower the loop gain when discharging capacitor 5. Even if there is jitter on DIN and the 070 width of VAR fluctuates, the clock frequency fluctuation can be suppressed, and even when there is jitter on DIN, the clock jitter can be suppressed and synchronization will not be lost.

The phase comparator 16 of this embodiment has a second section 1. As can be seen from the timing chart in FIG. 3, both edges of DIN are detected and current is applied to VAR2 and REF2. In the case of the double edge detection method, the detection sensitivity is increased and the PLL pull-in performance is better than the single edge detection method such as the phase comparator 3 shown in the conventional example, but when the PLL is synchronized, the duty of the DIN data When the ratio changes significantly,
Since the OVO width of VAR2 differs greatly between the rising edge and the falling edge of DIN, the frequency fluctuation of the PLL clock becomes large and the PLL synchronization tends to be lost.

According to this embodiment, as shown in FIG. 3, even with both edge detection methods, during PLL synchronization, VAR2 is OV period and
Since the periods in which EF2 is 5V overlap by the time interval tc, the loop gain can be significantly reduced by tc, and D
Even if the duty ratio of IN data changes greatly, the frequency fluctuation of the PLL clock is small and synchronization does not occur. Therefore, when the PLL device of the present invention is combined with a phase comparator for both edge detection methods to configure a PLL as in this embodiment, the pull-in ability of the PLL is higher than that of the single edge detection method, and the The detection method problem can be solved, and the performance is superior in all respects to a PLL configured with a single edge detection method phase comparator.

Effects of the Invention As explained above, according to the present invention, when synchronizing a PLL with a small number of parts, the loop gain is increased and the PLL is
It is possible to improve the ability to pull in L, and when the PLL is synchronized, if there is no jitter in DIN, it goes without saying that even if there is jitter in DIN, clock jitter can be suppressed and synchronization will not be lost. Furthermore, even in a PLL configured with phase comparators of both edge detection methods, the DI
By suppressing clock frequency fluctuations even if the duty ratio of N data changes significantly, clock jitter can be suppressed and synchronization can be prevented. P composed of
A PLL in which the LL is configured with a single edge detection type phase comparator.
It can improve performance in all aspects, and its practical effects are significant.

[Brief explanation of drawings]

FIG. 1 shows the DIN of an R-DAT according to an embodiment of the present invention.
A block configuration diagram of a PLL device for reception, Fig. 2 is a timing chart immediately after synchronization of the PLL in this embodiment, and Fig. 3 is a timing chart during PLL synchronization in this embodiment - Fig. 4 is the conventional R-DAT
FIG. 5 is a block diagram of a PLL device for DIN reception, and a timing chart at the time of PLL synchronization in a conventional example. 6.9... Capacitor, 6,7.8...
・Resistance, 14...VCo, 1s...4
Frequency divider, 16/old...phase comparator, 17...P
LL synchronization detection circuit, 18... Voltage control circuit, 1
9, 20, 21...Song/Resistance, 22...Condensation? , 23... LPF, 24... operational amplifier. Name of agent: Patent attorney Shigetaka Awano (1 person)
EFlsi. −−m−−−−−−−ryou−−−−−
1-----CL K 2 ” αV

Claims (1)

[Claims] In order to receive digital input data for a digital interface, a voltage controlled oscillator that oscillates a clock synchronized with the digital input data, and a voltage controlled oscillator that uses the digital input data and the oscillation clock of the voltage controlled oscillator as input, N When synchronizing the digital input data and the oscillation clock of the voltage controlled oscillator from an asynchronous state to a phase comparison section that outputs a phase comparison signal (an integer of 1 or more), as soon as PLL synchronization is detected, the output voltage is changed. A voltage control circuit that changes the voltage to a voltage different from the voltage before detecting synchronization, and an inversion circuit whose input stage is a differential amplifier whose input signals are the N phase comparison signals output from the phase comparison section and the voltage. A PLL device comprising a low-pass filter configured with an amplifier.