JPH0613896A - Phase locked loop - Google Patents

Abstract

PURPOSE:To provide a phase locked loop with improved phase locked loop characteristics provided with the charge pump of low power consumption by generating an average DC current based on a phase lead signal and a phase lag signal. CONSTITUTION:An average current output charge pump 102 is constituted of a control signal generating circuit 101, pulse width/voltage conversion circuits 302 and 303 and a voltage/current conversion circuit 304 of differential input. The control signal generating circuit 101 generates TINC, TDEC and TRESET signals from an INC signal 106 and a DEC signal 107. The pulse width of the TINC is converted to the voltage at the pulse width/voltage conversion circuit 302 and the pulse width of the TDEC is converted to the voltage at the pulse width/voltage conversion circuit 303. The voltage/current conversion circuit 304 receives the output voltages VINC and VDE of the pulse width/voltage conversion circuits 302 and 303 by the differential input and outputs the average current (DC current) 108 corresponding to the electric potential difference.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit used in a recording data reproducing apparatus for decoding and reproducing a data signal recorded on a recording medium such as a magnetic disk.

[0002]

2. Description of the Related Art In a magnetic disk device or the like, a phase synchronizing circuit used for reproducing a recording data signal generally has a conventional block structure shown in FIG. 7, and a time chart showing its operation is shown in FIG. .

A phase comparator 101 compares the phase of an input signal 105 with a phase of a VCO clock 110 output from a voltage controlled oscillator (VCO) 104, and when the phase of the input signal 105 leads the phase of the VCO clock 110. The INC signal 106 is output for that time, and the DEC signal 107 is output when the time is delayed. The charge pump 2 receives the INC signal 106 and the DEC signal 107, and performs a charging operation according to the INC signal 106 by D
The discharge operation is performed according to the EC signal 107. The loop filter 103 integrates and smoothes the output 8 of the charge pump 2 to generate the VCO control voltage 109. VCO1
04 is a VC having a frequency corresponding to the VCO control voltage 109.
The O clock 110 is output. In this way, the phase synchronization circuit operates and the phase of the VCO clock 110 is changed to the input signal 1
Match the phase of 05.

As the phase comparator 101, a frequency phase comparator may be used in addition to the normal phase comparator. The frequency / phase comparator is used at the time of synchronization pull-in, and for example, as shown in FIG.
It can be configured by 93 and a frequency dividing circuit 94. The input signal 105 is input to the CK terminal of the flip-flop 91, and the VCO clock is input to the CK terminal of the flip-flop 92 so that the frequency of the input signal 105 becomes equal to that of the input signal 105 by the frequency dividing circuit 94 (here, 3 frequency dividing circuit). The divided clock 95 obtained by dividing 110 is input.

The operation of this circuit will be described with reference to FIG. When the phase of the input signal 105 is ahead of the divided clock 95, the INC signal 106 rises at the rising edge of the input signal 105 and the divided clock 95
At the rising edge of, the DEC signal 107 rises, the NAND output 96 becomes "L" level, the flip-flops 91 and 92 are reset, and the INC signals 106 and D
The EC signal 107 falls. On the contrary, when the phase of the input signal 105 is behind the divided clock 95, the DEC signal 107 is first generated at the rising edge of the divided clock 95.
Rises, the INC signal 106 rises at the rise of the input signal 105, the NAND output 96 becomes "L" level, the flip-flops 91 and 92 are reset, and the INC signal 106 and the DEC signal 107 fall.

The frequency division ratio of the frequency dividing circuit is determined by the data signal pattern (sync pattern) at the time of synchronization pull-in, and differs depending on the recording code system. The sync pattern of 2-7RLLC is a 4T pattern of "10001000 ...", and the sync pattern of 1-7RLLC is "100100."
It is a 3T pattern of "...".
-7RLLC divides by 4, and 1-7RLLC divides by 3.

[0007]

In the magnetic disk, the length of the sync pattern at the time of synchronous pull-in is determined by the format, and is usually as short as about 10 bytes. For this reason, in the above-mentioned conventional technique, in order to complete the pull-in in a short time, the charge pump current is often set to a large value, resulting in an increase in power consumption.

Further, there is a time difference detection circuit disclosed in Japanese Patent Laid-Open No. 62-256520 as a prior art of a circuit for converting a phase comparison output into a direct current. However, this circuit requires a special phase comparator, It has problems such as a narrow range and is not suitable for synchronization pull-in. Also,
There are also problems that the current sources for integration of the two input signals are configured with P polarity on one side and N polarity on the other side, the characteristics do not match, and an offset is likely to occur because the integration result is not differentially converted into a current.

It is an object of the present invention to reduce the power consumption of a charge pump, particularly to reduce the power consumption at the time of synchronization pull-in, and to directly connect to a conventional phase comparator, frequency phase comparator or the like to obtain good phase synchronization characteristics. An object of the present invention is to provide a phase locked loop circuit equipped with a charge pump.

[0010]

In order to achieve the above object, according to claim 1 of the present invention, the phase of an input signal is compared with the phase of an oscillation signal of a voltage controlled oscillator or a frequency-divided signal thereof to obtain a phase. A phase comparator that outputs a lead signal and a phase delay signal and a charge operation according to the phase lead signal by receiving the phase lead signal and the phase delay signal and a discharge operation according to the phase delay signal and responding to the phase difference In a phase-locked circuit consisting of a charge pump that outputs a current signal and a loop filter that integrates this output current and converts it into a voltage and outputs it as the control voltage of the voltage-controlled oscillator,
The circuit configuration of the charge pump includes a first integrating circuit for converting the pulse width of the phase lead signal into a voltage, a second integrating circuit for converting the pulse width of the phase delay signal into a voltage, and the first and second The control signal generation circuit that generates a signal that resets the integrated value of each integration circuit immediately before the integration circuit starts integration, and the output voltage of the first and second integration circuits described above is received by a differential input. The voltage-current conversion circuit outputs an average DC current according to the voltage difference.

According to another aspect of the present invention, the first integrator circuit and the second integrator circuit have the same circuit configuration, and
A first capacitor for both integration and holding, and a first capacitor that is turned on for a time corresponding to the pulse width of the phase lead signal or the phase delay signal to charge the capacitor with a constant current to convert the pulse width into a voltage. A switch and a second switch that is turned on just before starting integration by the reset signal generated by the control signal generation circuit and resets the voltage of the capacitor to an initial value.

According to another aspect of the present invention, the control signal generation circuit delays the phase advance signal by a first set time td1 and the phase delay signal is delayed by a second set time td2. A second delay circuit for causing the phase advance signal or the phase delay signal, whichever is first input to the rising edge of the signal, causes the Q output to become "High", and outputs the Q output as a generation reset signal, and A third delay circuit for sending a state inversion signal to the flip-flop so that the ON time width of the generation reset signal becomes the third set time td3, and the td3 is the first and second integration circuits. Is set so that the integrated value of the phase reset signal can be reset. For td1 and td2, the phase advance signal and the phase delay signal rise after the generation reset signal is turned off. It is set to.

[0013]

In the charge pump according to the present invention, the average current continues to be output until the next phase comparison, so that the same gain can be obtained with a smaller current setting and the power consumption is lower than the conventional pulse current output. In addition, the size of the transistor can be reduced and the cost is low. Further, since the ripple of the loop filter output voltage is reduced, the loop characteristics can be stabilized and the input dynamic range of the VCO may be small. Further, unlike the time difference detection circuit, a special phase comparator is not required, and a capture range can be widened by combining with a frequency phase comparator or the like.

Further, since the integrator circuits having the same structure are provided for the two input signals and the current is differentially converted,
The current offset can be reduced.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an embodiment of a phase locked loop circuit according to the present invention. It is composed of a phase comparator 101, an average current output charge pump 102, a loop filter 103, and a VCO 104. The operation of this circuit will be described with reference to FIG. The phase comparator 101 has an input signal 105 and a VCO clock 110.
Of the input signals 105 are advanced, the INC signal 106 is output, and when the phase of the VCO clock 110 is advanced, the DEC signal 107 is output. The average current output charge pump 102 uses the INC signal 1
06 and the pulse width of the DEC signal 107 are integrated, an average current corresponding to the difference between the integration results is output to the next signal input, the loop filter 103 integrates and smooths the current, and the control voltage of the VCO 104 is reached. Is output.

In the conventional charge pump, the INC signal 1
06, since the current is output only for the time of the pulse width of the DEC signal 107, a pulse current output as indicated by the dotted line is obtained. Since the current gain is the time integration of the output current, the average current output charge pump requires a smaller current than the conventional charge pump for the same current gain. Also, the ripple of the loop filter voltage generated by the pulse current can be reduced,
It is possible to stabilize the PLL loop characteristic.

Next, one embodiment of the average current output charge pump 102 is shown in FIG. It is composed of a control signal generation circuit 301, pulse width-voltage conversion circuits 302 and 303, and a differential input voltage-current conversion circuit 304. The control signal generation circuit 301 outputs the T signal from the INC signal 106 and the DEC signal 107.
Three signals of INC, TDEC and TRESET are generated. The pulse width-voltage conversion circuit 302 converts the TINC pulse width, and the pulse width-voltage conversion circuit 303 converts the TDEC pulse width into a voltage. The voltage-current conversion circuit 304 outputs the output voltages VINC and VDE of the pulse width-voltage conversion circuits 302 and 303.
C is received by a differential input, and an average current (DC current) 108 corresponding to the potential difference is output.

A concrete embodiment of the average current output charge pump 102 is shown in FIG. Pulse width-voltage conversion circuit 302
Is composed of current sources 11 and 13, switches S1 and S3, a capacitor C1, and a MOS transistor Q1. In this circuit, S1 is turned on for the duration of the pulse width of the input signal,
By charging the capacitor C1, the current is integrated over time and the pulse width is converted into a voltage. S3 is a switch for resetting the voltage of the capacitor to 0V, which is turned on only immediately before the start of integration. With such a timing, one capacitor for integration and one for holding can be shared. The pulse width-voltage conversion circuit 303 also has the same circuit configuration as 302. The pulse width of TINC is TwINC and the pulse width of TDEC is TwDEC
Then, the relationship between the input pulse width and the capacitor charging voltage in this circuit is expressed by the following equation.

[0019]

[Equation 1]

[0020]

[Equation 2]

C1 and C2 perform integration and hold the integration result (charging voltage value). Therefore, make sure that the MOS transistor Q is not affected by the input current of the next stage circuit.
Impedance conversion is performed by 1 and Q2. Q1, Q2
Also serves as a level shifter. The voltage-current conversion circuit 304 includes transistors Q3 to Q10, resistors R1 and R2, and a current source 15. VI in the differential circuit of Q3 and Q4
Converting the potential difference between NC and VDEC into current, Q1 to Q10
It outputs through the current mirror circuit of. When the mirror ratio of the current mirror circuit is N, R1 (= R2) · I5> (V
In the case of INC-VDEC), the relationship between the input potential difference and the output current Io of this circuit is expressed by the following equation.

[0022]

[Equation 3]

Therefore, the input phase difference of the average current output charge pump 102 (INC signal 106 and DEC signal 1
The relationship between the output current and the pulse width difference of (07) is as follows.

[0024]

[Equation 4]

In this average current output charge pump, since the INC signal side and the DEC signal side are completely constituted by the balanced circuit except for the current mirror circuit at the output stage, offset is unlikely to occur. Although the differential circuit is composed of a combination of a bipolar transistor and a resistor in consideration of linearity of current conversion and an input dynamic range, it may be a MOS transistor.

FIG. 5 shows a concrete example of the control signal generation circuit 301. Flip-flop 501, OR gate 50
2 and delay elements 1 to 3. The operation of this circuit and the average current output charge pump 102 shown in FIG. 4 will be described with reference to FIG. INC signal 106 and DEC signal 107
Whichever comes first, the Q edge of the flip-flop 501 becomes "H" due to the rising edge input, and TRES
ET turns on. The pulse width of TRESET is determined by the delay time td3 of the delay element 3, and the capacitors C1 and C2
Set so that can be fully reset. TIN C is IN
C signal 106 is delayed by delay element 1, and TDEC is DE
C signal 107 is a signal delayed by delay element 2,
Set the delay time so that the output starts after RESET is turned off. S1 is turned on for the duration of the pulse width of TINC to charge C1. VINC is the voltage of C1
The voltage is level-shifted by the GS voltage. The TDEC side operates similarly and VDEC is output. The voltage-current conversion circuit receives these two voltages differentially, and the potential difference VINC
Output a current according to VDEC. By changing the average current output charge pumps I1 and I2 and the mirror ratio N, it is possible to deal with different clock frequencies and to have a degree of freedom in gain setting.

[0027]

According to the present invention, the power consumption of the charge pump can be reduced. Further, the ripple of the loop filter output voltage can be reduced, and the PLL loop characteristic can be stabilized. It can be combined with a frequency phase comparator at the time of synchronization pull-in, and a phase lock circuit with a wide capture range can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a phase synchronization circuit according to the present invention.

FIG. 2 is an operation explanatory diagram of the circuit of FIG.

FIG. 3 is a block diagram of an embodiment of a charge pump according to the present invention.

FIG. 4 is a circuit diagram of an embodiment of a charge pump according to the present invention.

5 is a configuration diagram of an embodiment of a control signal generation circuit in FIG.

FIG. 6 is an operation explanatory diagram of the charge pump according to the present invention.

FIG. 7 is a block diagram of a conventional phase locked loop circuit.

FIG. 8 is an operation explanatory diagram of the circuit of FIG. 7.

FIG. 9 is a diagram showing an example of a conventional frequency phase comparator.

FIG. 10 is an operation explanatory diagram of a conventional frequency phase comparator.

[Explanation of symbols]

 101 ... Phase comparator 102 ... Average current output charge pump 103 ... Loop filter 104 ... Voltage controlled oscillator (VCO) 105 ... Input signal 106 ... INC signal 107 ... DEC signal 108 ... Charge pump output current 109 ... Loop filter output voltage 110 ... VCO output clock 301 ... Control signal generation circuit 302, 303 ... Pulse width-voltage conversion circuit 304 ... Voltage-current conversion circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tokunori Karasawa, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside Hitachi Imaging Information Systems (72) Inventor Tsuyoshi Tateyama 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa (72) Incorporated company Hitachi Image Information Systems (72) Inventor Ken Urakami 5-20-1 Kamimizumoto-cho, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Semiconductor Design Development Center (72) Inventor Genhiro Nakai Odawara, Kanagawa Kozu 2880 Address Stock company Hitachi Ltd. Odawara factory

Claims (5)

[Claims] 1. A phase comparator which compares the phase of an input signal with the phase of an oscillation signal of a voltage controlled oscillator or a frequency-divided signal thereof to output a phase advance signal and a phase delay signal, and a phase advance signal and a phase delay. A charge pump that receives a signal and performs a charge operation according to a phase advance signal and a discharge operation according to a phase delay signal to output a current signal according to a phase difference, and an output current that is integrated and converted into a voltage In a phase locked loop circuit including a loop filter that outputs a control voltage of the voltage controlled oscillator, the charge pump includes a first integration circuit that converts a pulse width of a phase lead signal into a voltage and a pulse width of a phase delay signal. A second integrator circuit for converting to a voltage and a signal for resetting the integral value of each integrator circuit immediately before the first and second integrator circuits start integrating A control signal generation circuit and a voltage-current conversion circuit that receives the output voltages of the first and second integration circuits by differential inputs and outputs an average DC current according to the voltage difference. Phase synchronization circuit. 2. The first integrator circuit and the second integrator circuit according to claim 1 have the same circuit configuration, and each of them has one capacitor for integration and holding, and the phase advance signal or phase. The switch is turned on for a time corresponding to the pulse width of the delay signal to charge the capacitor with a constant current to convert the pulse width into a voltage, and the reset signal generated by the control signal generation circuit starts integration. A phase-locked loop circuit comprising a second switch that is turned on only immediately before and resets the voltage of the capacitor to an initial value. 3. The control signal generating circuit according to claim 1, wherein the phase delay signal is delayed by a first set time td1, and the phase delay signal is set by a second set time t.
A second delay circuit that delays by d2, and a flip-flop that outputs the Q output as a generation reset signal because the Q output becomes "High" due to the rising edge of the signal that is input first of the phase lead signal and the phase delay signal. When,
The ON time width of the generation reset signal is set to the third set time t
a third delay circuit for sending a state inversion signal to the flip-flop so as to be d3, and the td3 is set so that the integrated values of the first and second integrating circuits can be reset, and td1 and The td2 is set so that the phase lead signal and the phase delay signal rise after the generation reset signal is turned off. 4. A phase locked loop circuit comprising a charge pump according to any one of claims 1, 2 and 3, which is integrated into a circuit using MOS transistors as constituent elements. 5. A phase locked loop circuit according to claim 4, which is an integrated circuit formed by a BiCMOS process.