JP3263621B2 - PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase) for outputting an oscillation clock of a predetermined frequency synchronized with a reference clock.
Locked Loop) circuit.

[0002]

2. Description of the Related Art In a television, a PLL circuit is used which generates an oscillation clock to be used for synchronous reproduction of a color signal based on a burst clock included in a composite video signal.

The PLL circuit includes a digital circuit system and an analog circuit system. PLL circuit is CMOS
In the case of using a digital circuit having a configuration, a memory for storing data of the oscillation timing of the oscillation clock, a digital filter, a multiplier, and the like are required, and the circuit configuration becomes large-scale. In the case of using a CMOS analog circuit, external components such as a capacitor are required, but the circuit can be downsized.

FIG. 9 shows a CMOS type analog PLL circuit 100 in a conventional television receiver. The PLL circuit 100 includes an exclusive OR (EXOR) circuit 101, a tri-state buffer 102, a charge pump circuit 103 having a CMOS configuration, and a low-pass filter (L
PF) 106, voltage controlled oscillators (VCO) 107 and 1
/ 4 frequency divider 108 is provided.

As shown in FIG. 10, an EXOR circuit 101 inputs a burst clock Rc having a duty ratio of 50% as a reference clock and an output clock Pc having a duty ratio of 50% output from a 1/4 frequency divider 107. . N
In the case of the color television of the TSC (National Television System Commitee) system, the frequency of the burst clock Rc is 3.58 MHz. The EXOR circuit 101 outputs a clock S1 based on a comparison result between the phase of the burst clock Rc and the phase of the output clock Pc. Therefore,
Only when the cycle of the output clock Pc matches the cycle of the burst clock Rc and the phase of the output clock Pc leads the phase of the burst clock Rc by 90 °, the clock S1 is twice as large as the burst clock Rc. The duty ratio becomes 50% in frequency.

[0006] The tri-state buffer 102 receives a control signal RE which rises according to the burst clock period of the composite video signal. When the control signal RE is at “H”, the tristate buffer 102
The output clock S1 of the R circuit 101 is output to the charge pump circuit 103, and when the control signal RE is “L”, the output is in a high impedance state.

The charge pump circuit 103 includes a pMOS transistor 104 and an nMOS transistor 105 connected in series between a power supply and ground. In the charge pump circuit 103, the pMOS transistor 104 and the nMOS transistor 105 are turned on and off only when the control signal RE is "H" by the tristate buffer 102. When the pMOS transistor 104 is on, the current Ip flows from the power supply side to the LPF 106, and the nMO
When the S transistor 105 is on, the current In
Flows from the LPF 106 to the ground side.

The LPF 106 is charged and discharged by the currents Ip and In, and outputs a control voltage Vt in which the clock S 1 is smoothed to the VCO 107. The VCO 107 controls the control voltage Vt
And outputs an oscillation clock Fv having a frequency corresponding to the voltage value. In the case of television, the frequency of the oscillation clock Fv is 14.3181 which is four times the frequency of the burst clock Rc.
8 MHz.

The 分 frequency divider 108 outputs to the EXOR circuit 101 a clock Pc obtained by dividing the frequency of the oscillation clock Fv by ４. The A / D converter 109 samples the composite video signal CV using the oscillation clock Fv as a sampling clock, performs analog-to-digital conversion on each sampled value, and outputs a digital signal S2. The composite video signal CV contains a color difference signal modulated at a predetermined phase, and the sampling operation of the A / D converter 109 extracts this color difference signal.

[0010]

SUMMARY OF THE INVENTION The above-mentioned PLL circuit 100
In the VCO 107, the frequency of the oscillation clock Fv with respect to the control voltage Vt fluctuates due to a temperature change, a fluctuation in the power supply potential, or the like. In order to output a constant frequency oscillation clock Fv from the VCO 107, the control voltage Vt must be changed according to each condition. Here, the charge pump circuit 103 outputs the output clock S of the EXOR circuit 101.
Since the LPF 106 is charged and discharged with the voltage value of 1, the duty ratio of the output clock S1 of the EXOR circuit 101 must be changed to change the control voltage Vt.

For example, as shown in FIG. 11B, when the control voltage Vt is の of the power supply potential, the clock S1 is in an ideal state with a duty ratio of 50%. On the other hand, as shown in FIG. 11A, in order to make the control voltage Vt larger than 1/2 of the power supply potential, it is necessary to make the duty ratio of the clock S1 larger than 50%. 1
As shown in FIG. 1 (c), the control voltage Vt is set to 1 /
To make it smaller than 2, the duty ratio of the clock S1 needs to be less than 50%. In such a case, the difference between the phase of the burst clock Rc and the phase of the clock Pc is 9
As a result, the phase of the oscillation clock Fv deviates from a desired phase.

The oscillation clock Fv out of phase as described above
If the A / D converter 109 performs sampling on the basis of the above, the color signal cannot be accurately reproduced, resulting in a change in hue.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a PLL circuit which can reliably maintain the synchronization between a reference clock and an oscillation clock.

[0014]

In order to achieve the above object, the present invention is directed to a PL for generating an oscillation clock that maintains a constant phase difference with respect to a reference clock having a constant cycle.
An L circuit, a voltage-controlled oscillator that outputs an oscillation clock having a frequency corresponding to the control voltage, a comparison circuit that extracts a phase difference between the oscillation clock and a fixed-cycle reference clock, and outputs a clock based on the phase difference; Select one of the ground potential and the power supply potential in response to the clock output from the comparison circuit, draw a constant current from the output to the ground side by selecting the ground potential, and set a constant current from the power supply side to the output by selecting the power supply potential Controlling a voltage-controlled oscillator by smoothing the output of a charge pump circuit connected to an output of a charge pump circuit for supplying current and repeating a ground potential or a power supply potential in response to a clock output from a comparison circuit in response to a clock output from a comparison circuit A low-pass filter for obtaining a voltage.

According to a second aspect of the present invention, a charge pump circuit includes a first and a second transistor which are turned on and off alternately based on an output clock of a comparison circuit; a constant current source for supplying a constant current; Connected to one transistor,
A first current mirror circuit for supplying a drive current when the first transistor is turned on based on the constant current of the constant current source; and a first current mirror circuit connected to the second transistor and based on the constant current of the constant current source. A second current mirror circuit for flowing a drive current when the second transistor is turned on, and a first current mirror circuit for flowing a drive current when the first transistor or the second transistor is turned on based on a constant current of the constant current source. And the second current mirror circuit, and the first and second current mirror circuits are connected in series to the first transistor and the second transistor, respectively.

According to a third aspect of the present invention, there is provided a PLL circuit for generating an oscillation clock that maintains a constant phase difference with respect to a reference clock having a constant cycle, and a voltage control for outputting an oscillation clock having a frequency corresponding to a control voltage. Take out the phase difference between the oscillator and the oscillation clock with respect to the fixed period reference clock,
A comparison circuit that outputs a clock based on the phase difference, and one of the ground potential and the power supply potential is selected in response to the clock output from the comparison circuit, and a constant current is drawn from the output to the ground side by selecting the ground potential. A first charge pump circuit for supplying a constant current from the power supply side to the output by selecting a power supply potential, and selecting one of the ground potential and the power supply potential in response to a clock output from the comparison circuit; A constant current is drawn from the output to the ground side by selection, a constant current is supplied from the power supply side to the output by selection of the power supply potential, and a second charge having a higher output load driving capability than the first charge pump circuit. A pump circuit and first and second
The output of the first and second charge pump circuits connected to the output of the charge pump circuit and repeating the ground potential or the power supply potential in response to the clock output from the comparison circuit is smoothed to reduce the control voltage of the voltage controlled oscillator. A low-pass filter, a lock detection circuit for detecting whether the oscillation clock maintains a constant phase difference with respect to the reference clock, and a response to the detection result of the lock detection circuit. When the constant phase difference is maintained, the first charge pump circuit is selectively operated, and when the oscillation clock does not maintain the constant phase difference with respect to the reference clock, the second charge pump circuit is activated. And a selection circuit for selectively operating.

According to a fourth aspect of the present invention, there is provided a PLL circuit for generating an oscillation clock that maintains a constant phase difference with respect to a reference clock having a constant cycle, wherein the voltage control outputs an oscillation clock having a frequency corresponding to a control voltage. Take out the phase difference between the oscillator and the oscillation clock with respect to the fixed period reference clock,
A comparison circuit that outputs a clock based on the phase difference, and one of the ground potential and the power supply potential is selected in response to the clock output from the comparison circuit, and a constant current is drawn from the output to the ground side by selecting the ground potential. A charge pump circuit that supplies a constant current from the power supply to the output by selecting a power supply potential, and a charge that is connected to the output of the charge pump circuit and that repeats the ground potential or the power supply potential in response to a clock output from the comparison circuit A low-pass filter for smoothing the output of the pump circuit to obtain a control voltage of the voltage-controlled oscillator,
A lock detection circuit for detecting whether or not the oscillation clock maintains a predetermined phase difference with respect to the reference clock; and a low-pass circuit when the lock detection circuit cannot detect the oscillation clock lock for more than a predetermined period. A switch for supplying a ground potential or a power supply potential to the input or output of the filter.

According to the invention of claim 5, the reference clock is a burst clock in the composite video signal.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. In each embodiment, the same components as those of the conventional PLL circuit shown in FIG. 9 have the same reference numerals, and a description thereof will be partially omitted.

(First Embodiment) FIG. 1 shows an analog type PLL circuit 10 having a CMOS configuration. The PLL circuit 10 includes an EXOR circuit 101, a tri-state buffer 12, a constant-current type charge pump circuit 20, a low-pass filter (LPF) 30, a VCO 107, and a 1/4 frequency divider 108.

The EXOR circuit 101 is provided with a burst clock Rc having a duty ratio of 50% as a reference clock and 1 /
An output clock Pc with a duty ratio of 50% output from the frequency divider 107 is input. In the case of supporting color television of the NTSC system, the frequency of the burst clock Rc is 3.58 MHz. The EXOR circuit 101 functions as a phase comparison circuit that compares the phase of the burst clock Rc with the phase of the output clock Pc, and outputs a clock S1 based on the comparison result. Therefore, the phase of the output clock Pc is 90 ° with respect to the phase of the burst clock Rc.
Only when it is advanced, the clock S1 has twice the frequency of the burst clock Rc and has a duty ratio of 50%.

The tri-state buffer 12 includes an OR circuit 13, an inverter 14, and an AND circuit 15. O
The R circuit 13 receives the control signal RE indicating the superimposed period of the burst clock Rc in the composite video signal, and outputs the output clock S1 of the EXOR circuit 101 to the charge pump circuit 20 when the control signal RE is at L level. When the control signal RE is at H level, the OR circuit 13 cuts off the output clock S1 and outputs an H level signal.

AND circuit 15 receives control signal RE via inverter 14 and outputs output clock S 1 to charge pump circuit 20 when the output signal of inverter 14 is at H level, that is, when control signal RE is at L level. When the output signal of the inverter 14 is at the L level, that is, when the control signal RE is at the H level, the AND circuit 15 cuts off the output clock S1 and fixes the output to the L level.

The charge pump circuit 20 includes a resistor 21, n
MOS transistors 22, 24, 27, 28 and pMO
S transistors 23, 25, 26 are provided. The nMOS transistor 22 has a drain connected to the power supply via the resistor 21, a grounded source, and a gate connected to the drain. In this embodiment, the resistance 21 and the nMO
The S transistor 22 forms a constant current source. The gate voltage of the nMOS transistor 22 is set by the resistance value of the resistor 21 and the resistance voltage divided by the on-resistance value of the nMOS transistor 22.
S transistor 22 allows a constant current to flow.

The nMOS transistor 24 has a grounded source, a drain connected to the pMOS transistor 23, and a gate (drain) of the nMOS transistor 22.
And a gate connected to the gate. The nMOS transistor 24 includes the resistor 21 and the pMOS
A current mirror circuit is configured for the MOS transistor 23. Therefore, a current having a magnitude equal to the constant current flowing through the nMOS transistor 22 flows through the nMOS transistor 24.

The pMOS transistor 23 has a source connected to the power supply, a drain connected to the nMOS transistor 24, and a gate connected to the drain. A current equal to the current flowing through the nMOS transistor 24 flows through the pMOS transistor 23, and the gate voltage of the pMOS transistor 23 is set based on this current.

PMOS transistors 25, 26 and nM
The OS transistors 27 and 28 are connected in series between the power supply and the ground. The pMOS transistor 25 has a source connected to the power supply, a drain connected to the pMOS transistor 26, and a gate connected to the output terminal of the OR circuit 13. The nMOS transistor 28 has a source connected to ground, a drain connected to the nMOS transistor 27, and a gate connected to the output terminal of the AND circuit 15. Therefore, when the control signal RE is at the H level, that is, not during the period of the burst clock, the pMOS transistor 25 and the nMOS transistor 28 are turned off regardless of the level of the clock S1. When the control signal RE is at the L level,
During the period of the burst clock, the pMOS transistor 25 and nMO
The S transistor 28 turns on / off.

The pMOS transistor 26 has a source connected to the pMOS transistor 25, a drain connected to the LPF 30, and a gate connected to the gate of the pMOS transistor 23. The pMOS transistor 26 supplies the LPF 30 with a current Ip1 having a magnitude equal to the constant current flowing through the nMOS transistor 22 only when the pMOS transistor 25 is turned on. The nMOS transistor 27 has a source connected to the nMOS transistor 28, a drain connected to the LPF 30, and a gate connected to the gate of the nMOS transistor 22. nMOS transistor 2
Reference numeral 7 indicates that the current In1 having the same magnitude as the constant current flowing through the nMOS transistor 22 is extracted from the LPF 30 only when the nMOS transistor 28 is turned on.
pMOS transistor 26 and nMOS transistor 2
7, a large channel length is used so that channel length modulation does not occur. As shown in FIG. 2, the currents Ip1 and In1 are kept substantially equal from the ground potential VSS to the power supply potential VDD. It is.

The LPF 30 includes a resistor 31 and a capacitor 3
2,33. Capacitors 32 and 33 of LPF 30
Is charged and discharged by the currents Ip and In, and outputs the control voltage Vt to the VCO 107. Large capacitors are used for the capacitors 32, 33, and the capacitors 52, 5
The variation of the control voltage Vt based on the leak current from the control voltage V3 is reduced.

The VCO 107 outputs an oscillation clock Fv having a frequency corresponding to the value of the control voltage Vt. In the case of the NTSC color television, the frequency of the oscillation clock Fv is 14.318 which is four times the frequency of the burst clock Rc.
18 MHz.

The 分 frequency divider 108 outputs to the EXOR circuit 101 a clock Pc obtained by dividing the frequency of the oscillation clock Fv by ４. The A / D converter 109 samples the composite video signal CV using the oscillation clock Fv as a sampling clock, performs analog-to-digital conversion, and outputs a digital signal S2.

Now, in the PLL circuit 10 configured as described above, the frequency of the oscillation clock Fv of the VCO 107 fluctuates due to a temperature change or the like. In order to output the oscillation clock Fv having a constant frequency from the VCO 107, the voltage of the control voltage Vt must be changed so as to cancel the influence of a temperature change or the like.

The charge pump circuit 20 is of a constant current type, in which the currents Ip1 and In1 of the same magnitude are used as LPs.
The charge and discharge of F30 are controlled. When the LPF 30 is charged and discharged by the charge pump circuit 20 of the constant current system, L
The control voltage Vt output from the PF 30 maintains a constant value when the duty ratio of the clock S1 for operating the charge pump circuit 20 is 50%. And the clock S
When the duty ratio exceeds 50%, the control voltage Vt increases. When the duty ratio becomes less than 50%, the control voltage Vt increases.
Will decrease. Therefore, even if the control voltage Vt is changed to another value, the duty ratio of the output clock S1 of the EXOR circuit 101 does not need to be changed, and the duty ratio can be maintained at 50%. That is, as shown in FIG. 3 (b), the control voltage Vt is set to 1 / the power supply potential.
At 2, the clock S1 is in an ideal state with a duty ratio of 50%. Then, as shown in FIGS. 3A and 3C, the duty ratio of the clock S1 is 50% even when the control voltage Vt is higher or lower than 1/2 of the power supply potential. Therefore, the phase of the clock Pc is 90 ° ahead of the phase of the burst clock Rc, and the phase of the oscillation clock Fv can be maintained at a desired phase.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIG. In the present embodiment, the same components as those of the PLL circuit shown in FIG. 1 have the same reference numerals, and a description thereof will be partially omitted.

FIG. 4 shows an analog PLL circuit 40 having a CMOS configuration. This PLL circuit 40 differs from the charge pump circuit 20 only in the configuration of a charge pump circuit 41.

That is, the charge pump circuit 41 is of a constant current type, and the pMOS transistors 25, 26, 4
2 and 44, nMOS transistors 27, 28 and 45 and a resistor 43. The pMOS transistor 42 has a source connected to the power supply, a drain grounded via the resistor 43, and a gate connected to the drain. pM
The gate voltage of the pMOS transistor 42 is set by the resistance voltage division by the on-resistance value of the OS transistor 42 and the resistance value of the resistor 43, and pMO is set by the gate voltage.
S transistor 42 allows a constant current to flow.

The pMOS transistor 44 has a source connected to the power supply, a drain connected to the nMOS transistor 45, and a gate connected to the gate of the pMOS transistor 42. The pMOS transistor 44 and the pMOS transistor 42 constitute a current mirror circuit. Therefore, a current having a magnitude equal to the constant current flowing through the pMOS transistor 42 flows through the pMOS transistor 44.

The nMOS transistor 45 has a grounded source, a drain connected to the pMOS transistor 44, and a gate connected to the drain. n
The MOS transistor 45 includes a pMOS transistor 44
, And the gate voltage of the nMOS transistor 45 is set based on this current.

PMOS transistors 25, 26 and nM
The OS transistors 27 and 28 are connected in series between the power supply and the ground. The pMOS transistors 25 and 2
6 and the nMOS transistors 27 and 28 themselves are the same as those in FIG. Then, the gate of the pMOS transistor 44 is connected to the gate of the pMOS transistor 26, and n
The gate of the MOS transistor 45 is connected to the gate of the nMOS transistor 27 to form the charge pump circuit 41.

With the above configuration, the PLL circuit 4 of the present embodiment
0 has the same operation and effect as the first embodiment. (Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIGS. In the present embodiment, the same components as those of the PLL circuit shown in FIG. 1 have the same reference numerals, and a description thereof will be partially omitted.

FIG. 5 shows an analog PLL circuit 50 having a CMOS configuration. The PLL circuit 50 includes an EXOR circuit 101, a tristate buffer 12, first and second
Charge pump circuits 51, 52, LPF 30, lock detector 62, first and second selectors 64, 65, VC
An O107 and a ４ frequency divider 108 are provided.

The lock detector 62 outputs a burst clock Rc.
And the clock Pc output from the 1/4 frequency divider 107, the phase of the clock Pc is changed to the burst clock Rc.
Is locked to a phase difference of about 90 ° with respect to the phase of the
Detects whether or not synchronization with c.

The selection circuit 63 receives the first and second charge pump circuits 51, 52 based on the detection result of the lock detector 62.
52 is to be selected. Selection circuit 6
Reference numeral 3 includes a first selector 64 connected to the output terminal of the OR circuit 13 and a second selector 65 connected to the output terminal of the AND circuit 15. Lock detector 62
When it is determined that the clock Pc is not in the locked state, the first and second selectors 64 and 65 select the second charge pump circuit 52 to change the output clock of the OR circuit 13 and the output clock of the AND circuit 15. Supply. When the lock detector 62 determines that the clock Pc is in the locked state, the first and second selectors 6
4 and 65 select the first charge pump circuit 51 and
An output clock of the R circuit 13 and an output clock of the AND circuit 15 are supplied.

The first charge pump circuit 51 is of a constant current type and has the same configuration as the charge pump circuit 20. The gate of the pMOS transistor 25 of the charge pump circuit 51 is connected to one terminal of a first selector 64, and the gate of the nMOS transistor 28 is connected to one terminal of a second selector 65.

The second charge pump circuit 52 is a constant current type charge pump circuit having a higher current driving capability than the first charge pump circuit 51, and includes a resistor 53, an nMO
It includes S transistors 54, 56, 59, 60 and pMOS transistors 55, 57, 58. This resistor 53,
nMOS transistors 54, 56, 59, 60 and pM
The circuit configuration itself by the OS transistors 55, 57, 58 is the resistor 21, the nMOS transistors 22, 24, 2
7 and 28 and the same as the first charge pump circuit 51 including the pMOS transistors 23, 25 and 26.

As the pMOS transistor 58, a transistor having a short channel length and allowing some modulation of the channel length is used in order to improve the ability to flow a current. As shown in FIG. 6, the current Ip2 is increased by increasing the control voltage Vt. It is going to decrease with it. Also, the nMOS transistor 59
In order to improve the ability to flow a current, a device having a short channel length and allowing a slight channel length modulation is used. As shown in FIG. 6, the current In2 increases as the control voltage Vt increases. Has become.

Next, the operation of the PLL circuit 50 configured as described above will be described. Now, burst clock Rc in composite video signal CV of a certain channel
If the oscillation clock Fv is synchronized while maintaining a desired phase difference, the lock detector 62 determines that the clock Pc is in the locked state. Therefore, the first charge pump circuit 51 is selected by the first and second selectors 64 and 65, the output clock of the OR circuit 13 is supplied to the pMOS transistor 25, and the output clock of the AND circuit 15 is supplied to the nMOS transistor 28. Is done.

When the control signal RE is at L level,
That is, when the period is the burst clock period, EX
Output clock S with a duty ratio of 50% of OR circuit 101
1, the pMOS transistor 25 and the nMOS transistor 28 are turned on and off alternately. When the pMOS transistor 25 is on, the LPF 30
It is charged by the current Ip1 flowing through the S transistor 26. When the nMOS transistor 28 is on,
LPF 30 is a current I flowing through nMOS transistor 27.
It is discharged by n1 (= Ip1). As a result, LP
The control voltage Vt of F30 is stabilized at a predetermined value.

Next, when the input of the burst clock Rc to the PLL circuit 50 is temporarily stopped due to switching of the receiving channel or the like, the control signal RE at the H level causes p
MOS transistor 25 and nMOS transistor 28
Are turned off, and the LPF 30 is not charged or discharged.
At this time, the control voltage V
t decreases, and the frequency of the oscillation clock Fv decreases. Accordingly, the frequency of the clock Pc output from the 1/4 frequency divider 108 also decreases.

When a predetermined time has elapsed and the burst clock Rc is input again, the lock detector 62 determines that the clock Pc is in the unlocked state. Therefore, the second charge pump circuit 52 is selected by the first and second selectors 64 and 65, the output clock of the OR circuit 13 is supplied to the pMOS transistor 57, and A
The output clock of the ND circuit 15 is the nMOS transistor 6
0 is supplied.

When the control signal RE is at the L level, p based on the output clock S1 of the EXOR circuit 101
MOS transistor 57 and nMOS transistor 60
Are turned on and off alternately. When the pMOS transistor 57 is on, the LPF 30 is charged by the current Ip2 flowing through the pMOS transistor 58. nMOS
When the transistor 60 is on, the LPF 30 is n
Current In2 flowing through MOS transistor 59 (= Ip
It is discharged by 2). As a result, the control voltage Vt of the LPF 30 approaches a predetermined value at high speed.

As the control voltage Vt approaches a desired value, the frequency of the oscillation clock Fv approaches the target frequency. At the same time, the frequency of the clock Pc output from the 1/4 frequency divider 108 also approaches the target frequency.

When the frequency of the clock Pc approaches the target frequency and the lock detector 62 determines that the clock Pc is in the locked state, the first and second selectors 64 and 65 select the second charge pump circuit 52. Is replaced with the first charge pump circuit 51, and OR
The output clock of the circuit 13 is supplied to the pMOS transistor 25, and the output clock of the AND circuit 15 is supplied to the nMOS transistor 28. As a result, the control voltage Vt
Stabilizes at a predetermined value while suppressing ringing.

As described above, the PLL circuit 50 of the present embodiment
A first charge pump circuit 51 and a second charge pump circuit 52 having high current driving capability are provided, and whether or not the phase of the clock Pc is locked to a phase difference of about 90 ° with respect to the phase of the burst clock Rc A lock detector 62 for detecting the state is provided. When the clock Pc is in the unlocked state, the second charge pump circuit 5
2 is selected and the LPF 30 is charged and discharged by the currents Ip2 and In2, and when the clock Pc is in the locked state,
When the first charge pump circuit 51 is selected and the currents Ip1,
The LPF 30 was charged and discharged by In1.
Therefore, when switching the reception channel, etc., LP
The voltage value of the control voltage Vt of F30 can be pulled into a predetermined voltage value at high speed, and the oscillation clock Fv synchronized with the burst clock Rc can be obtained at high speed.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to FIGS. In the present embodiment, the same components as those of the PLL circuit shown in FIG. 1 have the same reference numerals, and a description thereof will be partially omitted.

FIG. 7 shows an analog PLL circuit 70 having a CMOS structure.
A switch 71 and a lock detector 72 are provided in addition to the configuration of the LL circuit 10.

The lock detector 72 outputs a burst clock Rc.
And the clock Pc output from the 1/4 frequency divider 107, the phase of the clock Pc is changed to the burst clock Rc.
It is detected whether or not the phase difference of 90 ° is locked for a predetermined time or more, that is, whether or not the oscillation clock Fv is not synchronized with the burst clock Rc for a predetermined time or more. When the lock detector 72 determines that the clock Pc has not been locked for a predetermined time or more, it outputs a one-shot unlock detection signal S3.

The switch 71 is provided between the LPF 30 and the ground. When the unlock detection signal S3 is output from the lock detector 72, the switch 71 is turned on for the period during which the unlock detection signal S3 is output, and the switch 71 is turned on.
The output of 0 is grounded, the value of the control voltage Vt is forcibly reduced to the ground potential VSS, and the PLL circuit 70 is reset. When the unlock detection signal S3 is no longer input, the switch 71 disconnects the output of the LPF 30 from the ground.

The PLL circuit 70 of this embodiment uses the charge pump circuit 20 of the constant current system. However, the current characteristic of the pMOS transistor 26 and the current characteristic of the nMOS transistor 27 between the ground potential VSS and the power supply potential VDD are used. Cannot be strictly symmetric, and the current Ip1 of the pMOS transistor 26 is slightly larger than the current In1 of the nMOS transistor 27, as shown in FIG.

In such a PLL circuit 70, the clock Pc may not be locked against an input frequency change in a step response such as switching of a receiving channel.
That is, the voltage of the control voltage Vt of the LPF 30 is normally Ip
The voltage value Vp where 1 = In1 is trapped,
Even if the voltage value V1 of the control voltage Vt is the lock point, the control voltage Vt cannot be changed from Vp to V1 because the capacity of the LPF 30 is large and the capture range is narrow.

In this embodiment, when the unlock state of the clock Pc continues for a predetermined time or more in the step response, the unlock detection signal S3 output from the lock detector 72
And the control voltage Vt is forcibly set to the ground potential VSS. Ground potential V of control voltage Vt
As the frequency decreases to SS, the frequency of the oscillation clock Fv decreases, and the frequency of the clock Pc output from the 1/4 frequency divider 108 decreases.

When control signal RE is at L level, E based on burst clock Rc and clock Pc is used.
PMO based on the output clock S1 of the XOR circuit 101
The S transistor 25 and the nMOS transistor 28 are turned on and off alternately, and the LPF 30 is charged by the current Ip1 and discharged by the current Ip2. As a result, the control voltage Vt rises from the ground potential VSS, and the clock Pc is locked at the voltage V1.

As described above, in the present embodiment, when the unlocked state of the clock Pc continues for a predetermined time or more in the step response such as the switching of the receiving channel, the control voltage V
After forcibly setting the value of t to the ground potential VSS, the EXOR circuit 101 based on the burst clock Rc and the clock Pc
The LPF 30 is charged and discharged based on the output clock S1 to increase the value of the control voltage Vt from the ground potential VSS, and lock the clock Pc with the voltage V1 to generate the oscillation clock Fv.
Can be reliably synchronized with the burst clock Rc.

It should be noted that the present invention is not limited to the above embodiments, but may be modified and embodied as follows. Even in that case, the same operation and effect can be obtained. 4th
In the PLL circuit 70 of the embodiment, the switch 71 and the lock detector 72 are provided for the PLL circuit 10 of the first embodiment, but the switch 71 and the lock detector 72 are provided for the PLL circuit 40 of the second embodiment. You may. In this case, in the charge pump circuit 41 of the PLL circuit 40, the nMOS is applied between the ground potential VSS and the power supply potential VDD.
The current In1 of the transistor 27 becomes slightly larger than the current Ip1 of the pMOS transistor 26. Therefore, the switch 71 is provided between the power supply VDD and the LPF 30, and when the unlock state of the clock Pc continues for a predetermined time or more,
The control voltage Vt is forced to the power supply potential VDD by turning on the switch 71 only during the period in which the one-shot unlock detection signal S3 is output, and then the control voltage Vt is lowered from the power supply potential VDD to a predetermined voltage. Then, the clock Pc may be locked to synchronize the oscillation clock Fv with the burst clock Rc.

In each of the above embodiments, the burst clock Rc included in the composite video signal CV is used as the reference clock, and the PLL circuit in the color television receiver that outputs the oscillation clock Fv synchronized with the burst clock Rc is embodied. However, the PLL is not limited to this, and outputs an oscillation clock synchronized with an arbitrary clock other than the burst clock as a reference clock.
It may be embodied in a circuit.

[0066]

As described above in detail, according to the first to fifth aspects of the present invention, the synchronization between the reference clock and the oscillation clock can be reliably maintained.

According to the third aspect of the present invention, an oscillation clock synchronized with the reference clock can be obtained at a high speed. According to the invention of claim 4, in the step response, the oscillation clock can be reliably synchronized with the reference clock.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a PLL circuit according to a first embodiment.

FIG. 2 is a diagram showing current characteristics of a charge pump circuit;

FIG. 3 is a waveform chart showing an operation.

FIG. 4 is a circuit diagram showing a PLL circuit according to a second embodiment.

FIG. 5 is a circuit diagram showing a PLL circuit according to a third embodiment;

FIG. 6 is a diagram showing current characteristics of a charge pump circuit;

FIG. 7 is a circuit diagram showing a PLL circuit according to a fourth embodiment;

FIG. 8 is a diagram showing current characteristics of a charge pump circuit;

FIG. 9 is a circuit diagram showing a conventional PLL circuit.

FIG. 10 is a waveform chart showing the operation.

FIG. 11 is a waveform diagram showing a problem of the conventional example.

[Explanation of symbols]

20 charge pump circuit 23, 26 pM constituting the second current mirror circuit
OS transistor 24, 27 nM constituting first current mirror circuit
OS transistor 25 pMOS transistor as second transistor 28 nMOS transistor as first transistor 30 low-pass filter (LPF) 51 first charge pump circuit 52 second charge pump circuit 62, 72 lock detection circuit 63 selection circuit 71 Switch 101 EXOR circuit as comparison circuit 107 Voltage controlled oscillator (VCO) Fv Oscillation clock Rc Burst clock as reference clock Vt Control voltage

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03L ⁷ /06-7/14

Claims (5)

(57) [Claims] 1. A PLL circuit for generating an oscillation clock that maintains a constant phase difference with respect to a reference clock having a constant cycle, comprising: a voltage-controlled oscillator that outputs an oscillation clock having a frequency corresponding to a control voltage; A comparison circuit that extracts a phase difference of the oscillation clock with respect to the reference clock, and outputs a clock based on the phase difference; and selects one of a ground potential and a power supply potential in response to the clock output from the comparison circuit; A charge pump circuit that draws a constant current from the output to the ground side by selecting a potential and supplies a constant current from the power supply side to the output by selecting a power supply potential; and a ground potential or power supply connected to the output of the charge pump circuit. The output of the charge pump circuit, which repeats a potential in response to a clock output from the comparison circuit, is smoothed and the voltage control is performed. And a low pass filter to obtain a control voltage of the oscillator, the charge pump circuit is connected to the power supply potential, wherein
A first transformer operating according to the output clock of the comparison circuit
And the output of the comparison circuit.
A second transistor that operates in response to the lock;
Flow connected in series between the first and second transistors
Third and fourth transistors for controlling the current flowing through
Output from the connection point of the third and fourth transistors.
A PLL circuit characterized in that: 2. The charge pump circuit according to claim 1, wherein the charge pump circuit supplies a constant current.
And a third constant current source for supplying the constant current to the constant current source .
2. The PLL circuit according to claim 1, wherein the current mirror connection is performed . 3. A PLL circuit for generating an oscillation clock that maintains a constant phase difference with respect to a reference clock having a constant period, comprising: a voltage-controlled oscillator that outputs an oscillation clock having a frequency corresponding to a control voltage; A comparison circuit that extracts a phase difference of the oscillation clock with respect to the reference clock, and outputs a clock based on the phase difference; and selects one of a ground potential and a power supply potential in response to the clock output from the comparison circuit; A first charge pump circuit that draws a constant current from the output to the ground side by selecting a potential and supplies a constant current from the power supply side to the output by selecting a power supply potential; and responds to a clock output from the comparison circuit. Select either the ground potential or the power supply potential, pull the constant current from the output to the ground side by selecting the ground potential, and select the power supply side by selecting the power supply potential. A second charge pump circuit that supplies a constant current from the first charge pump circuit to the output and has a higher output load driving capability than the first charge pump circuit, and is connected to the outputs of the first and second charge pump circuits. A low-pass filter that obtains a control voltage of the voltage-controlled oscillator by smoothing an output of the first and second charge pump circuits that repeats a ground potential or a power supply potential in response to a clock output from the comparison circuit; A lock detection circuit that detects whether the oscillation clock maintains a constant phase difference with respect to the reference clock; and wherein the oscillation clock is constant with respect to the reference clock in response to a detection result of the lock detection circuit. The first charge pump circuit is selectively operated when the phase difference of A selection circuit for selectively operating the second charge pump circuit when a fixed phase difference is not maintained, wherein the first charge pump circuit is connected to a power supply potential.
And a first operating in response to an output clock of the comparison circuit.
Connected to the ground potential and the comparison circuit
Second transistor that operates in response to the output clock of
Connected in series between the first and second transistors
And fourth transistors for controlling the flowing current
And a connection between the third and fourth transistors.
A PLL circuit characterized by obtaining an output from a point . 4. A PLL circuit for generating an oscillation clock that maintains a constant phase difference with respect to a reference clock having a constant cycle, comprising: a voltage-controlled oscillator that outputs an oscillation clock having a frequency corresponding to a control voltage; A comparison circuit that extracts a phase difference of the oscillation clock with respect to the reference clock, and outputs a clock based on the phase difference; and selects one of a ground potential and a power supply potential in response to the clock output from the comparison circuit; A charge pump circuit that draws a constant current from the output to the ground side by selecting a potential and supplies a constant current from the power supply side to the output by selecting a power supply potential; and a ground potential or power supply connected to the output of the charge pump circuit. The output of the charge pump circuit, which repeats a potential in response to a clock output from the comparison circuit, is smoothed and the voltage control is performed. A low-pass filter that obtains a control voltage of an oscillator, a lock detection circuit that detects whether the oscillation clock maintains a constant phase difference with respect to the reference clock, and a lock detection circuit that exceeds a predetermined period. A switch for supplying a ground potential or a power supply potential to an input or an output of the low-pass filter when lock of the oscillation clock cannot be detected, the charge pump circuit being connected to a power supply potential,
A first transformer operating according to the output clock of the comparison circuit
And the output of the comparison circuit.
A second transistor that operates in response to the lock;
Flow connected in series between the first and second transistors
Third and fourth transistors for controlling the current flowing through
Output from the connection point of the third and fourth transistors.
A PLL circuit characterized in that: 5. The PLL circuit according to claim 1, wherein the reference clock is a burst clock in a composite video signal.