JPH05110429A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To reduce a locking time from an unlock state to a lock state, to attain high stability in the lock state and to improve noise immunity. CONSTITUTION:Two output signals from two-analog/digital-output type phase comparator 1 are added and the sum is given to a loop filter 2 and a DC voltage obtained from the loop filter 2 controls a voltage controlled oscillator 3 in the phase locked loop circuit. A 2-way switch 8 is interposed between a digital output terminal 5 of the phase comparator 1 and the loop filter 2 to apply switching control to the 2-way switch 8 with a lock detection signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a phase locked loop circuit (hereinafter referred to as a PLL circuit) suitable as a frequency synthesizer for radio equipment.

[0002]

2. Description of the Related Art As is well known, a PLL circuit is widely used for a frequency synthesizer of a digital tuning type radio.

The basic configuration of this PLL circuit is a voltage-controlled oscillator (hereinafter referred to as VCO) that generates a local oscillation frequency fL, and a pre-frequency divider that divides the output signal of this VCO with a fixed frequency division ratio. Bowl (hereinafter referred to as prescaler)
A variable divider that further divides the output signal of the prescaler with a variable division ratio, a crystal oscillator that generates a clock signal that serves as a phase reference, an output signal of the variable divider and the crystal oscillator. From a phase comparator for phase-comparing the output clock signal and a low-pass filter (hereinafter referred to as a loop filter) for averaging the output signal of the phase comparator and converting it into a DC voltage, and controlling the VCO with this. Is becoming

When the phase of the output clock signal of the crystal oscillator and the phase of the output signal of the variable frequency divider are relatively far apart, the oscillation frequency of the VCO randomly fluctuates and is not stabilized. On the other hand (hereinafter referred to as an unlocked state), when the phase of the output clock signal of the crystal oscillator and the phase of the output signal of the variable frequency divider approach within a certain range, the VCO of the VCO is adjusted so that the phases of the two become the same. The oscillation frequency is suddenly drawn in, and thereafter the oscillation frequency of the VCO is stabilized in that state (hereinafter referred to as the lock state).

Since a certain correlation is established between the oscillation frequency of the VCO and the frequency division ratio of the variable frequency divider in this locked state, the frequency division ratio of the VCO is controlled by controlling the frequency division ratio from the outside. Set the oscillation state to the desired local oscillation frequency f
It can be stabilized with L.

By the way, as the above-mentioned phase comparator, an analog type phase comparator which outputs an analog signal whose instantaneous voltage represents a phase difference, and a digital (pulse train) signal whose average voltage represents a phase difference. Is known as a digital phase comparator which outputs

In the case of the analog type phase comparator, since it responds relatively slowly to the detected phase difference, it is suitable for maintaining the locked state, but in the unlocked state, it can be pulled into the locked state. It has the drawback of taking time. On the other hand, in the case of a digital phase comparator,
Since it responds relatively sensitively to the detected phase difference, it is not suitable for maintaining the locked state, but in the unlocked state, it has an advantage that it can be pulled into the locked state in a relatively short time. For this reason, in recent PLL circuits, a phase comparator that outputs the detected phase difference as both an analog signal and a digital signal is used.

An example of such an analog / digital dual output type phase comparator is shown in FIG. In the figure, the sample-hold phase comparator 1 is provided with an output terminal 4 for analog output and an output terminal 5 for digital output. Output signals obtained from these two output terminals 4 and 5 are shown. After being added to each other, they are averaged by the common loop filter 2 and converted into a DC voltage.
The oscillation frequency of O3 is controlled. For convenience of explanation,
Other components of the PLL circuit such as a crystal oscillator, a prescaler, a variable frequency divider, etc. are omitted in the drawing.

In such an analog / digital two-output type phase comparator 1, the VCO can be optimally controlled in both the unlocked state and the locked state, but the output terminal 5 still outputs the VCO. There is a disadvantage that the operation of the VCO 3 is destabilized by the noise component contained in the digital signal.

Therefore, conventionally, in a PLL circuit using this type of analog / digital two-output type phase comparator, a diode reverse is provided between the digital signal output terminal 5 and the loop filter 2. A configuration in which the parallel circuit 6 is interposed and the forward threshold voltage VF (about 0.6 V) is utilized to remove the noise component is adopted.

However, as described above, a diode is provided between the digital signal output terminal 5 and the loop filter 2.
The anti-parallel circuit 6 is interposed, and its forward threshold voltage VF
Even in the PLL circuit that removes the above-mentioned noise component using (about 0.6 V), the level of the noise component does not always fall within the forward threshold voltage VF (about 0.6 V), so It may not be possible to remove the noise component,
Moreover, since the sensitivity of the VCO 3 arranged in the latter stage of the loop filter 2 is extremely high, that is, it changes by several MHz per 1V, even if a slight noise leaks, the frequency synthesizer as a whole does not operate. There is a problem that the noise characteristic is greatly deteriorated.

[0012]

As described above, in the PLL circuit using the analog / digital two-output type phase comparator, the VCO is optimized in both the unlocked state and the locked state. Controllable, but still VC due to the noise component contained in the digital signal from the output terminal 5
There is an inconvenience that the operation of O3 becomes unstable, and in order to solve this inconvenience, a diode anti-parallel circuit 6 is interposed between the digital signal output terminal 5 and the loop filter 2,
Even in the PLL circuit configured to remove the noise component using the forward threshold voltage VF (about 0.6 V), the level of the noise component is not always the forward threshold voltage VF.
Since it does not fall within (about 0.6 V), it may not be possible to completely remove the noise component, and if the sensitivity of the VCO 3 arranged after the loop filter 2 changes by several MHz per 1 V. Since the above-mentioned highly sensitive one is used, there is a problem that the noise characteristic of the entire frequency synthesizer is significantly deteriorated even by a slight noise leakage.

SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the above problems and to provide a PLL circuit having a short pull-in time from an unlocked state to a locked state, high stability in the locked state, and good resistance to noise. And

[0014]

SUMMARY OF THE INVENTION According to the present invention, two output signals from an analog / digital two-output type phase comparator are added to each other and applied to a loop filter, and a DC voltage obtained from the loop filter is used. In a phase locked loop circuit for controlling a voltage controlled oscillator, a bidirectional switch is interposed between a digital output terminal of the phase comparator and a loop filter, and the bidirectional switch is controlled to open / close by a lock detection signal. It is characterized by doing.

[0015]

In general, the lock detection signal in this type of analog / digital two-output type phase comparator has a binary state of "1" in the locked state and "0" in the unlocked state. Therefore, by using this lock detection signal to control the opening and closing of the switch interposed in the digital signal output path, it is possible to reliably switch whether or not the digital output signal from the phase comparator is added to the loop filter, and to unlock. While the high-speed pull-in by the digital signal is possible in the state, the influence of noise can be completely eliminated by disconnecting the digital signal in the locked state.

[0016]

FIG. 1 is a circuit diagram showing an embodiment of a PLL circuit according to the present invention. Note that, for convenience of explanation, other components of the PLL circuit such as a crystal oscillator, a prescaler, and a variable frequency divider are not shown.

In the figure, reference numeral 1 is a sample-hold phase comparator as an analog / digital two-output type phase comparator. The phase comparator 1 has an analog voltage whose instantaneous voltage indicates a detected phase difference. An analog output terminal 4 that outputs a signal, a digital output terminal 5 that outputs a digital signal whose average voltage represents the detected phase difference, and "lock" in a steady state and "unlock" during a transient response 2 A lock detection signal output terminal 7 for outputting a lock detection signal indicating a value state is provided.

Further, the digital output terminal 5 of the phase detector 1
Between the loop filter 2 and the loop filter 2, more precisely, a bidirectional analog switch 8 is interposed between the digital output terminal 5 and the signal addition point.
The control input terminal of is connected to the lock detection signal output terminal 7 of the phase comparator 1.

Next, the operation of the PLL circuit having the above configuration will be described in detail. When the present PLL circuit is in the unlocked state, the content of the lock detection signal is "0", and in response to this, the analog switch 8 is in the closed state (on state).

Therefore, in the unlocked state, as a result of the digital signal being supplied to the loop filter 2, high-speed pull-in is possible in the process from the unlocked state to the locked state.

On the other hand, when the PLL circuit is in the locked state,
The content of the lock detection signal becomes "1", and in response to this, the analog switch 8 is opened (OFF state).

Therefore, in the locked state, no digital signal is supplied to the loop filter 2,
VCO3 caused by the noise component contained in the digital signal
The malfunction of is completely eliminated. Further, in this state, the loop filter 2 is supplied with only the analog signal whose sensitivity to the detected phase difference is relatively slow, so that the locked state is stably maintained.

As described above, according to the PLL circuits of the above embodiments, the lock detection signal is used to control the opening / closing of the switch 8 interposed in the digital signal output path.
By reliably switching whether or not the digital output signal from the phase comparator 1 is added to the loop filter 2, it is possible to perform high-speed pull-in by the digital signal in the unlocked state, while disconnecting the digital signal in the locked state. Provided is a PLL circuit that can completely eliminate the influence of noise, and thus has a short pull-in time from the unlocked state to the locked state, high stability in the locked state, and good resistance to noise. You can

[0024]

As described above, according to the present invention,
A phase-locked loop in which two output signals from an analog / digital two-output type phase comparator are added to each other and given to a loop filter, and a DC voltage obtained from the loop filter is used to control a voltage controlled oscillator. In the circuit, since the bidirectional switch is interposed between the digital output terminal of the phase comparator and the loop filter and the bidirectional switch is controlled to open / close by the lock detection signal, the unlocked state is changed to the locked state. It is possible to provide a PLL circuit having a short pull-in time, high stability in a locked state, and good resistance to noise.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a PLL circuit according to the present invention.

FIG. 2 is a block diagram showing an example of a conventional PLL circuit.

[Explanation of symbols] 1 sample-hold phase comparator 2 loop filter 3 VCO 4 analog signal output terminal 5 digital signal output terminal 7 lock detection signal output terminal 8 analog switch

Claims (1)

[Claims] 1. An analog / digital two-output type phase comparator adds two output signals to each other to give a loop filter, and a DC voltage obtained from the loop filter controls a voltage-controlled oscillator. In the phase locked loop circuit described above, a bidirectional switch is interposed between the digital output terminal of the phase comparator and the loop filter, and the bidirectional switch is controlled to open / close by a lock detection signal. Droop circuit.