JPS623528A - Pll oscillator - Google Patents

Abstract

PURPOSE:To obtain a PLL oscillator with a simple circuit where a time reaching a stable synchronous state is short by providing a voltage application means approaching an output of a low pass filter to a steady-state voltage by applying a constant voltage to the low pass filter when the oscillation is not in the steady-state. CONSTITUTION:An asynchronization detection signal is outputted from a lock detector at application of power or an asynchronizing state to turn on a switch SWX. Then a constant voltage outputted from a constant voltage power circuit POW is fed to a connecting point between a resistor R and a capacitor C via the switch SWX and a diode D0 to approach the oscillating frequency of a voltage controlled oscillator VCO forcibly in the vicinity of an object oscillation frequency. The diode D0 is provided, which is turned off when the output voltage of a phase detector PFD gets higher than a prescribed voltage and an output voltage of the phase detector PFD (higher than the prescribed voltage) is fed to an oscillation frequency control terminal, then the phase locked loop is operated normally in the PLL oscillator.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a phase-long loop (PLL) oscillator, and more particularly to a PLL oscillator having a low-pass response characteristic due to a low-pass filter.

[Conventional technology]

The PLL oscillator oscillates in synchronization with the input signal.

Since the response characteristic to the phase change of the input signal can be changed, it is often used as a noise removal circuit for input signals. FIG. 4 is a circuit diagram of a conventional PLL oscillator.

The input signal applied from the input terminal IN and the output of the voltage controlled oscillator VCO are applied to the phase detector PFD, and the phase detector PFD detects the phase difference between the two signals. The detection output has high frequency components removed by a low pass filter LPF consisting of a resistor R and a capacitor C, and is applied to the oscillation frequency control input of the voltage controlled oscillator VCO to determine the oscillation frequency of the voltage controlled oscillator VCO. Then, the output of the voltage controlled oscillator VCO is applied to the external circuit from the output terminal 0tJT. The synchronization-related operations of this PLL oscillator have been reported in various fields, so they will not be discussed here. Generally, the synchronization range of this oscillator (the range in which the output of the oscillator is synchronized with the input signal when the input signal is free of noise and changes slowly) is determined by the voltage-to-frequency conversion characteristics of the voltage-controlled oscillator VCO. Furthermore, the synchronization range of the PLL oscillator is almost unrelated to the noise improvement characteristics for the input signal, and the noise improvement characteristics are determined by the characteristics of the low-pass filter LPF shown in FIG. For example, by lowering the passband of the low-pass filter LPF, changes in the phase of the input signal outside the two passbands are removed.

When using this PLL oscillator for the purpose of removing noise, the passband of the low-pass filter LPF is lowered as described above (note that even if the passband of this low-pass filter is lowered, the synchronization remains almost unchanged). However, due to the effect of the low-pass filter LPF, there is a problem in that the time from power-on to synchronization with the input signal and the time from loss of synchronization to synchronization become longer.

FIG. 5 is a transient response characteristic diagram from when the power is turned on until a synchronous steady state is reached. The horizontal axis represents time T, and the vertical axis represents voltage V applied to the oscillation frequency control input of voltage controlled oscillator VC○. As is clear from this characteristic diagram, the time t until the voltage V becomes constant, that is, passes through the stable point P, is long. When such a PLL oscillator is used, for example, in a synchronous communication system, there is a problem in that it cannot be used immediately after power is turned on, and communication cannot be performed until a specific time has elapsed. The same problem also occurs when synchronization is lost due to noise or the like. In order to improve this and shorten the time it takes from these states (when power is turned on or when synchronization is lost) to become synchronized, conventionally a lock detector has been installed to determine whether the PLL oscillator is in an asynchronous state or a synchronous state. , the result of the lock detector is 21 [! I was switching the low pass filter of it. FIG. 6 is a circuit diagram of a conventional PLL oscillator in which the time required for stabilization is shortened by switching between two low-pass filters. Two low-pass filters LPFO and LPFI are provided in the position of the low-pass filter LPF in FIG. 4.

The switching control circuit FS switches the switching device SW according to the signal of the lock detector LOD, and the two low-pass filters LPFO
, LPFI is selected and applied to the voltage controlled oscillator ■CO. Each low pass filter L
PFO and LPFI are composed of resistors Ro r R+ + capacitors Ca and C+, and the values of these resistors and capacitors are set to be R+>>Ro, C+>>Co, and the low-pass filter LPFO The passband of is much lower than that of the low-pass filter LPF1. In addition, the low-pass filter LPFO,L
Amplifiers AMPO and AMPI are provided at the output of PF1, and these are isolation amplifiers to prevent the respective passbands from being changed by the switch SW made of polyurethane. When a signal indicating an asynchronous state is applied from the lock detector, the connection position of the switch SW consisting of a volume selects the output of the low-pass filter LPFO, and when synchronization is achieved, the low-pass filter gradually filters out. It operates to select the output of LPFI.

FIG. 7 is a transient response characteristic diagram of the conventional circuit shown in FIG. 6 from when the power is turned on to when the synchronization stabilizes. The horizontal axis represents time T, and the vertical axis represents voltage V applied to the oscillation frequency control input of the voltage controlled oscillator VCO. From the figure, the time t until the voltage V becomes constant, that is, passes the stable point P, is the fifth
It is much shorter than the characteristic curve shown in the figure. still.

The period to represents the period during which the low pass filter LPFO is selected, and 1+ represents the period during which the low pass filter LPF 1 is selected. On the other hand, the reason why the switch SW is constituted by a polyram is to prevent the PLL oscillator from becoming unsynchronized with the input signal again due to switching at seven instants. The period tx of the characteristic curve diagram in FIG. 7 corresponds to this,
This is the time during which the volume of the switch SW is being changed.

However, a volume whose position is changed mechanically lacks high-speed response. Therefore, it may be possible to electrically and smoothly switch the output of the low-pass filter LPFO to the low-pass filter LPFI while maintaining the synchronized state of the PLL oscillator, but in this case.

Each low-pass filter LP is controlled by an electrical signal.
Switcher SW that smoothly switches the output of FO and LPFI
However, a switching control circuit FS was required to control it. For this reason, the conventional PLL oscillator has a complicated circuit.

[Purpose of the invention]

In view of the above-mentioned drawbacks of the conventional art, the present invention provides a PLL circuit which has nine simple circuits and which takes a short time from an asynchronous state to a synchronous stable state.
The purpose was to provide an oscillator.

[Key points of the invention]

The above object according to the invention is a voltage controlled oscillator.

a phase detector that detects a phase difference between an output signal of the voltage controlled oscillator and an input signal applied from an external device;

In a PLL oscillator comprising a low-pass filter that removes a high-frequency component of the detection output of the phase detector and outputs it to the oscillation frequency control terminal of the voltage-controlled oscillator, the low-pass filter has a constant state when one oscillation is not in a steady state. This is achieved by providing a P' L L oscillator characterized in that it is equipped with a voltage applying means that applies a voltage to bring the output of the low-pass filter close to a steady voltage. And its action is as follows.

the controlled oscillator; a phase detector that detects a phase difference between the output signal of the voltage controlled oscillator and an input signal applied from an external device; and a phase detector that removes high-frequency components of the phase detector to determine the oscillation frequency of the voltage controlled oscillator. A PLL oscillation circuit is configured with a low-pass filter applied to the control terminal, and when asynchronous, the switch means is turned on to forcibly apply a constant voltage to the oscillation frequency control terminal of the voltage-controlled oscillator that should be in the vicinity of the target oscillation frequency. , synchronize the oscillation of the oscillator circuit to the input signal by rapidly approaching a steady state. Then, the switch means is turned off to configure a stable PLL oscillation circuit.

[Embodiments of the invention]

The present invention will be described in detail below using one drawing.

FIG. 1 is a circuit diagram of a PLL oscillator according to an embodiment of the present invention. Low-pass filter L of the conventional circuit shown in Figure 4
It is further turned on by the lock detector LOD at the connection point of the PF resistor R and capacitor C.

Switch SWX and diode D whose off is controlled.

The configuration is such that the output voltage of the constant voltage power supply circuit pow is applied via the constant voltage power supply circuit pow. The lock detector (LOI) is a circuit that outputs an asynchronous detection signal when the output of the voltage controlled oscillator VCO is not synchronized with the input signal input from the input terminal IN. When the power is turned on or when there is no synchronization, the lock detector outputs an asynchronous detection signal, and the switch SWX is turned on by this asynchronous detection signal. As a result, the constant voltage output from the constant voltage power supply circuit POW is applied to the switch SWX.

It is connected to the connection point between the resistor R and the capacitor C through the diode Do, that is, to the oscillation frequency control terminal of the voltage controlled oscillator VCO, and forces the oscillation frequency of the voltage controlled oscillator VCO to be near the target oscillation frequency. For example, if the output voltage of the constant voltage power supply circuit pow is vl, vl will be applied to the oscillation frequency control terminal of the voltage controlled oscillator VCO. still.

To simplify the explanation, the junction voltage of the diode Do is assumed to be OV. This voltage ■1 is a voltage controlled oscillator■
It is a voltage that sets the oscillation frequency of CO to the target frequency, that is, a voltage that is slightly lower than the steady state output voltage. When this voltage vI is applied to the voltage controlled oscillator VCO, the oscillation frequency changes, and the synchronization state is entered, the phase detector PFD The output voltage of is higher than the voltage v1. This causes diode D.

The diode is turned off by applying a reverse voltage to VCO, and the voltage V' applied to the oscillation frequency control terminal of the voltage controlled oscillator VCO becomes the output voltage of the phase detector PFD. If there is no diode DO here, the voltage controlled oscillator VCO
A constant voltage Vl remains applied to the oscillation frequency control terminal of the PLL oscillator, and the period in the PLL oscillator is no longer applied. When the output voltage of the one-phase detector PFD becomes higher than the voltage v1 due to the provision of the diode Do,
The diode Do is turned off, and the output voltage (1) of the constant voltage power supply circuit pow is not applied to the oscillation frequency control terminal of the voltage controlled oscillator VCO.

Since the output voltage (higher than voltage v1) of the phase detector PFD is applied to this oscillation frequency control terminal, the synchronized loop in the PLL oscillator operates normally. The voltage controlled oscillator VCO is controlled by the output voltage of the phase detector PFD, and the oscillation output of the voltage controlled oscillator VCO is synchronized with the input signal. FIG. 2 is a transient response characteristic diagram of the embodiment of the present invention shown in FIG. 1 from when the power is turned on until a synchronous steady state is reached. The horizontal axis is time T, and the vertical axis is voltage V' applied to the oscillation frequency control input of the voltage controlled oscillator VCO.

For comparison, the response curve of the conventional circuit is shown by a dotted line. When the power is turned on, the voltage V' suddenly rises from 0 to vl. This Vl is the voltage output from the constant voltage power supply circuit pow described above. When entering the synchronized state, the phase detector PF
The output of D becomes higher than this voltage ■1, and a synchronous steady state is reached at the stable point P.

When the characteristic curve (solid line) of the embodiment of the present invention is compared with the characteristic curve of the conventional circuit, the characteristics are similar when the voltage applied to the oscillation frequency control input of the voltage controlled oscillator VCO is v1 or higher, but In the embodiment of the present invention, the time required to change from to (1) to (1) is much shorter than in the conventional circuit.

Therefore, it passes through the stable point P much earlier than the time from when the power is turned on in the conventional circuit.

In FIG. 1, although not shown, a signal from a voltage controlled oscillator VCO is applied to the lock detector LOD, and this signal is used to determine whether the output is synchronized with the input signal. The stable point P in FIG. 2 is the point at which the lock detector LOD detects synchronization, and after this point the lock detector LOD turns off the switch SWX. By turning off the switch SWX, the operating characteristics become similar to those of the conventional circuit.

In the operation described above, when synchronization is entered when switch SWX is on, diode Do is reverse biased and turns off, resulting in constant voltage power supply circuit Po.
The configuration is such that the voltage w is not applied to the low pass filter LPF. In addition to configuring the constant voltage power supply circuit POW to be synchronized when the diode Do is turned off, the present invention also provides that the internal resistance of the constant voltage power supply circuit POW is not set to 0Ω but is set to a specific value, so that the diode Do is turned off. It is also possible to configure such that the detection signal of the phase detector PFD is applied to the voltage controlled oscillator even if the phase detector PFD is not used.

FIG. 3 is a circuit configuration diagram of another embodiment of the present invention, showing a PLL oscillator that outputs a high frequency synchronization signal in response to an input signal. The resistor R3, the Zener diode Zr, the variable resistor Rv, and the capacitor C1 constitute a constant voltage power supply circuit that is a simplified version of the constant voltage power supply circuit POW in FIG. 1 described above.

The power supply element B is connected to a Zener diode Zv via a resistor R2.
It is connected to the. The other end of the Zener diode Z7 is grounded via a variable resistor R.

The sum of the voltage generated across the variable resistor RV by the current flowing through it and the Zener voltage of the Zener diode Z7 is applied to the emitter of the transistor T. variable resistance R
Since the voltage generated across the transistor T1 is much lower than the Zener voltage, approximately the Zener voltage value is applied to the emitter of the transistor T1.

The variable resistor Rv is provided to minutely change the voltage value applied to this emitter, and the capacitor CP connected between the connection point of the resistor R3 and the Zener diode Zr and the ground is connected to the emitter of the transistor T7. This is to reduce the AC impedance between grounds. At the base of transistor T1 is a lock detector LOD.
The output signal of
A signal is added. Therefore, when asynchronous.

The voltage of the above-mentioned simple constant voltage power supply is applied to the filter via the diode D, and is forced into the low-pass filter LP.
The output of F is set to a specific voltage. Note that the specific voltage means that when this voltage is applied to the voltage controlled oscillator VCO via the resistor R/ and the amplifier AMP, the frequency divider DIV
This value is such that the frequency of the signal applied to the phase detector PFD is slightly lower than the frequency of the input signal. The phase detector PFD, low pass filter LPF, resistor Rl, amplifier AMP, voltage controlled oscillator VCO, and frequency divider DIV form one loop, and the frequency of the input signal applied to the first phase detector PFD is divided. Since the frequency of the voltage controlled oscillator VCO is the same, the oscillation frequency of the voltage controlled oscillator VCO is divided by the frequency divided by the frequency divider DIV.
The frequency is higher than the frequency of the input signal of the FD. For example, if the frequency divider DIV divides the frequency by 1/4, the voltage controlled oscillator VCO has a frequency of 4 for the input signal of the 9-phase detector PFD.
Oscillates at twice the oscillation frequency. Since the output voltage of the phase detector PFD is small, the amplifier AMP is inserted to increase the voltage input to the voltage controlled oscillator, and the resistor R
' is for increasing the input impedance of the amplifier.

If this circuit is in sync, transistor T7 is off, so the phase response to the input signal is approximately the resistance R
It is determined by a low-pass filter LPF consisting of a capacitor C and a capacitor C. however.

During non-synchronization, the transistor T is turned on by the signal applied from the lock detector, so the voltage determined by the Zener diode Zr and the variable resistor RV is applied to the low-pass filter LPF via the diode D, and the voltage controlled oscillator V
A voltage value amplified by an amplifier AMP is applied to CO.

This voltage value is such that the frequency of the signal oscillated by the voltage controlled oscillator VCO is approximately four times the frequency of the input signal.

This forces the oscillation frequency of the voltage controlled oscillator VCO to be approximately four times the frequency of the input signal.

The oscillation frequency of the voltage controlled oscillator VCO is set to 1 by the frequency divider DIV.
Since the frequency is divided by /4, a signal approximately equal to the frequency of the input signal (actually, as described above, slightly lower) is applied to the five-phase detector PFD. As a result, for synchronization, the phase detector PFD is replaced by the transistor T, and the low-pass filter LP.
Since it outputs a voltage higher than the voltage applied to F, the diode D is turned off and the output of the 1-phase detector PFD is amplified by the amplifier AMP via the low-pass filter LPF and applied to the voltage controlled oscillator ■CO, resulting in a synchronous control state. becomes. When the synchronization state is reached, the transistor T7 is turned off, so the third
The circuit shown in the figure becomes a PLL oscillator that responds with the time constant of a low-pass filter LPF.

In another embodiment of the invention in FIG. 3, the low-pass filter L
Since the output voltage of the constant voltage power supply with the internal resistance RV is applied to PF, the output of the two-phase detector PFD is divided by the internal resistance Rv, etc., so it is attenuated and applied to the oscillation frequency control terminal of the voltage controlled oscillator VCO. Become. Therefore, even if the diode D is on (when the frequency of the voltage controlled oscillator VCO is not set to a low level by the voltage of the constant voltage power supply), a synchronized state can be achieved.

〔Effect of the invention〕

As described above, the present invention uses a simple circuit to forcibly apply a voltage to the low-pass filter during non-synchronization, and generates a voltage-controlled oscillator V
The oscillation frequency of the CO is brought close to the frequency of the input signal for synchronization. According to the present invention, it is possible to obtain a PLL oscillator that takes a short time to reach a stable synchronization state with a simple circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention. FIG. 2 is a response characteristic curve diagram of the embodiment of the present invention shown in FIG. FIG. 3 is a circuit diagram of another embodiment of the present invention. 4 and 6 are circuit configuration diagrams of a conventional PLL oscillator. FIGS. 5 and 7 are response characteristic curve diagrams in FIGS. 4 and 6, respectively. PFD...phase detector. LPF...Low pass filter. VCO: Voltage controlled oscillator. LOD...Lock detector. SWX...Switch. Do, D. ・Diode. T7...Transistor. Z, ... Zener diode. Rv...variable resistance. Patent Applicant Casio Computer Co., Ltd. Figure 1 Figure 2 Figure 3

Claims (4)

[Claims] (1) a voltage controlled oscillator; a phase detector that detects the phase difference between the output signal of the voltage controlled oscillator and an input signal applied from an external device; In a PLL oscillator consisting of a low pass filter output to an oscillation frequency control terminal of a voltage controlled oscillator,
A PLL oscillator characterized by comprising voltage applying means for applying a constant voltage to the low-pass filter to bring the output of the low-pass filter close to a steady voltage when the oscillation is not in a steady state. (2) The PLL according to claim 1, wherein the voltage applying means includes a power source and a switch means, and the switch means has a diode, and the diode is turned off at least in a steady state. oscillator. (3) The PLL oscillator according to claim 1, wherein the voltage application means includes a power source and a switch means, and the switch means has a switch section that is turned off when the PLL oscillator is in a steady state. . (4) The PLL oscillator according to claim 3, wherein the switch means includes a diode that is turned off at least in a steady state.