JPH025622A - Pll frequency synthesizer - Google Patents

Abstract

PURPOSE:To improve the stability and modulation performance, such as pull-in time, noise band width, etc., of the title synthesizer by actuating a PLL circuit performance changing means which switches a loop inherent frequency of a prescribed value to a larger value by means of a frequency changing means for a prescribed period. CONSTITUTION:In the normal state, switches S1 and S2 of the loop filter 20 incorporated in this PLL frequency synthesizer are controlled to opened states. Therefore, the loop inherent frequency of a PLL circuit goes to a relatively small value omegaL and the stability of the synthesizer in noise band width, etc., becomes extremely excellent. When the frequency of the output frequency fo of the synthesizer is changed, the switches S1 and S2 of the loop filter 20 are simultaneously closed with the input of a frequency switching timing signal and the loop inherent frequency is changed to a relatively large value omegaH. Therefore, the pull-in time of the PLL frequency synthesizer can be shortened and the synthesizer can be immediately stabilized with a new oscillation frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the invention (industrial application field)
p) PLL that generates a signal of a desired frequency using a circuit
Regarding frequency synthesizers.

(Prior art and problems to be solved by the invention) Conventionally, PLL frequency synthesizers have been developed using a stable operating PLL.
- With the advent of IC, it has been applied in a wide range of fields from measuring instruments to consumer equipment.

The basic performance of such a PLL frequency synthesizer, that is, the pull-in time that is the frequency pull-in time, the noise bandwidth that indicates the stability against noise (disturbance), etc., is determined by the built-in PLL frequency synthesizer.
It is well known that the following relationship exists with respect to the loop natural frequency ω'1 of the LL circuit. In other words, the pull-in time becomes shorter and better as the loop natural frequency vIlωn becomes larger, but the noise bandwidth etc. On the contrary, the stability of

Also, when performing FM modulation using a PLL frequency synthesizer, the loop natural frequency ωn of the built-in PLL circuit
If is large, FM modulation cannot be applied from low frequencies.

Therefore, in the past, the loop natural frequency ωn was designed to be relatively small with emphasis on stability and modulation performance, which are important for a PLL frequency synthesizer, resulting in a long pull-in time.

The present invention was made in order to solve the problems remaining in the PLL frequency synthesizer described above, and the present invention has been made in order to solve the problems remaining in the above-mentioned PLL frequency synthesizer. The objective is to provide a PLL frequency synthesizer that exhibits the best characteristics without sacrificing both.

Structure of the Invention (Means for Solving the Problems) The means configured in the present invention to solve the above problems are as follows: A signal of a frequency determined based on a frequency command signal,
P generated using a PLL circuit with a predetermined loop natural frequency
In the LL frequency synthesizer, the PLL circuit performance changing means switches the loop natural frequency of the PLL circuit to a value larger than the predetermined loop natural frequency, and when the frequency command signal is input, the PLL circuit performance changing means changes for a predetermined period of time. The gist of the invention is a PLL frequency synthesizer characterized by comprising: a frequency switching means for operating the PLL frequency synthesizer;

(Function) The loop natural frequency of the PLL circuit incorporated in the PLL frequency synthesizer of the present invention is designed in advance to a predetermined value, and the PLL frequency synthesizer is equipped with a PLL circuit performance changing means for switching the predetermined value of the loop natural frequency to a higher value.

Further, it has a frequency switching means that operates intermittently when a frequency 1 command signal is input to the PLL frequency synthesizer, and this frequency switching means operates the PLL circuit performance changing means for a predetermined period of time.

Therefore, the basic performance of the PLL frequency synthesizer of the present invention is determined by the PLL circuit having a predetermined loop natural frequency designed in advance during the overcrowded frequency generation operation. When a frequency command signal for changing the generated frequency is input, the basic performance is determined by the PLL circuit with a large loop natural frequency changed by the PLL circuit performance changing means for a predetermined period determined by the frequency switching means. be done.

Note that the predetermined loop natural frequency designed in advance is
Preferably, the stability and modulation characteristics of the frequency synthesizer are determined as the most important factors, and the large value loop natural frequency to be changed by the PLL circuit performance changing means is determined with the pull-in time as the most important factor.

Further, it is desirable that the predetermined period during which the frequency switching means operates the PLL circuit performance changing means is appropriately determined in consideration of the pull-in time of the PLL frequency synthesizer.

EXAMPLES Hereinafter, in order to explain the present invention more specifically, examples will be given and explained.

(Embodiment) FIG. 1 is a block diagram showing the configuration of a PLL frequency synthesizer according to an embodiment. As shown in the figure〈PL of the example
The basic configuration of the L frequency synthesizer employs a dense prescaler method suitable for generating relatively high frequencies of several tens of MHz.

That is, it includes a phase detector 10 that compares the phases of a reference signal fr with a stable frequency and a frequency-divided signal fn from a variable frequency divider 50, which will be described later, and outputs a signal based on the phase difference between both signals fr and fn. The output signal of the phase detector 10 is given to the voltage controlled oscillator 3o via a loop filter 20 having low-pass characteristics. And voltage controlled oscillator 30
outputs a signal (output signal) fo having a frequency corresponding to the input voltage signal.

While the output signal fo of the voltage control oscillator 30 is provided for use by other devices, it is input to a prescaler 40 capable of high-speed frequency division processing and frequency-divided (1/M). The value is again frequency-divided by the variable frequency divider 50 to become the frequency-divided signal frt, which is input to one side of the phase detector 10 as described above. Note that when the frequency switching timing signal, which is a pulse signal, is input from the frequency controller 60, the frequency division value of the variable frequency divider 50 is appropriately set to a value of +-E- with an interval at the rising edge of the frequency switching timing signal. .

Therefore, the output signal fo of the PLL frequency synthesizer of the embodiment is determined by the following equation.

fo=N ◆ M dispute f "However, N is the frequency division value of the variable frequency divider 50, and is appropriately set to any one shift when the frequency switching timing signal from the frequency controller 60 is input.

Further, the frequency step Δf that can be controlled by the frequency switching timing signal from the frequency controller 60 is expressed by the following equation.

Δf=M−fr Furthermore, the PLL frequency synthesizer of the embodiment has the following unique configuration.

The loop filter 20 is formed from passive elements such as a resistor and a capacitor C, and is configured as a lag lead type filter exhibiting low-pass characteristics.

However, as shown in the figure, the resistor R
Ike resistors Ra and Rb are connected in parallel to A and RB via switches Sl and S2.

Therefore, this switch S1. The transfer characteristics of the relube filter 20 can be easily varied by opening and closing S2. That is, the loop natural frequency ωn of the PLL circuit can be changed by opening and closing the switches Sl and S2 of the loop filter 2o.

Further, the loop filter 2o is configured to input the frequency switching timing signal outputted from the frequency controller 60 in the same way as the variable frequency divider 50, and the switch S
1 and S2 are operated to close. In other words, the output signal f
The frequency switching timing signal that gives the timing to change the frequency of
00 is used as a frequency division value change timing signal, and the loop natural frequency ω of the PLL circuit is connected between the signal output devices.
It is used as a period of change in history. This switch S
1. The timing chart in FIG. 2 visually represents the execution timing of the opening/closing operation of S2, that is, the timing of changing the loop natural frequency ωn.

When the frequency controller 60 outputs a frequency switching timing signal (FIG. 2(a)) indicating the timing to change the frequency of the output signal fo, the variable frequency divider 50 synchronizes with the rising edge of the frequency switching timing signal. Then, the frequency division value rNJ is changed, and for example, the frequency of the output signal fo is changed by Δf (FIG. 2(b)).

At the same time as this change in the output signal fo, the loop filter 20
switch S1. S2 is controlled to open only during the output period T of the frequency switching timing signal (FIG. 2(C)). Therefore, during this closing control period, the loop natural frequency of the PLL circuit changes from the normal 1-direction ωL to the value ωH (ωH〉ωL).
will be changed to

Note that the opening control interval at this time, that is, the output interval T of the frequency switching timing signal is set to be slightly longer than the interval until the output signal fo stabilizes at the target value, as shown in the figure.

It is clear that the PLL frequency synthesizer of this embodiment configured as described above has the following effects. In a normal state in which the output signal fo is fixed at a constant frequency, the switches S1 . S2 is controlled to be open, and therefore the loop natural frequency of the PLL circuit is a relatively small value of ωL.

Therefore, the stability of the noise bandwidth and the like of the PLL frequency synthesizer is extremely good, and stable operation can be ensured. Additionally, the frequency to which modulation is applied is less restricted, resulting in a frequency synthesizer with excellent operability.

On the other hand, when changing the frequency of the output frequency fo of the PLL frequency synthesizer, the switch S1. s2 is controlled to open simultaneously with the input of the frequency switching timing signal, changing the loop natural frequency of the PLL circuit to a large value ωH.

Therefore, the pull-in time of the PLL frequency synthesizer is short and the new oscillation frequency can be settled immediately.

Moreover, after the pull-in time due to H of the loop natural frequency has elapsed (interval T in FIG. 2), the switch Sl of the loop filter 2o is automatically turned on.

Since S2 is controlled to be open, the output signal fo of the new oscillation frequency continues to be output extremely stably against noise.

In the above embodiment, a prescaler method was used as an example of a PLL frequency synthesizer, but the above technique can be applied to any other type of synthesizer, such as a direct method, a mixer method, etc.

In addition, although a lag lead type filter is shown as an example of a loop filter for the built-in PLL circuit, active ◆
whether in any other form, such as a filter,
It is good if the transfer function can be changed. To change this transfer function, switch S1. Although S2 is shown as a circuit symbol, this switch is a functional component for changing circuit constants, and may be either a mechanical switch or an electrical switch. Anything that has the ability to change circuit constants may be omitted.

As described in detail with reference to examples, the effects of the invention are as follows.
A frequency synthesizer sets the loop natural frequency of a PLL circuit to a value larger than usual only when switching frequencies, and maintains the loop natural frequency at a small value of 1 during normal steady state.

Therefore, when changing the frequency of the output signal, the pull-in time is shortened, and transient stability can be improved. Moreover, during steady state after the output signal has shifted to the target frequency, the stability of the noise bandwidth etc. is improved.
This is a PLL frequency synthesizer with excellent operability.

[Brief explanation of the drawing]

FIG. 1 shows a configuration block diagram of a PLL frequency synthesizer according to an embodiment, and FIG. 2 shows a timing chart for explaining the operation of the PLL frequency synthesizer according to the embodiment. 10... Phase detector 20... Loop filter 30... Voltage controlled oscillator 40... - Prescaler 5
0...Variable frequency divider

Claims (1)

[Scope of Claims] 1. In a PLL frequency synthesizer that generates a signal with a frequency determined based on a frequency command signal using a PLL circuit with a predetermined loop natural frequency, the loop natural frequency of the PLL circuit is determined based on the predetermined loop natural frequency. A PLL frequency synthesizer comprising: PLL circuit performance changing means for switching to a value larger than the natural frequency; and frequency switching means for operating the PLL circuit performance changing means for a predetermined period when the frequency command signal is input. .