JPH04142814A - Pll circuit - Google Patents

Abstract

PURPOSE:To improve the spurious characteristic stably and effectively by providing a sampling signal generating means and a sample and hold means to the PLL circuit. CONSTITUTION:A sampling signal generating means 6 generates a sampling signal with the same period as that of a reference signal but different in phase, and a sample and hold means 7 samples and holds a DC voltage outputted from a loop filter 3 according to a sampling signal generated from the sampling signal generating means 6. Then the voltage subject to sampling and holding is fed to a voltage controlled oscillator 4 as its control voltage. Thus, the spurious characteristic is stably and effectively improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [First aspect of the invention] (Industrial Application Field) The present invention relates to a PLL circuit used for configuring a frequency synthesizer of a radio device, for example.

(Prior art) Generally, P L L (Phase 1 locked 1 o
The oscillator (op) circuit has a voltage controlled oscillator (VCO) 4 as shown in FIG.
PD) 2, and the phase comparator 2 compares the phase of the fed back oscillation output signal FS with the phase of the reference signal BS generated from the reference oscillator 1. Then, a control voltage C■ is generated from the loop filter 3 in accordance with the comparison output PO, and by supplying this control voltage CV to the VCO 4, a signal with a frequency corresponding to the control voltage value C■ is sent from the VCO 4. The MS is configured to oscillate.

Here, the phase comparator 2 is composed of, for example, a phase comparator section 2] and two switches 22H522L, as shown in FIG. For example, as shown in FIG. 11, when the phase of the feedback signal FS lags behind the phase of the reference signal BS, the phase comparator 21 outputs a comparison output POH having a pulse width corresponding to this delayed phase, and - When the phase of the force feedback signal FS leads the phase of the reference signal BS, a comparison output POL having a pulse width corresponding to this leading phase is output.

Each of the switches 22H and 22L is turned on only while the respective comparison outputs POH and POL are at "H" level. Further, the loop filter 3 is composed of resistors R1 and R2 and a capacitor CI.

The control voltage CV is the voltage value generated across the capacitor C, and this voltage value is the voltage value generated between each of the switches 22H, 22
It changes depending on the charge injection and removal performed on the capacitor C during the on-period of L.

(Problems to be Solved by the Invention) Ideally, this type of circuit is in a stable state when the phase of the reference signal BS and the phase of the feedback signal FS completely match. However, in reality, the switches 22H and 22L
There is a leak in capacitor C1 of loop filter 3,
In order to compensate for the drop in control voltage due to this leakage, the switch 22H22L periodically repeats an operation of closing for a very short period of time. Therefore, the control voltage CV does not become an ideal DC voltage, and an AC signal having the frequency of the reference signal as a fundamental wave component is superimposed. When the VCO 4 is controlled by such a control voltage Cv, sideband waves are generated in the oscillation output of the VCO 4 at intervals of the reference signal frequency fr, as shown in FIG. 12, for example.

In a mobile radio communication device that employs a multi-channel access method, if a local oscillation signal contains spurious components such as the sideband waves mentioned above, when receiving a desired radio channel, it may also receive radio waves from an adjacent radio channel. become,
Therefore, interference from other radio channels occurs on the desired radio channel, resulting in deterioration of reception sensitivity. Therefore, if you want to obtain high reception sensitivity in a mobile radio communication device, P
The LL circuit needs to generate a local oscillation signal with extremely few spurious components such as sidebands.

Therefore, conventionally, as shown in FIG. 13, for example, a low pass filter (LPF
)3] is inserted. This kind of LP
F31 is generally called a spurious removal filter, and is composed of a two-stage RC circuit. However,
Since the response characteristics of a PLL circuit are generally set to be determined by the time constant of loop filter 3, the cutoff frequency of the spurious removal filter needs to be set higher than that of loop filter 3. . Therefore, there is a limit to the amount of spurious components that can be removed by the spurious removal filter 31, and this is not an effective countermeasure.

On the other hand, as another spurious removal filter, twin-T
It has also been considered to use a filter 32 consisting of a circuit and insert this filter 32 between the loop filter 3 and the VCO 4 as shown in FIG. L4. This circuit is the 15th
As shown in the figure, it has a transmission zero point. By making this frequency fs coincide with fr, which is a spurious frequency, spurious components can be effectively reduced. However, since the transfer characteristics of the twin-T circuit are very steep, if fs deviates from fr, there is a risk that the spurious characteristics will deteriorate rapidly. For this reason, it is susceptible to variations in element values of resistors and capacitors, for example, and changes in element values due to temperature fluctuations, and is not an effective solution in reality.

In addition, as a method to improve spurious characteristics,
Attempts have also been made to lower the cutoff frequency of the loop filter 3, for example, without using a spurious removal filter. However, if the cutoff frequency of the loop filter 3 is lowered, the response of the PLL circuit loop becomes slower.
This creates a problem in that it takes a long time to switch wireless channels.

Therefore, the present invention is based on the information in the article [1], and can sufficiently reduce spurious components without being affected by variations in element values or temperature fluctuations, and without increasing wireless channel switching time. The purpose of the present invention is to provide a PLL circuit that can stably and effectively improve spurious characteristics.

[Configuration of the Invention (Means for Solving the Problems)] In order to achieve the above [1], the present invention feeds back the oscillation output of the voltage controlled oscillator to the phase comparator via a frequency divider, and performs this phase comparison. In the PLL circuit, the phase of the feedback signal and the reference signal are compared with each other in the oscillator, a DC voltage is generated from the loop filter according to the comparison output, and is supplied to the voltage controlled oscillator. Then, the sampling signal generating means generates a sampling signal having the same period and a different phase from the reference signal, and the sample holding means generates the DC voltage output from the loop filter using the sampling signal. The sampled and held voltage is sampled and held in accordance with a sampling signal generated by the signal generating means, and the sampled and held voltage is supplied to the voltage controlled oscillator as a control voltage.

(Function) As a result, according to the present invention, spurious components included in the output voltage of the loop filter are converted into DC components by being sampled by the sample and hold means in synchronization with a sampling signal having the same period as the reference signal. will be done. Since this DC component is suppressed by the feedback action of the PLL circuit, the spurious component is effectively removed as a result. Therefore, spurious characteristics are improved. Furthermore, since the sampling signal is generated based on a reference signal that is stable against temperature fluctuations, it is hardly affected by variations in element values or temperature fluctuations, and a stable spurious removal operation can be performed.

(Embodiment) FIG. 1 is a circuit block diagram showing the configuration of a PLL circuit in an embodiment of the present invention. In this figure, the same parts as those in FIG. 9 are given the same reference numerals and detailed explanations will be omitted.

The PLL circuit of this embodiment includes a delay circuit 6 as a sampling signal generating means and a sample hold circuit (S/H).
7. The delay circuit 6 is a reference oscillator 10
and the phase comparator 2. Further, the sample hold circuit 7 is provided between the loop filter 3 and the VCO 4.

FIG. 2 is a circuit diagram showing a specific configuration of the delay circuit 6 and sample hold circuit 7. As shown in FIG.

The delay circuit 6 consists of a D-type flip-flop 61, the reference f0 BS is supplied to the clock terminal, and the Q output or feedback input is supplied to the D input terminal. I want this D
2 for the reference signal BS by means of a type flip-flop 6].
A frequency dividing circuit is configured.

The Q output of this D-type flip-flop 61 is the reference signal B
It is supplied to the phase comparator 2 as S'. In addition, the Q output is sent to the sample hold circuit 7 as the sampling signal C8.
is supplied to

On the other hand, the sample hold circuit 7 includes switches 71 and 72 made of semiconductor switches, and a voltage holding capacitor C71.
, C72, buffer circuits 74 and 75, and inverter 7
It consists of 3. The switches 71 and 72 are operated by the sampling signal C8 generated from the delay circuit 6 and the inverted sampling signal C8' obtained by logically inverting the sampling signal C8 by the inverter 73, and when the sampling signal is at the "H" level, sometimes"
It is in the "closed" state, and it is in the "open" state when it is at the "L" level.

Next, the operation of the circuit configured as above will be explained.

The reference oscillator 10 generates a reference signal BS having twice the frequency of the frequency oscillator 1 shown in FIG. 9 above. This reference signal BS is applied to the D-type flip-flop 61 of the delay circuit 6.
As shown in FIG. 3, this phase comparator 2 outputs a Q output with a frequency of 1/2 and a duty of 50% relative to the reference signal BS as a new reference signal BS'.
Supplied as. In the phase comparator 2, as shown in FIG. 11, the phases of the reference signal BS' and the oscillation output signal FS fed back from the VCO 4 via the variable frequency divider 5 are compared, and the phase difference corresponds to the phase difference. A DC voltage cV is output from the loop filter 3. At this time, the phase comparator 2 outputs a phase difference pulse PO at a period corresponding to the reference signal BS', as shown in FIG. 3, for example, in order to compensate for leakage from the capacitor to the noise C1 even in the steady state. Therefore, the above-mentioned DC voltage c■ has the above-mentioned phase difference pulse P as shown in FIG.

The alternating current signal component caused by this is superimposed, and this alternating current component causes spurious generation.

On the other hand, the delay circuit 6 generates a sampling signal C8 having a frequency of 1/2 and a phase shifted by 1800 with respect to the reference signal BS. Then, in the sample-and-hold circuit 7, the switches 72 and 71 each perform a switching operation in response to the sampling signal C8 and its inverted signal C8'.

For example, the rising time t of the reference signal BS'.

In , since the sampling signal C8 falls,
In response to this, switch 72 becomes open.

Further, the switch 72 operates at the above t due to the delay time of the inverter 73. The closed state is reached at time t1 after a minute delay.

Therefore, in the period until the next rising timing t2 of the sampling signal C8, the output voltage CV of the loop filter 3 is either supplied to the capacitor C71 or
4 is supplied with the charging voltage C72 of the capacitor C72 as a control voltage. That is, during this period, VCO
4, the AC component included in the output voltage Cv of the loop filter 3 is not transmitted.

Next, at time t2 when the reference signal BS' falls, that is, delayed by 1/2 period from the rise, the switch 72 is closed. This item, roof filter 3
The output voltage CV is supplied to a capacitor C72 via a capacitor C71. However, after a short time t3, the switch 7 is opened. Therefore, the charging voltage E1 of the capacitor C71 maintains the value at this time t. That is, the output voltage CV of the loop filter 3 is sampled during the minute period from t2 to t in 1. This sampled voltage value is held in the capacitor C72.

Similarly, when the reference signal BS' rises, the switch 72 is opened and then the switch 73 is closed. Therefore, the change in the potential E of the capacitor C71 caused by closing the switch 71, that is, the change in the potential E of the capacitor C71, that is, the loop filter 3
Voltage fluctuations due to alternating current components contained in the output voltage CV of the VCO 4 do not appear as fluctuations in the potential C' of the capacitor C72, and therefore the control voltage CV' of the VCO 4 is kept at a constant value.

On the other hand, when the reference signal BS' falls, the switch 7
2 is in the closed state, and immediately after that, the switch 71 is in the open state. Therefore, the output voltage CV of the Lube filter 3 is sampled during this minute period, and this sampled value is held in the capacitor C72 and supplied to the VCO 4 as the control voltage CV'.

As described above, in this embodiment, the sampling and holding circuit 7 is used to sample the output voltage Cv of the loop filter 3 at the cycle of the reference signal BS', and this sampled voltage is held until the next sampling point. Since the voltage is supplied to the VCO4 as the control voltage CV', the AC component synchronized with the reference signal BS' contained in the output voltage C■ of the loop filter 3 can be converted into a DC value, and as a result, the AC component can be removed. can do.

This effect will be further explained using FIG. 4. Note that, in order to facilitate understanding, the figure shows a case where a sine wave having the same period as the reference signal BS is used. This sine wave is converted into a sampling signal C8I, C32, C33 having the same period as that period.
When sampling using , any sampling signal C8I.

Even when C32 and C33 are used, if the period is equal to the period of the sine wave, the sampled voltage value SEI,
SE2. As shown in FIG. 5, SE3 becomes a constant value. That is, the sine wave alternating current [,) appears only as a direct current value in the sampling voltage, and no alternating current component appears at all. In other words, the AC component has been removed.

Therefore, according to the PLLM path of this embodiment, V
CO4 can be driven, thereby making it possible to transmit and receive wireless signals with extremely little spurious.

Moreover, in this embodiment, the output voltage CV of the loop filter 3
Since sampling is performed at the falling edge of the reference signal BS', that is, at a 1/2 period shift from the rising edge, even if the phase of the sampling signal varies slightly, the reference signal component included in the output voltage CV Sampling can be performed in a state that contains as little as possible.

That is, the reference signal component included in the output voltage CV of the loop filter 3 is the reference signal BS' as shown in FIG.
Occurs near the rising edge of . Therefore, when sampling the output voltage C■ using, for example, the sampling signal C8I of FIG. 6, sampling will be performed at a position where the reference signal component changes rapidly.

Therefore, even if the phase of the sampling signal C3I changes slightly, the change appears as a large change in the sampling voltage, and eventually the fundamental signal component cannot be completely removed.

On the other hand, if the sampling signal C82 in FIG. 6, which is generated at the falling edge of the reference signal BS', is used, the amount of change in the fundamental signal component is small when the falling edge of the reference signal BS' approaches 1. Even if the phase of the signal C82 changes minutely, the change does not appear as a large change in the sampling voltage.

Further, the transfer characteristic of the sample and hold circuit 7 is twin
-It has a transmission zero point like the T circuit. However, the frequency at which the transmission zero point occurs is the sampling frequency, and this sampling frequency is the reference signal B generated from the reference oscillator 10.
Since it is generated based on S, it is hardly affected by variations in element values or temperature fluctuations. Therefore, extremely stable spurious removal can be achieved.

Further, according to the present embodiment, the timing of the sampling signal C8' for driving the switch 71 located on the previous stage among the switches 7] and 72 of the sample and hold circuit 7 is changed by passing the timing of the sampling signal C8' through the inverter 73. Since the sampling signal C8 for driving 72 is delayed by a minute time, the switches 71 and 72 are not closed at the same time at the rising edge of the reference signal BS', and the switch 72 is always open. Alternatively, the switch 71 may be closed after the time is reached. Therefore, the output voltage CV of the loop filter is
Even if it is momentary, it is possible to prevent a problem in which the signal passes through the switches 71 and 72 and is supplied directly to the VCO 4.

Note that the present invention is not limited to the above embodiments. For example, when the reference signal BS has a duty of 50%, the sampling signal generating means may be configured using an inverter 62 as shown in FIG. However, in this case, the frequency of the reference signal BS does not need to be set to twice the frequency of the reference signal BS' supplied to the phase shift comparator 2, and may be the same frequency.

Further, the reference signal is often created by dividing the high frequency output of the reference oscillator using a frequency divider. In this case, as a sampling signal generation circuit, for example, a frequency divider 6 as shown in FIG.
The sampling signal C8 may be generated by shifting the output signal BS' of No. 3 using the shift register 64.

With this circuit, the phase of the sampling signal C8 can be controlled relatively freely by changing the number of stages of the shift register 64 or appropriately dividing the output signal of the reference oscillator 1 with a frequency divider and using it as a shift clock. can be easily set. In addition, in this case, the phase of the sampling signal can be set at any position other than around the rising edge of the reference signal, in addition to setting it at a point shifted by /2 from the rising edge of the reference signal. Good too.

In addition, the circuit configuration of the sampling signal generating means and the sample holding means, the type of device to which the PLLH path is applied, etc. can be modified in various ways without departing from the spirit of the present invention.

[Effects of the Invention] As detailed above, according to the present invention, a sampling signal generation means and a sample hold means are newly provided, and the sampling signal generation means generates a sampling signal having the same period and a different phase from the reference signal. The sampling and holding means samples and holds the DC voltage output from the loop filter according to the sampling signal generated from the sampling signal generating means, and the sampled and held voltage is used as the control voltage. By supplying the voltage to the voltage controlled oscillator, it is not affected by variations in element values or temperature fluctuations, and it is possible to sufficiently reduce spurious components without increasing the wireless channel switching time. PL that can stably and effectively improve
L circuit can be provided.

]9

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing the configuration of a PLL circuit in an embodiment of the present invention, FIG. 2 is a circuit configuration diagram showing the main part configuration of the PLL circuit, and FIGS. 3 to 6 are block diagrams of the PLL circuit. The f6 waveform diagram, FIG. 7, and FIG. 8 used to explain the operation are circuit diagrams showing other different embodiments of the present invention, and FIG.
The figure is a circuit block diagram showing the basic configuration of a conventional PLL circuit, FIG. 10 is a circuit diagram showing the main part configuration of the PLL circuit, FIG. Figure 12 is a characteristic diagram for explaining the problems of the conventional PLL circuit, Figures 13 and 14 are circuit diagrams showing the main part configurations of different conventional PLL circuits, respectively.
This figure is a characteristic diagram for explaining the problem of the circuit shown in FIG. 14. 1.10... Reference oscillator, 2... Phase comparator, 3...
・Loop filter, 4...Voltage controlled oscillator (VCO)
5... Variable frequency divider, 6... Delay circuit, 7...
Sample hold circuit, 71.72... switch, 7
3... Inverter, 74.75... Buffer circuit,
BS, BS'...Reference signal, FS...Feedback signal, P
O... Phase comparison output, cs, cs'... Sampling signal, C ■... Output voltage of loop filter, CV'
... Output voltage (control voltage) of the sample and hold circuit.

Claims (2)

[Claims] (1) The oscillation output of the voltage controlled oscillator is fed back to the phase comparator via the frequency divider, the phase of the feedback signal is compared with the reference signal in this phase comparator, and the DC current is output from the loop filter according to the comparison output. In a PLL circuit that generates a voltage and supplies it to the voltage controlled oscillator, a sampling signal generating means for generating a sampling signal having the same period and a different phase as the reference signal, and between the loop filter and the voltage controlled oscillator. A sample hold is inserted into the loop filter to sample and hold the DC voltage output from the loop filter according to the sampling signal generated from the sampling signal generating means, and supplies the sampled and held voltage to the voltage controlled oscillator as a control voltage. A PLL circuit characterized by comprising means. (2) The PLL circuit according to claim 1, wherein the sampling signal generating means generates a sampling signal whose phase is shifted by 180 degrees with respect to the reference signal.