KR0117251Y1 - Circuit for generating synchronization clocks - Google Patents

Abstract

The present invention relates to a European type digital trunk circuit, and to a synchronous clock generation circuit of the European type digital trunk circuit to accurately output the various clocks required by the European type digital trunk circuit.

According to the present invention, the clock required by the digital trunk interface circuit part can be output accurately and the clock can be stably output without being influenced by external environment change.

Description

Synchronous Clock Generation Circuit of European Digital Trunk Circuit

1 is a block diagram of a synchronous clock generation circuit of a conventional European digital trunk circuit

2 is a block diagram of a synchronous clock generation circuit of a European digital trunk circuit according to the present invention

3 is a detailed circuit diagram of the clock generator shown in FIG.

4 is an operation timing diagram of a clock generator.

* Description of the symbols for the main parts of the drawings *

1 trunk interface circuit part 4 phase comparison unit

5: low pass filter 6: constant voltage supply

7: voltage controlled oscillator 8: power noise canceller

9: divider 10: clock generator

The present invention relates to a European digital trunk circuit, and more particularly, to a synchronous clock generation circuit of a European digital trunk circuit to accurately output various clocks required by the European digital trunk circuit.

The synchronous clock generation circuit of the conventional European digital trunk circuit is composed of a digital trunk interface circuit section 1, a digital PLL circuit section 2 and an oscillation section 3 as shown in FIG. The digital trunk interface circuit unit 1 extracts an 8 KHz clock from the signal supplied from the partner station and outputs it to the digital PLL circuit unit 2 side. The digital PLL circuit section 2 consists of a single chip, which operates according to the 16.384 MHz clock supplied from the oscillation section 3 and is required by the digital trunk interface circuit section 1 according to the 8 KHz clock supplied from the digital trunk interface circuit section 1. 4 MHz clock, 2 MHz clock, and frame pulses ) Is outputted to the digital trunk interface circuit unit 1 side.

Since the synchronous clock generation circuit of the conventional digital trunk circuit uses a single chip digital PLL circuit section 2, if any one of the input clocks is missed, the center frequency cannot be adjusted so that a precise clock cannot be output. There was a problem that the clock can not be stably output due to the influence of external environment changes such as temperature changes.

The present invention was devised to solve the above problems, and it is a European method to output the clock precisely required by the digital trunk interface circuit part and to stably output the clock without being affected by external environment changes. It is an object of the present invention to provide a synchronous clock generating circuit of a digital trunk circuit.

In order to achieve the above object, the present invention extracts and outputs the clock of the first frequency from the signal supplied from the counterpart switching station, and the clock and the frame pulse of the second and third frequencies ( In the European-style digital trunk circuit having a trunk interface circuit section 1 operated by), the clock of the first frequency supplied from the trunk interface circuit section 1 to one input terminal and the first frequency supplied to the other input terminal A phase comparator 4 for outputting a clock according to the result of the phase comparison between the clocks, a low pass filter 5 for low-pass filtering the clock from the phase comparator 4, and a low pass filter 5 supplied from the low pass filter 5 A voltage-controlled oscillator 7 for outputting a clock of the fourth frequency in accordance with the clock, and a constant-voltage supply 6 for maintaining a constant level of a potential of the clock supplied from the low-pass filter 5 to the voltage-controlled oscillator 7 side. ), A power source noise remover 8 for removing noise of power supplied to the voltage controlled oscillator 7 side, and a first output terminal according to a clock of a fourth frequency supplied from the voltage controlled oscillator 7 Outputs the clock of the first frequency to the phase comparator 4 side, and outputs the clock of the fifth frequency to the system side through the second output terminal, and the clock and the synchronization signal of the second frequency through the third output terminal ( ) And a clock and a synchronizing signal of the second frequency supplied from the third output terminal of the frequency divider 9 Clock and frame pulses of the second and third frequencies to the trunk interface circuit part 1 according to It provides a synchronous clock generating circuit of the European-style digital trunk circuit, characterized in that it comprises a clock generator (10) for outputting.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram of a synchronous clock generation circuit of a European digital trunk circuit according to the present invention, FIG. 3 is a detailed circuit diagram of the clock generator shown in FIG. 2, and FIG. 4 is an operation timing diagram of the clock generator.

As shown in FIG. 2, the synchronous clock generating circuit of the European-type digital trunk circuit of the present invention includes a trunk interface circuit part 1, a phase comparator 4, a low pass filter 5, a constant voltage supply part 6, and a voltage. The control oscillator 7, the power supply noise canceling unit 8, the divider 9 and the clock generator 10 are connected to each other. The trunk interface circuit unit 1 extracts an 8 KHz clock from the signal supplied from the partner station and outputs it to the phase comparison unit 4. The phase comparison section 4 compares the phase of the 8KHz clock supplied from the trunk interface circuit section 1 with the 8KHz clock supplied from the divider section 9, and outputs the clock to the low pass filter 5 side. Numeral 5 low-passes the clock supplied from the phase comparator 4 and outputs it to the voltage controlled oscillator 7 side. The constant voltage supply unit 6 maintains a constant voltage level input to the voltage controlled oscillator 7, and the voltage controlled oscillator 7 generates a clock of 16.384 MHz according to the clock supplied from the low pass filter 5. Output to the dispensing part 9 side. The frequency division unit 9 divides the clock of 16.384 MHz supplied from the voltage controlled oscillation unit 7 to generate clocks and synchronization signals of 8 KHz, 8 MHz and 4 MHz. 8KHz clock is outputted to the phase comparator 4 side, and 8MHz clock is outputted to the system side as the system clock, and 4MHz clock and synchronization signal ( ) Is outputted to the clock generator 10 side. The clock generator 10 has a clock of 4 MHz and a synchronization signal (supplied from the divider 9). Clock and frame pulses (4 MHz and 2 MHz) ), And the power supply noise removing unit 8 removes the noise of the power supply supplied to the voltage controlled oscillation unit 7.

The clock generator 10 is connected to the D flip-flops 15 to 18, the NOR gates 19 and 20, and the inverter 21 as shown in FIG. 3. The D flip-flop 15 uses a clock of 2 MHz as shown in FIG. 4B according to the clock of 4 MHz as shown in FIG. 1) side, the output stage (Q) outputs a clock of 2MHz and output stage ( Is connected to the input terminal D, and the output of the NOR gate 19 is connected to the reset terminal R. The D flip-flop 16 has a synchronization signal ( ) Is input and the clock stage CK is input to the clock of 4MHz through the inverter 21 and the output stage ( ) Is connected to the input terminal of the NOR gate 19 and to the input terminal D of the D flip-flop 17. In the D flip-flop 17, a clock of 4 MHz is input to the clock terminal CK and an output terminal ( ) Is connected to one input terminal of the NOR gate 19, the input terminal D is connected to the other input terminal of the NOR gate 19, and the output terminal Q is connected to the input terminal of the NOR gate 20, and at the same time, the D flip-flop 18 Is connected to the input terminal (D). In the D flip-flop 18, a clock of 4 MHz is input to the clock stage CK and an output stage ( ) Is connected to one input terminal of the NOR gate 20 and the input terminal D is connected to the output terminal Q of the D flip-flop 17 and the other input terminal of the NOR gate 20. The NOR gate 20 has an output terminal Q of the D flip-flop 17 and an output terminal of the D flip-flop 18 ( Flame pulses as shown in FIG. 4C according to the clock supplied from ) Is outputted to the trunk interface circuit unit 1 side, and the clock of 4 MHz is immediately outputted to the trunk interface circuit unit 1 side. As can be seen in Figure 4, a 2 MHz clock transitions from a low level to a high level and at the same time a frame pulse ( ) Becomes low level, the synchronization is performed for each frame of data input and output to the trunk interface circuit (1).

As described above, the present invention employs an analog PLL circuit composed of a phase comparator 4, a low pass filter 5, a voltage controlled oscillator 7, and a divider 9, which is required by the digital trunk interface circuit. It outputs the clock precisely and at the same time, it outputs the clock stably without being affected by the external environment change.

Claims (1)

The clock of the first frequency is extracted from the signal supplied from the counterpart switching station, and the clock and the frame pulse of the second and third frequencies ( In the European-style digital trunk circuit having a trunk interface circuit section (1) operated by Phase comparison unit 4 for outputting a clock according to a result of the phase comparison between the clock of the first frequency supplied to the other input terminal and the clock of the first frequency supplied from the trunk interface circuit unit 1, the phase comparison A low pass filter 5 for low-pass filtering the clock from the unit 4, a voltage controlled oscillator 7 for outputting a clock of the fourth frequency in accordance with the clock supplied from the low pass filter 5, and the low pass filter (5) from the constant voltage supply part 6 which keeps the potential level of the clock supplied to the voltage-controlled oscillator 7 side constant, and a power supply noise removing noise of the power supplied to the voltage-controlled oscillator 7 side. Rejection 8 outputs the clock of the first frequency to the phase comparator 4 through the first output terminal according to the clock of the fourth frequency supplied from the voltage controlled oscillator 7 and to the system side through the second output terminal. A clock of the fifth frequency is output and the clock and the synchronization signal of the second frequency are output through the third output terminal. ) And a clock and a synchronizing signal of the second frequency supplied from the third output terminal of the frequency divider 9 Clock and frame pulses of the second and third frequencies to the trunk interface circuit part 1 according to And a clock generator (10) for outputting the synchronous clock generation circuit of the European digital trunk circuit.