KR940018232U - Synchronous clock generation circuit of European digital trunk circuit - Google Patents

Synchronous clock generation circuit of European digital trunk circuit

Info

Publication number
KR940018232U
KR940018232U KR2019920027342U KR920027342U KR940018232U KR 940018232 U KR940018232 U KR 940018232U KR 2019920027342 U KR2019920027342 U KR 2019920027342U KR 920027342 U KR920027342 U KR 920027342U KR 940018232 U KR940018232 U KR 940018232U
Authority
KR
South Korea
Prior art keywords
circuit
clock generation
synchronous clock
digital trunk
european digital
Prior art date
Application number
KR2019920027342U
Other languages
Korean (ko)
Other versions
KR0117251Y1 (en
Inventor
방진원
Original Assignee
엘지정보통신주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘지정보통신주식회사 filed Critical 엘지정보통신주식회사
Priority to KR92027342U priority Critical patent/KR0117251Y1/en
Publication of KR940018232U publication Critical patent/KR940018232U/en
Application granted granted Critical
Publication of KR0117251Y1 publication Critical patent/KR0117251Y1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
KR92027342U 1992-12-29 1992-12-29 Circuit for generating synchronization clocks KR0117251Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR92027342U KR0117251Y1 (en) 1992-12-29 1992-12-29 Circuit for generating synchronization clocks

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92027342U KR0117251Y1 (en) 1992-12-29 1992-12-29 Circuit for generating synchronization clocks

Publications (2)

Publication Number Publication Date
KR940018232U true KR940018232U (en) 1994-07-30
KR0117251Y1 KR0117251Y1 (en) 1998-06-01

Family

ID=19348506

Family Applications (1)

Application Number Title Priority Date Filing Date
KR92027342U KR0117251Y1 (en) 1992-12-29 1992-12-29 Circuit for generating synchronization clocks

Country Status (1)

Country Link
KR (1) KR0117251Y1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102212726B1 (en) 2020-08-31 2021-02-04 김보화 Electric cooker with heat diffusion structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102212726B1 (en) 2020-08-31 2021-02-04 김보화 Electric cooker with heat diffusion structure

Also Published As

Publication number Publication date
KR0117251Y1 (en) 1998-06-01

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Legal Events

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A201 Request for examination
E701 Decision to grant or registration of patent right
REGI Registration of establishment
FPAY Annual fee payment

Payment date: 20070129

Year of fee payment: 10

EXPY Expiration of term