JPH07209379A - Semiconductor test device synchronized with outside clock - Google Patents

Abstract

PURPOSE:To provide a semiconductor tester that uses the clock signal generated from a device to be tested after it has been stabilized by removing jitter. CONSTITUTION:A frequency divider A 11, a phase detection circuit 12, a loop filter 13, VCO(Voltage Controlled Oscillator) 14 and another frequency divider B 16 which make input of a clock signal 21 generated from a device to be tested are provided. In addition, a test cycle production device 15 and an interleave circuit 18 are provided. An operation clock output from VCO 14 is input to the test cycle production device 15, test cycle signals 22 are output, distributed to device inside circuits and feedback is performed for the phase detection circuit 12 through the frequency divider B 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit in a semiconductor tester for receiving a clock signal from the outside to remove jitter and synchronizing it with an internal clock.

[0002]

2. Description of the Related Art FIG. 3 shows a prior art example. In the semiconductor test equipment, the operation clock is generated inside the equipment, a test pattern is generated in synchronization with the clock and applied to the device under test, and the output signal from the device under test is compared with the expected value pattern. Was. Since all the internal operations of the device operate in synchronization with the clock, there is no problem that jitter occurs. On the other hand, some devices generate clocks themselves. In this case, a method of operating the test apparatus by using the device clock itself can be considered. But according to this method,
It is necessary to synchronize the device clock with the clock of the test apparatus. However, since the two clocks are completely asynchronous, there is a problem that the clock taken in as shown in FIG. 4 causes jitter.

[0003]

The present invention has been made in view of this problem, and an object thereof is to provide a circuit in which jitter does not occur even when an external clock is used.

[0004]

[Means for Solving the Problems]

(Claim 1) A clock generated by a device under test is taken in from an input terminal and a frequency divider for dividing the frequency by 1 / N is provided, and an output signal of the frequency divider and an output signal of another frequency divider are provided. A phase detector having inputs and is provided. A loop filter having the output of the phase detector as an input signal is provided, and a voltage control oscillator (hereinafter referred to as VCO) having the output of the loop filter as an input is provided. The output signal of the VCO is used as the input signal of the test cycle generator, the output signal of the VCO is distributed to the other circuits of the test apparatus, and the output of the test cycle generator is used as the input 1
A frequency divider for dividing / N is provided, and the output of the frequency divider is
As described above, it is one input of the phase detector.

(Claim 2) A test frequency generator capable of setting a frequency in frequency units is provided, and a frequency divider for dividing the output signal by 1 / N is provided. A phase detector that receives the output signal of another frequency divider is provided. A loop filter having the output of the phase detector as an input signal is provided, and a VCO having the output of the loop filter as an input is further provided. The output signal of the VCO is used as the input signal of the test cycle generator, the output signal of the VCO is distributed to the other circuits of the test apparatus, and the output of the test cycle generator is used as the input to perform 1 / N frequency division. A frequency divider is provided, and the output of the frequency divider is one input of the phase detector as described above.

[0006]

Function: Frequency divider A, phase detector, loop filter, V
Due to the interaction between CO and the frequency divider B, one PLL (Ph
ase Locked Loop) circuit is formed, and the clock signal that is fetched asynchronously is used as a stabilized operation clock. That is,
It serves to provide an operating clock without jitter components.

[0007]

EXAMPLE A clock signal 21 input from the device under test 19 to the input terminal 10 is measured for its cycle using a counter, and its value is set in the test cycle generating circuit 15 in advance. The difference between claim 1 and claim 2 is that the clock generating means is the frequency generator 20 itself or the clock generated by the device under test 19. Therefore, the following description is common. Next, the clock signal 21 before being input to the frequency divider A11 is also input to the interleave circuit 18 as a clock for synchronizing input / output with the device under test 19.

It is assumed that the frequency of the input asynchronous clock signal 21 is f. A frequency divider A · 11 for dividing the clock signal 21 into 1 / N is provided and input to the frequency divider A · 11. Therefore, the output of the frequency divider A · 11 is f1 = f / N. Next, the phase detector 12 having two input terminals is provided. One input signal is f1, and the frequency signal of f2 is input to the other input terminal. The phase detector 12 outputs the frequency difference between f1 and f2, and the loop filter 13 uses this frequency difference as an input signal and converts it into a corresponding voltage signal. The VCO 14 converts the converted voltage signal into a frequency signal, which is used as the operation clock 23 of the test apparatus.

The test cycle generator 15 receives the operation clock 23 as an input, generates a set test cycle signal 22 for use in the internal circuit of the test apparatus, and inputs it to the frequency divider B.multidot.16. A frequency signal of f2 after being divided by / N is input to the other input terminal of the phase detector 12. As a result, the PLL circuit is formed, and the operation clock 23 that stabilizes the clock signal 21 that is asynchronously fetched
To The interleave circuit 18 applies the pattern signal to the device under test 19 and the device under test 1
When the output signal from 9 is received, the test period signal 22 is changed to the clock signal 21 and the clock signal 21 is changed to the test period signal 22 in order to reliably deliver the signal.
Change the clock between and.

[0010]

Since the present invention is constructed as described above,
The following effects are achieved. It has been possible to provide a circuit in which jitter does not occur even when an external clock is used. Therefore, the test apparatus can be operated by the actual operation clock of the device under test 19, and the clock can be set in frequency units, so that it is possible to cope with the case where a minute frequency resolution is required, and its effect. The field is large.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment.

FIG. 2 is a block diagram showing a second embodiment.

FIG. 3 is a block diagram showing a conventional technique.

FIG. 4 is a diagram illustrating jitter.

[Explanation of symbols]

 11 Frequency Divider A 12 Phase Detector 13 Loop Filter 14 Voltage Controlled Oscillator (VCO) 15 Test Cycle Generator 16 Frequency Divider B 17 Pattern Comparison Unit / Pattern Generation Unit 18 Interleave Circuit 19 Device Under Test (DUT) 20 Test frequency generator 21 Clock signal 22 Test period signal 23 Operation clock

Claims (2)

[Claims] 1. A frequency divider A (11) which receives a clock signal (21) of a device under test (19) as an input and which receives the clock signal (21) as an input, a frequency divider A (11) and a frequency divider B (16). ) And an output signal of the phase detector (12) which outputs the frequency difference between the two input signals, and a loop filter which inputs the output of the phase detector (12) and converts the frequency into a voltage signal. (13), a voltage controlled oscillator (14) that receives the output signal of the loop filter (13), a frequency divider B (16) that receives the test period signal, and a test period signal (22). A semiconductor test apparatus synchronized with an external clock, comprising: an interleave circuit (18) having a clock signal (21) as an input. 2. A test frequency generator (20) capable of generating a clock signal in frequency units, and a frequency divider A (11) having a clock signal (21) as an input.
And a phase detector (12) which inputs the output signals of the frequency divider A (11) and the frequency divider B (16) and outputs a frequency difference between the two input signals, and a phase detector (12) Filter (13) for converting the frequency signal into a voltage signal by using the output signal of the input signal, a voltage controlled oscillator (14) for receiving the output voltage of the loop filter (13), and a test period signal (22) Frequency divider B (16) with input
And a test signal (22) and a clock signal (21) as an input, and an interleave circuit (18).